Commit Graph

85 Commits

Author SHA1 Message Date
Chad Rosier 3c03dee1d1 [AArch64] Add support for NEON scalar extract narrow instructions.
llvm-svn: 192971
2013-10-18 14:03:36 +00:00
Kevin Qin f22bf50443 Implemented aarch64 SIMD copy related ACLE intrinsic :
vget_lane, vset_lane, vcopy_lane, vcreate, vdup_n, vdup_lane, vmov_n.

llvm-svn: 192411
2013-10-11 02:34:30 +00:00
Chad Rosier 0babda4b9c [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point
convert instructions.

llvm-svn: 192232
2013-10-08 20:43:46 +00:00
Jiangning Liu b96ebac02b Implement aarch64 neon instruction set AdvSIMD (Across).
llvm-svn: 192029
2013-10-05 08:22:55 +00:00
Jiangning Liu 4617e9dc85 Implement aarch64 neon instruction set AdvSIMD (3V elem).
llvm-svn: 191945
2013-10-04 09:21:17 +00:00
Jiangning Liu 1bda93a252 Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL

llvm-svn: 190289
2013-09-09 02:21:08 +00:00
Hao Liu b1852eed38 Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshr$
 and 4 convert instructions:
      scvtf,ucvtf,fcvtzs,fcvtzu

llvm-svn: 189926
2013-09-04 09:29:13 +00:00
Kevin Qin c076d0682b mangle aarch64 Neon ACLE scalar instrinsic name with BHSD suffix.
llvm-svn: 189574
2013-08-29 07:55:15 +00:00
Hao Liu 4efa1402fe Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions
llvm-svn: 188452
2013-08-15 08:26:30 +00:00
Tim Northover 2fe823a6c3 AArch64: initial NEON support
Patch by Ana Pazos

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

llvm-svn: 187568
2013-08-01 09:23:19 +00:00
Michael Gottesman 1169a52c83 [NeonIntrinsicTestEmitter] vld1/vst1 do not require the :64 hint.
llvm-svn: 184786
2013-06-24 21:25:39 +00:00
Michael Gottesman c6b5e56c19 [NeonIntrinsicTestEmitter] Fix incorrect FileCheck pattern where we were expecting a ',' prefix to alignment hints.
llvm-svn: 184785
2013-06-24 21:25:37 +00:00
Michael Gottesman d95c49a91c [NeonIntrinsicTestEmitter] Add requirement to arm neon intrinsic tests for the feature long_tests.
This will prevent the tests from running on normal make check. You will need to
actually pass in --param run_long_tests=true to LIT in order to run these.

llvm-svn: 184784
2013-06-24 21:25:34 +00:00
Jim Grosbach d10f1c04aa ARM: Improve codegen for vget_low_* and vget_high_ intrinsics.
These intrinsics use the __builtin_shuffle() function to extract the
low and high half, respectively, of a 128-bit NEON vector. Currently,
they're defined to use bitcasts to simplify the emitter, so we get code
like:
uint16x4_t vget_low_u32(uint16x8_t __a) {
  return (uint32x2_t) __builtin_shufflevector((int64x2_t) __a,
                                              (int64x2_t) __a,
                                              0);
}

While this works, it results in those bitcasts going all the way through
to the IR, resulting in code like:
  %1 = bitcast <8 x i16> %in to <2 x i64>
  %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32>
  %zeroinitializer
  %3 = bitcast <1 x i64> %2 to <4 x i16>

We can instead easily perform the operation directly on the input vector
like:

uint16x4_t vget_low_u16(uint16x8_t __a) {
  return __builtin_shufflevector(__a, __a, 0, 1, 2, 3);
}

Not only is that much easier to read on its own, it also results in
cleaner IR like:

  %1 = shufflevector <8 x i16> %in, <8 x i16> undef,
                     <4 x i32> <i32 0, i32 1, i32 2, i32 3>

This is both easier to read and easier for the back end to reason
about effectively since the operation is obfuscating the source with
bitcasts.

rdar://13894163

llvm-svn: 181865
2013-05-15 02:40:04 +00:00
Michael Gottesman 3508389233 [neonemitter tests] Change triple of emitted tests to thumbv7s to match the target cpu being swift. Also specify the target-abi to apcs-gnu.
llvm-svn: 180233
2013-04-25 00:10:14 +00:00
Michael Gottesman 6cd3e560fd [6/6] ARM Neon Intrinsic Tablegen Test Generator.
Added GenerateChecksForIntrinsic method to generate FileCheck patterns
for generated arm neon tests.

Reviewed by Bob Wilson.

llvm-svn: 179644
2013-04-16 23:00:26 +00:00
Michael Gottesman 1d712fe52d [5/6] ARM Neon Intrinsic Tablegen Test Generator.
Changed the test generation target cpu type from cortex-a9 to swift.

Reviewed by Bob Wilson.

llvm-svn: 179642
2013-04-16 22:55:01 +00:00
Michael Gottesman d44c8f7d20 [4/6] ARM Neon Intrinsic Tablegen Test Generator.
Added code to NeonEmitter::runTests so that GenTest gets all of the needed
arguments to invoke the neon test generation methods.

Reviewed by Bob Wilson.

llvm-svn: 179640
2013-04-16 22:48:52 +00:00
Michael Gottesman 095c58f1c4 [3/6] ARM Neon Intrinsic Tablegen Test Generator.
Refactored out the method InstructionTypeCode from MangleName for use in
further patches which perform neon tablegen test generation.

Reviewed by Bob Wilson.

llvm-svn: 179636
2013-04-16 22:07:30 +00:00
Michael Gottesman fc89cc2a91 [2/6] ARM Neon Intrinsic Tablegen Test Generator.
This patch causes OpInst records to be silently identified with their Non-Op
inst counterparts so that the same test generation infrastructure can be used to
generate tests.

Reviewed by Bob Wilson.

llvm-svn: 179628
2013-04-16 21:18:42 +00:00
Bob Wilson 2b59395d0e Define Neon intrinsics as "static inline" to avoid warning. rdar://13108414
We had been defining Neon intrinsics as "static" with always_inline attributes.
If you use them from an extern inline function, you get a warning, e.g.:

static function 'vadd_u8' is used in an inline function with external linkage

This change simply adds the inline keyword to avoid that warning.

llvm-svn: 179406
2013-04-12 20:17:20 +00:00
Joerg Sonnenberger 691a16b444 Don't throw exceptions in clang-tblgen by switching to PrintFatalError.
Add locations in a number of places, where they are available for free.

llvm-svn: 166691
2012-10-25 16:37:08 +00:00
Richard Smith f44b8ee52e Placate the mingw32 buildbot by suffixing 64-bit constants with ULL.
llvm-svn: 161831
2012-08-14 03:55:16 +00:00
Richard Smith 7d6d47b862 Fix undefined behavior (and wrong code, as far as I can tell) in NEON builtin
tablegen code, found by -fcatch-undefined-behavior. I would appreciate if
someone more familiar with the NEON code could point me in the direction of how
to write a test for this. We appear to have essentially no test coverage
whatsoever for these builtins.

llvm-svn: 161827
2012-08-14 01:28:02 +00:00
Jim Grosbach cc6b1816fd TableGen: Remove extraneous \ character from arm_neon.h definitions.
llvm-svn: 161244
2012-08-03 17:30:46 +00:00
Jakob Stoklund Olesen 995e0e13fa Make clang-tblgen backends functions instead of TableGenBackends.
Get rid of a bunch of header files. TableGen output should be unaffected.

Patch by Sean Silva!

llvm-svn: 158388
2012-06-13 05:12:41 +00:00
Jim Grosbach 6acd46f5e9 TableGen: Remove extraneous '\' at EOL in generated tests.
llvm-svn: 157700
2012-05-30 18:18:29 +00:00
Jim Grosbach 6f855e3024 ARM: Support marking intrinsic definitions as 'unavailable'
llvm-svn: 156490
2012-05-09 18:17:30 +00:00
David Blaikie 8a40f700e6 Remove unreachable code in Clang. (replace with llvm_unreachable where appropriate or when GCC requires it)
llvm-svn: 148292
2012-01-17 06:56:22 +00:00
Bob Wilson bd646de67f Relax type checking for a few Neon intrinsics. <rdar://problem/10538555>
Not long ago, I tightened up the type checking for pointer arguments of
Neon intrinsics to match the specifications provided by ARM.  One consequence
was that it became impossible to access the unaligned versions of a few
Neon load/store operations.  Since there are just a few of these intrinsics
where it makes a difference, I think it's better to relax the type checking
than to either introduce new non-standard unaligned intrinsics or to disallow
intrinsics for the unaligned operations.

llvm-svn: 146963
2011-12-20 06:16:48 +00:00
Bob Wilson 89d14247ff Fix Neon builtin pointer argument checking for "sret" builtins.
The code for checking Neon builtin pointer argument types was assuming that
there would only be one pointer argument.  But, for vld2-4 builtins, the first
argument is a special sret pointer where the result will be stored.  So,
instead of scanning all the arguments to find a pointer, have TableGen figure
out the index of the pointer argument that needs checking.  That's better than
scanning all the arguments regardless.  <rdar://problem/10448804>

llvm-svn: 144834
2011-11-16 21:32:23 +00:00
Bob Wilson e4d7723b87 Check pointer types for arguments of Neon load/store macros. rdar://9958031
The Neon load/store intrinsics need to be implemented as macros to avoid
hiding alignment attributes on the pointer arguments, and the macros can
only evaluate those pointer arguments once (in case they have side effects),
so it has been hard to get the right type checking for those pointers.
I tried various alternatives in the arm_neon.h header, but it's much more
straightforward to just check directly in Sema.

llvm-svn: 144075
2011-11-08 05:04:11 +00:00
Bob Wilson 98bc98caa8 Clean up type flags for overloaded Neon builtins. No functional change.
This patch just adds a simple NeonTypeFlags class to replace the various
hardcoded constants that had been used until now.  Unfortunately I couldn't
figure out a good way to avoid duplicating that class between clang and
TableGen, but since it's small and rarely changes, that's not so bad.

llvm-svn: 144054
2011-11-08 01:16:11 +00:00
Bob Wilson 3b476aec6d Add __nodebug__ attribute to functions in arm_neon.h
This matches what we do for Intel vector intrinsics. <rdar://problem/10280207>

llvm-svn: 141958
2011-10-14 16:55:33 +00:00
Peter Collingbourne bee583fd6e Add the Clang tblgen backends to Clang, and flip the switch to cause
the build systems to use clang-tblgen.

llvm-svn: 141291
2011-10-06 13:03:08 +00:00