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4956 Commits

Author SHA1 Message Date
Owen Anderson a6201f0a72 Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness. 
llvm-svn: 137686
 2011-08-15 23:38:54 +00:00
Jim Grosbach 120a96a721 MCTargetAsmParser target match predicate support. 
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.

llvm-svn: 137675
 2011-08-15 23:03:29 +00:00
Owen Anderson 1d5d2cac8c Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 
Patch by James Molloy.

llvm-svn: 137647
 2011-08-15 20:51:32 +00:00
Owen Anderson de25f9aa8f Remove dead classes. 
llvm-svn: 137643
 2011-08-15 20:11:11 +00:00
Owen Anderson 61a3ece665 Fix incorrect encoding of UMAAL and friends. Patch by James Molloy. 
llvm-svn: 137641
 2011-08-15 20:08:25 +00:00
Owen Anderson 3157f2eebe Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy. 
llvm-svn: 137636
 2011-08-15 19:00:06 +00:00
Owen Anderson b9d82f411c Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
llvm-svn: 137635
 2011-08-15 18:44:44 +00:00
Jim Grosbach 30694dcdeb Update comment to reflect MC target machine refactor. 
llvm-svn: 137615
 2011-08-15 16:52:24 +00:00
Bob Wilson d1de7764be Expand VMOVQQQQ pseudo instructions. 
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed.  Our register allocator must be awesome!

llvm-svn: 137551
 2011-08-13 05:14:55 +00:00
Jim Grosbach 2325474368 ARM STR_POST_IMM offset encoding fix in load/store optimizer. 
Tidy up the code a bit and push the definition of the value next to the uses
to try to minimize this sort of issue from arising again while I'm at it.

rdar://9945172

llvm-svn: 137525
 2011-08-12 22:20:41 +00:00
Jim Grosbach f402f694e2 ARM expansion of pre-indexed store pseudos should maintain memoperands. 
Partial fix for rdar://9945172.

llvm-svn: 137513
 2011-08-12 21:02:34 +00:00
Owen Anderson 2d1d7a11f8 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
llvm-svn: 137502
 2011-08-12 20:36:11 +00:00
Owen Anderson 60138eaf93 Fix decoding of ARM-mode STRH. 
llvm-svn: 137499
 2011-08-12 20:02:50 +00:00
Owen Anderson 1043e173bc Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings. 
llvm-svn: 137494
 2011-08-12 19:41:29 +00:00
Owen Anderson 3987a61c16 Fix decoding of pre-indexed stores. 
llvm-svn: 137487
 2011-08-12 18:12:39 +00:00
Owen Anderson c5798a3a59 Separate decoding for STREXD and LDREXD to make each work better. 
llvm-svn: 137476
 2011-08-12 17:58:32 +00:00
Duncan Sands a41634e307 Silence a bunch (but not all) "variable written but not read" warnings 
when building with assertions disabled.

llvm-svn: 137460
 2011-08-12 14:54:45 +00:00
Jim Grosbach 8cffa28af8 ARM vector compare to zero instruction assembly parsing support. 
llvm-svn: 137389
 2011-08-11 23:51:13 +00:00
Jim Grosbach 37f7e6b2f4 Remove no-longer-true comments. These are for the assembler, also. 
llvm-svn: 137375
 2011-08-11 22:30:30 +00:00
Jim Grosbach e25942154c ARM STRT assembly parsing and encoding. 
llvm-svn: 137372
 2011-08-11 22:18:00 +00:00
Owen Anderson eca346ee1a Make the USAT16 operand decoder auto-generate-able. 
llvm-svn: 137371
 2011-08-11 22:10:11 +00:00
Owen Anderson ff0b442330 Add another accidentally omitted predicate operand. 
llvm-svn: 137370
 2011-08-11 22:08:38 +00:00
Owen Anderson 2f7aa73312 Add missing predicate operand on SMLA and friends. 
llvm-svn: 137368
 2011-08-11 22:05:38 +00:00
Jim Grosbach a2b8b60646 ARM load shifted register pre-index fix shift value asm parser encoding. 
llvm-svn: 137367
 2011-08-11 22:05:09 +00:00
Owen Anderson 12d13efa21 Handle new register classes in Thumb2 mode. Should fix the ARM buildbots. 
llvm-svn: 137364
 2011-08-11 21:52:38 +00:00
Owen Anderson f05e744857 Making SEL decodings auto-generate-able. 
llvm-svn: 137363
 2011-08-11 21:50:56 +00:00
Jim Grosbach 88981ff168 Tidy up comment. 
llvm-svn: 137359
 2011-08-11 21:41:59 +00:00
Owen Anderson b685c9f011 Fix decoding support for STREXD and LDREXD. 
llvm-svn: 137356
 2011-08-11 21:34:58 +00:00
Jim Grosbach d886f8cd8d ARM STRH assembly parsing and encoding. 
llvm-svn: 137353
 2011-08-11 21:17:22 +00:00
Owen Anderson 3a850f28d0 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
llvm-svn: 137347
 2011-08-11 20:47:56 +00:00
Jim Grosbach 2ea19d1438 Tidy up. Remove unused template parameter. 
llvm-svn: 137345
 2011-08-11 20:41:13 +00:00
Owen Anderson 887c0b1358 Improve operand validation for Thumb2 addressing modes. 
llvm-svn: 137344
 2011-08-11 20:40:40 +00:00
Jim Grosbach eb09f49a7f ARM STRD assembly parsing and encoding. 
llvm-svn: 137342
 2011-08-11 20:28:23 +00:00
Owen Anderson 6066340301 Continue to tighten decoding by performing more operand validation. 
llvm-svn: 137340
 2011-08-11 20:21:46 +00:00
Jim Grosbach 1b0f79573e Tidy up. 
llvm-svn: 137339
 2011-08-11 20:13:35 +00:00
Jim Grosbach 2a50260f2f ARM STRBT assembly parsing and encoding. 
llvm-svn: 137337
 2011-08-11 20:04:56 +00:00
Jim Grosbach d564bf3181 ARM STR(immediate) assembly parsing and encoding. 
llvm-svn: 137331
 2011-08-11 19:22:40 +00:00
Owen Anderson 3477f2cea5 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
llvm-svn: 137325
 2011-08-11 19:00:18 +00:00
Owen Anderson 0e15b48f3c Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
llvm-svn: 137323
 2011-08-11 18:55:42 +00:00
Owen Anderson e33c95d39b Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. 
llvm-svn: 137322
 2011-08-11 18:41:59 +00:00
Owen Anderson ed25385227 Improve error checking in the new ARM disassembler. Patch by James Molloy. 
llvm-svn: 137320
 2011-08-11 18:24:51 +00:00
Jim Grosbach 27ad83d8a9 ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
 2011-08-11 18:07:11 +00:00
Jim Grosbach 8ba76c6d5c ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
 2011-08-11 17:35:48 +00:00
Jim Grosbach d5d6359785 ARM LDRT assembly parsing and encoding. 
llvm-svn: 137282
 2011-08-10 23:43:54 +00:00
Jim Grosbach d3f7bcd43c Tidy up. 80 columns. 
llvm-svn: 137277
 2011-08-10 23:23:47 +00:00
Jim Grosbach cd4dd255c0 ARM LDRH(immediate) assembly parsing and encoding support. 
llvm-svn: 137260
 2011-08-10 22:42:16 +00:00
Jim Grosbach 1d9d5e93d1 ARM LDRD(register) assembly parsing and encoding. 
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
 2011-08-10 21:56:18 +00:00
Jim Grosbach f7164b2cfd Fix typo. Not quite sure how that slipped in there. 
llvm-svn: 137245
 2011-08-10 20:49:18 +00:00
Jim Grosbach 5b96b80644 ARM LDRD(immediate) assembly parsing and encoding support. 
llvm-svn: 137244
 2011-08-10 20:29:19 +00:00
Owen Anderson c86a5bd219 Add initial support for decoding NEON instructions in Thumb2 mode. 
llvm-svn: 137236
 2011-08-10 19:01:10 +00:00