Commit Graph

209889 Commits

Author SHA1 Message Date
Rui Ueyama 6666f6ad73 ELF2: Reduce nesting by returning early. NFC.
llvm-svn: 247168
2015-09-09 17:55:09 +00:00
Chandler Carruth 7b560d40bd [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible
with the new pass manager, and no longer relying on analysis groups.

This builds essentially a ground-up new AA infrastructure stack for
LLVM. The core ideas are the same that are used throughout the new pass
manager: type erased polymorphism and direct composition. The design is
as follows:

- FunctionAAResults is a type-erasing alias analysis results aggregation
  interface to walk a single query across a range of results from
  different alias analyses. Currently this is function-specific as we
  always assume that aliasing queries are *within* a function.

- AAResultBase is a CRTP utility providing stub implementations of
  various parts of the alias analysis result concept, notably in several
  cases in terms of other more general parts of the interface. This can
  be used to implement only a narrow part of the interface rather than
  the entire interface. This isn't really ideal, this logic should be
  hoisted into FunctionAAResults as currently it will cause
  a significant amount of redundant work, but it faithfully models the
  behavior of the prior infrastructure.

- All the alias analysis passes are ported to be wrapper passes for the
  legacy PM and new-style analysis passes for the new PM with a shared
  result object. In some cases (most notably CFL), this is an extremely
  naive approach that we should revisit when we can specialize for the
  new pass manager.

- BasicAA has been restructured to reflect that it is much more
  fundamentally a function analysis because it uses dominator trees and
  loop info that need to be constructed for each function.

All of the references to getting alias analysis results have been
updated to use the new aggregation interface. All the preservation and
other pass management code has been updated accordingly.

The way the FunctionAAResultsWrapperPass works is to detect the
available alias analyses when run, and add them to the results object.
This means that we should be able to continue to respect when various
passes are added to the pipeline, for example adding CFL or adding TBAA
passes should just cause their results to be available and to get folded
into this. The exception to this rule is BasicAA which really needs to
be a function pass due to using dominator trees and loop info. As
a consequence, the FunctionAAResultsWrapperPass directly depends on
BasicAA and always includes it in the aggregation.

This has significant implications for preserving analyses. Generally,
most passes shouldn't bother preserving FunctionAAResultsWrapperPass
because rebuilding the results just updates the set of known AA passes.
The exception to this rule are LoopPass instances which need to preserve
all the function analyses that the loop pass manager will end up
needing. This means preserving both BasicAAWrapperPass and the
aggregating FunctionAAResultsWrapperPass.

Now, when preserving an alias analysis, you do so by directly preserving
that analysis. This is only necessary for non-immutable-pass-provided
alias analyses though, and there are only three of interest: BasicAA,
GlobalsAA (formerly GlobalsModRef), and SCEVAA. Usually BasicAA is
preserved when needed because it (like DominatorTree and LoopInfo) is
marked as a CFG-only pass. I've expanded GlobalsAA into the preserved
set everywhere we previously were preserving all of AliasAnalysis, and
I've added SCEVAA in the intersection of that with where we preserve
SCEV itself.

One significant challenge to all of this is that the CGSCC passes were
actually using the alias analysis implementations by taking advantage of
a pretty amazing set of loop holes in the old pass manager's analysis
management code which allowed analysis groups to slide through in many
cases. Moving away from analysis groups makes this problem much more
obvious. To fix it, I've leveraged the flexibility the design of the new
PM components provides to just directly construct the relevant alias
analyses for the relevant functions in the IPO passes that need them.
This is a bit hacky, but should go away with the new pass manager, and
is already in many ways cleaner than the prior state.

Another significant challenge is that various facilities of the old
alias analysis infrastructure just don't fit any more. The most
significant of these is the alias analysis 'counter' pass. That pass
relied on the ability to snoop on AA queries at different points in the
analysis group chain. Instead, I'm planning to build printing
functionality directly into the aggregation layer. I've not included
that in this patch merely to keep it smaller.

Note that all of this needs a nearly complete rewrite of the AA
documentation. I'm planning to do that, but I'd like to make sure the
new design settles, and to flesh out a bit more of what it looks like in
the new pass manager first.

Differential Revision: http://reviews.llvm.org/D12080

llvm-svn: 247167
2015-09-09 17:55:00 +00:00
Matthias Braun 80595460d8 MachineVerifier: Check that SlotIndex MBBIndexList is sorted.
This introduces a check that the MBBIndexList is sorted as proposed in
http://reviews.llvm.org/D12443 but split up into a separate commit.

llvm-svn: 247166
2015-09-09 17:49:46 +00:00
Rui Ueyama 7da94a58a0 ELF2: Return early. NFC.
llvm-svn: 247165
2015-09-09 17:40:51 +00:00
Zachary Turner 84f5b0df8e Fix some compiler warnings.
llvm-svn: 247164
2015-09-09 17:25:43 +00:00
Alexander Kornienko ffc277989b [clang-tidy] Fix PR22785.
Fix http://llvm.org/PR22785. Bug 22785 - readability-braces-around-statements
doesn't work well with macros.

http://reviews.llvm.org/D12729

Patch by Marek Kurdej!

llvm-svn: 247163
2015-09-09 17:06:09 +00:00
Matt Arsenault ef67d76869 AMDGPU: Extract full 64-bit subregister and use subregs
Instead of extracting both 32-bit components from the 128-bit
register. This produces fewer copies and is easier for
the copy peephole optimizer to understand and see the actual uses
as extracts from a reg_sequence.

This avoids needing to handle subregister composing in the
PeepholeOptimizer's ValueTracker for this case.

llvm-svn: 247162
2015-09-09 17:03:29 +00:00
Matt Arsenault b5541fb098 AMDGPU: Remove unused multiclass argument
llvm-svn: 247161
2015-09-09 17:03:18 +00:00
Argyrios Kyrtzidis 203e92394d Fix a small bug in clang where generating some temporary files would have an extra period before the extension.
Patch by Cameron Esfahani!

llvm-svn: 247160
2015-09-09 16:48:47 +00:00
Tom Stellard 5268c17e52 llvm-config: Add --build-system option
Summary:
This can be used for distinguishing between cmake and autoconf builds.
Users may need this in order to handle inconsistencies between the
outputs of the two build systems.

Reviewers: echristo, chandlerc, beanz

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11838

llvm-svn: 247159
2015-09-09 16:39:30 +00:00
Dan Gohman f71abef701 [WebAssembly] Implement calls with void return types.
llvm-svn: 247158
2015-09-09 16:13:47 +00:00
Tom Stellard 9a197676b1 AMDGPU/SI: Fold operands through REG_SEQUENCE instructions
Summary:
This helps mostly when we use add instructions for address calculations
that contain immediates.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D12256

llvm-svn: 247157
2015-09-09 15:43:26 +00:00
Silviu Baranga a3e27edb5d [CostModel][AArch64] Remove amortization factor for some of the vector select instructions
Summary:
We are not scalarizing the wide selects in codegen for i16 and i32 and
therefore we can remove the amortization factor. We still have issues
with i64 vectors in codegen though.

Reviewers: mcrosier

Subscribers: mcrosier, aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D12724

llvm-svn: 247156
2015-09-09 15:35:02 +00:00
Rafael Espindola 3f4228f613 Start adding content to the dynamic section.
With this patch we create a dynamic string table (it is allocated, unlike
the regular one) and the dynamic section has a DT_STRTAB pointing to it.

llvm-svn: 247155
2015-09-09 15:33:08 +00:00
Sanjay Patel 6eccf487c9 don't repeat function names in comments; NFC
llvm-svn: 247154
2015-09-09 15:24:36 +00:00
Alexander Kornienko d3e098140f [clang-tidy] Automatically redirect to the new page.
llvm-svn: 247153
2015-09-09 15:23:39 +00:00
Dan Gohman 1ce7ba5fe0 [WebAssembly] Tidy up some unneeded newline characters.
llvm-svn: 247152
2015-09-09 15:13:36 +00:00
Joseph Tremoulet e5e75afe8f [CMake] Flag recursive cmake invocations for cross-compile
Summary:
Cross-compilation uses recursive cmake invocations to build native host
tools.  These recursive invocations only forward a fixed set of
variables/options, since the native environment is generally the default.
This change adds -DLLVM_TARGET_IS_CROSSCOMPILE_HOST=TRUE to the recursive
cmake invocations, so that cmake files can distinguish these recursive
invocations from top-level ones, which can explain why expected options
are unset.

LLILC will use this to avoid trying to generate its build rules in the
crosscompile native host target (where it is not needed), which would fail
if attempted because LLILC requires a cmake variable passed on the command
line, which is not forwarded in the recursive invocation.

Reviewers: rnk, beanz

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12679

llvm-svn: 247151
2015-09-09 14:57:06 +00:00
Sanjay Patel e283441836 function names start with a lower case letter; NFC
llvm-svn: 247150
2015-09-09 14:54:29 +00:00
Igor Breger ac29a82921 AVX512: Implemented encoding and intrinsics for
vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11802

llvm-svn: 247149
2015-09-09 14:35:09 +00:00
Sanjay Patel 2fbab9d893 don't repeat function names in comments; NFC
llvm-svn: 247148
2015-09-09 14:34:26 +00:00
Johannes Doerfert 7ca8dc2d2d Disable support for pointer expressions
The support for pointer expressions is broken as it can only handle
  some patterns in the IslExprBuilder. We should to treat pointers in
  expressions the same as integers at some point and revert this patch.

llvm-svn: 247147
2015-09-09 14:19:04 +00:00
Zoran Jovanovic 6b28f09d67 [mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions
Differential Revision: http://reviews.llvm.org/D11178

llvm-svn: 247146
2015-09-09 13:55:45 +00:00
Alex Lorenz b9a68dbcae Fix PR 24633 - Handle undef values when parsing standalone constants.
llvm-svn: 247145
2015-09-09 13:44:33 +00:00
Rafael Espindola d511726ce9 [Solaris] Use the GCC Installation detector to add the C++ include paths.
Patch by Xan López!

llvm-svn: 247144
2015-09-09 13:36:00 +00:00
Ed Maste d7b073e0aa Update expectedFailureFreeBSD to expectedFlakeyFreeBSD for intermittent tests
Due to LLDB or test race conditions these tests do not pass
consistently.

llvm.org/pr15037
llvm.org/pr19310
llvm.org/pr22611

llvm-svn: 247143
2015-09-09 13:15:14 +00:00
Michael Kruse da943ce613 Generate gitversion.h in autoconf builds
Add a custom makefile rule to generate lib/External/isl/gitversion.h
from GIT_HEAD_ID and trigger it using BULIT_SOURCES to ensure the file
exists before compilation starts.

The latest ISL creates gitversion.h from Makefile.am only, instead also
from configure.ac in previous version. While the Polly build invokes
configure, it does not invoke ISL's make such that the file was missing.

Invoking ISL's make would come with additional problems such as
triggering automake because of not preserved file time stamps.
Re-running automake might not be successful on other system
configurations for instance because it was preconfigured without
--with-clang option.

llvm-svn: 247142
2015-09-09 13:15:11 +00:00
Ed Maste bfd03da5ba XFAIL TestFormatters on FreeBSD
The test is hitting an assertion in Clang.  This is an extension of
r246766.

llvm.org/pr24691

llvm-svn: 247141
2015-09-09 13:10:33 +00:00
James Molloy 520838977b Rename ExitCount to BackedgeTakenCount, because that's what it is.
We called a variable ExitCount, stored the backedge count in it, then redefined it to be the exit count again.

llvm-svn: 247140
2015-09-09 12:51:10 +00:00
James Molloy 89eccee4db Delay predication of stores until near the end of vector code generation
Predicating stores requires creating extra blocks. It's much cleaner if we do this in one pass instead of mutating the CFG while writing vector instructions.

Besides which we can make use of helper functions to update domtree for us, reducing the work we need to do.

llvm-svn: 247139
2015-09-09 12:51:06 +00:00
Alexandros Lamprineas 3834d2ca08 [ARM] "cortex-r5f" and "cortex-m4f" are unknown names for clang.
The tests in test/CodeGen/arm-target-features.c are currently
passing but warning messages are suppressed. These tests are now
synchronized with the corresponding changes in Target Parser.

This patch will fix the regressions in clang caused by r247136

Differential Revision: http://reviews.llvm.org/D12722

llvm-svn: 247138
2015-09-09 11:29:06 +00:00
Tamas Berghammer 3366f0b42f Fix type in include header name
llvm-svn: 247137
2015-09-09 11:28:52 +00:00
Alexandros Lamprineas 712099ccfd LLVM does not distinguish Cortex-M4 from Cortex-M4F neither Cortex-R5 from R5F.
Removed "cortex-r5f" and "cortex-m4f" from Target Parser, sinced they are
unknown cpu names for llvm and clang. Also updated default FPUs for R5 and M4
accordingly.

Differential Revision: http://reviews.llvm.org/D12692

Change-Id: Ib81c7216521a361d8ee1296e4b6a2aa00bd479c5
llvm-svn: 247136
2015-09-09 11:20:48 +00:00
Tamas Berghammer bc99ce88f5 Add missing include after rL247131
llvm-svn: 247135
2015-09-09 11:16:32 +00:00
Mohit K. Bhakkad 9514a383c8 [LLDB][MIPS] Added support for the debugging of N32/O32 applications on MIPS64 target.
Patch by Nitesh Jain

Reviewers: clayborg, ovyalov.
Subscribers: jaydeep, bhushan, mohit.bhakkad, sagar, nitesh.jain, lldb-commits.
Differential Revision: http://reviews.llvm.org/D12671

llvm-svn: 247134
2015-09-09 10:32:20 +00:00
Tamas Berghammer 025103cc61 Change the looping stack detection code
In some special case (e.g. signal handlers, hand written assembly) it is
valid to have 2 stack frame with the same CFA value. This CL change the
looping stack detection code to report a loop only if at least 3
consecutive frames have the same CFA.

Differential revision: http://reviews.llvm.org/D12699

llvm-svn: 247133
2015-09-09 10:26:50 +00:00
Tamas Berghammer eb882fc1f8 Add basic fission support to SymbolFileDWARF
* Create new dwo symbol file class
* Add handling for .dwo sections
* Change indexes in SymbolFileDWARF to store compile unit offset next to
  DIE offset
* Propagate queries from dwarf compile unit to the dwo compile unit
  where applicable

Differential revision: http://reviews.llvm.org/D12291

llvm-svn: 247132
2015-09-09 10:20:48 +00:00
Tamas Berghammer 715cbe8939 Code cleanup in preparation of adding split dwarf support
* Remove some unused code
* Remove usage of DWARFDebugInfoEntry::Attributes where usage isn't
  reasonable
* Cleanup DWARFMappedHash with separating it to header and implementation
  file and fixing the visibility of the functions

Differential revision: http://reviews.llvm.org/D12374

llvm-svn: 247131
2015-09-09 10:20:36 +00:00
Tamas Berghammer 1535bebac6 Remove the dwo files in the cleanup stage of the tests
The dwo files are generated when the tests run with split dwarf info.

llvm-svn: 247130
2015-09-09 10:20:30 +00:00
Mohit K. Bhakkad a73239f860 [LLDB][MIPS] MIPS load/store instruction emulation for hardware watchpoints
Reviewers: clayborg.
Subscribers: jaydeep, bhushan, sagar, nitesh.jain, lldb-commits.
Differential Revision: http://reviews.llvm.org/D12670

llvm-svn: 247129
2015-09-09 10:17:58 +00:00
Daniel Sanders 2038747fce Fix vector splitting for extract_vector_elt and vector elements of <8-bits.
Summary:
One of the vector splitting paths for extract_vector_elt tries to lower:
    define i1 @via_stack_bug(i8 signext %idx) {
      %1 = extractelement <2 x i1> <i1 false, i1 true>, i8 %idx
      ret i1 %1
    }
to:
    define i1 @via_stack_bug(i8 signext %idx) {
      %base = alloca <2 x i1>
      store <2 x i1> <i1 false, i1 true>, <2 x i1>* %base
      %2 = getelementptr <2 x i1>, <2 x i1>* %base, i32 %idx
      %3 = load i1, i1* %2
      ret i1 %3
    }
However, the elements of <2 x i1> are not byte-addressible. The result of this
is that the getelementptr expands to '%base + %idx * (1 / 8)' which simplifies
to '%base + %idx * 0', and then simply '%base' causing all values of %idx to
extract element zero.

This commit fixes this by promoting the vector elements of <8-bits to i8 before
splitting the vector.

This fixes a number of test failures in pocl.

Reviewers: pekka.jaaskelainen

Subscribers: pekka.jaaskelainen, llvm-commits

Differential Revision: http://reviews.llvm.org/D12591

llvm-svn: 247128
2015-09-09 09:53:20 +00:00
Chandler Carruth 1688a772fc Fix a typo I spotted when hacking on SROA. Somewhat alarming that
nothing broke.

llvm-svn: 247127
2015-09-09 09:46:16 +00:00
Tobias Grosser f1ac57c6cd IslNodeBuilder: Add virtual function to obtain the schedule of an ast node
Not all users of our IslNodeBuilder will attach scheduling information to the
AST in the same way IslAstInfo is doing it today. By going through a virtual
function when extracting the schedule of an AST node other users can provide
their own functions for extract scheduling information in case they attach
scheduling information in a different way to the AST nodes.

No functional change for Polly itself intended.

llvm-svn: 247126
2015-09-09 09:24:38 +00:00
Zoran Jovanovic d9790793d6 [mips][microMIPS] Implement CACHEE and PREFE instructions
Differential Revision: http://reviews.llvm.org/D11628

llvm-svn: 247125
2015-09-09 09:10:46 +00:00
Hafiz Abid Qadeer 87f4f413ba Remove an invalid check in DW_OP_piece processing.
Summary:
When lldb is processing a location containing DW_OP_piece, the result is being
stored in the 'pieces' variable. The location is popped from the 'stack' variable.
So this check to see that 'stack' is not empty was invalid and caused the pieces
after the first to not get processed.

I am working on an architecture which has 16-bit and 8-bit registers. So this
problem was quite easy to see. But I was able to re-produce this issue on x86
too with long long variable and compiling woth -m32. It resulted in following
location list.
00000014 08048496 080484b5 (DW_OP_reg6 (esi); DW_OP_piece: 4; DW_OP_reg7 (edi); DW_OP_piece: 4)

and lldb was only showing the contents of first register when I evaluated the
variable as it does not process the 2nd piece due to this check.

Reviewers: clayborg, aprantl

Subscribers: lldb-commits

Differential Revision: http://reviews.llvm.org/D12674

llvm-svn: 247124
2015-09-09 09:06:05 +00:00
Matt Arsenault d768737454 AMDGPU: Fix not encoding src2 of VOP3b instructions
Broken by r247074. Should include an assembler test,
but the assembler is currently broken for VOP3b apparently.

llvm-svn: 247123
2015-09-09 08:39:49 +00:00
Sanjoy Das da0d79e0a0 [IRCE] Add INITIALIZE_PASS_DEPENDENCY invocations.
IRCE was just using INITIALIZE_PASS(), which is incorrect.

llvm-svn: 247122
2015-09-09 03:47:18 +00:00
Jason Molenda 21586c8385 When lldb gets the register definitions from the response of a
qXfer:features:read:target.xml packet, or via the
plugin.process.gdb-remote.target-definition-file setting, if the
register definition doesn't give us eh_frame or DWARF register
numbers for that register, try to get that information from the ABI
plugin.

The DWARF/eh_frame register numbers are defined in the ABI
standardization documents - so getting this from the ABI plugin is
reasonable.  There's little value in having the remote stub inform
us of this generic information, as long as we can all agree on the
names of the registers.

There's some additional information we could get from the ABI.  For
instance, on ABIs where function arguments are passed in registers,
lldb defines alternate names like "arg1", "arg2", "arg3" for these
registers so they can be referred to that way by the user.  We could
get this from the ABI if the remote stub doesn't provide that.  That
may be something worth doing in the future - but for now, I'm keeping
this a little more minimal.

Thinking about this, what we want/need from the remote stub at a
minimum are:

 1. The names of the register
 2. The number that the stub will use to refer to the register with
    the p/P packets and in the ? response packets (T/S) where 
    expedited register values are provided
 3. The size of the register in bytes
   
(nice to have, to remove any doubt)
 4. The offset of the register in the g/G packet if we're going to
    use that for reading/writing registers.

debugserver traditionally provides a lot more information in
addition to this via the qRegisterInfo packet, and debugserver 
augments its response to the qXfer:features:read:target.xml
query to include this information.  Including:

DWARF regnum, eh_frame regnum, stabs regnum, encoding (ieee754,
Uint, Vector, Sint), format (hex, unsigned, pointer, vectorof*,
float), registers that should be marked as invalid if this 
register is modified, and registers that contain this register.

We might want to get all of this from the ABI - I'm not convinced
that it makes sense for the remote stub to provide any of these 
details, as long as the ABI and remote stub can agree on register
names.

Anyway, start with eh_frame and DWARF coming from the ABI if 
they're not provided by the remote stub.  We can look at doing
more in the future.

<rdar://problem/22566585> 

llvm-svn: 247121
2015-09-09 03:36:24 +00:00
Jason Molenda 0ace3f5c73 A change I'm open to reverting if there is disagreement:
When lldb receives a gdb-remote protocol packet that has
nonprintable characters, it will print the packet in
gdb-remote logging with binary-hex encoding so we don't 
dump random 8-bit characters into the packet log.

I'm changing this check to allow whitespace characters
(newlines, linefeeds, tabs) to be printed if those are
the only non-printable characters in the packet. 

This is primarily to get the response to the 
qXfer:features:read:target.xml packet to show up in the
packet logs in human readable form.  Right now we just
get a dozen kilobytes of hex-ascii and it's hard to 
figure out what register number scheme is being used.

llvm-svn: 247120
2015-09-09 03:24:52 +00:00
Lang Hames 856e4767ff [RuntimeDyld] Add support for MachO x86_64 SUBTRACTOR relocation.
llvm-svn: 247119
2015-09-09 03:14:29 +00:00