Commit Graph

6431 Commits

Author SHA1 Message Date
Malcolm Parsons 21e545d08d Fix typos of occurred and occurrence
llvm-svn: 323318
2018-01-24 10:33:39 +00:00
Hiroshi Inoue 501931b117 [NFC] fix trivial typos in comments
"the the" -> "the"

llvm-svn: 323302
2018-01-24 05:04:35 +00:00
Benjamin Kramer cbce2f02e9 [TableGen] Optimize the regex search.
llvm::Regex is still the slowest regex engine on earth, running it over
all instructions on X86 takes a while. Extract a prefix and use a binary
search to reduce the search space before we resort to regex matching.

There are a couple of caveats here:
- The generic opcodes are outside of the sorted enum. They're handled in an extra loop.
- If there's a top-level bar we can't use the prefix trick.
- We bail on top-level ?. This could be handled, but it's rare.

This brings the time to generate X86GenInstrInfo.inc from 21s to 4.7s on
my machine.

llvm-svn: 323277
2018-01-23 23:05:04 +00:00
Volkan Keles 1b55f1f804 Add a utility to reduce GlobalISel tests
Summary: This patch adds a script to reduce GlobalISel failures using bugpoint.

Reviewers: bogner

Reviewed By: bogner

Subscribers: MatzeB, qcolombet, rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D41876

llvm-svn: 323248
2018-01-23 19:47:10 +00:00
Justin Bogner eaae305a09 update_mir_test_checks: Improve the check for LLVM IR in MIR files
The LLVM IR section of a MIR document can start with "--- |" rather
than just "---", because "|" is a sigil for a freeform document in
YAML. We need to handle this so that we don't try to add check lines
to the LLVM IR functions in a MIR file.

llvm-svn: 323178
2018-01-23 06:39:04 +00:00
Ilya Biryukov cc5e82b2f7 [Dockerfiles] Use a newer version of ninja when building inside debian8.
Summary:
The debian8 repos have an old version of ninja that seems to sometimes crash
when building llvm.

Reviewers: ioeric, mehdi_amini

Reviewed By: ioeric

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D42304

llvm-svn: 323134
2018-01-22 17:19:41 +00:00
Dimitry Andric aad72b77c6 Follow-up to rL322875 by initializing the do_libcxxabi variable properly.
llvm-svn: 322879
2018-01-18 19:30:30 +00:00
Dimitry Andric d05541f7d6 Add a -no-libcxxabi option to the test-release.sh script.
On FreeBSD, it is currently not possible to build libcxxabi and link
against it, so we have been building releases with -no-libs for quite
some time.

However, libcxx and libunwind should build without problems, so provide
an option to skip just libcxxabi.

llvm-svn: 322875
2018-01-18 18:39:13 +00:00
Daniel Sanders 12e6e709e9 [globalisel][tablegen] Honour priority order within nested instructions.
It appears that we haven't been prioritizing rules that contain nested
instructions properly. InstructionOperandMatcher didn't override
isHigherPriorityThan so it never compared the instructions/operands/predicates
inside nested instructions.

Fixes PR35926. Thanks to Diana Picus for the bug report.

llvm-svn: 322754
2018-01-17 20:34:29 +00:00
Fangrui Song c4526fc5af [utils] Make .cfi_startproc optional for powerpc
Summary: llc sometimes may not emit .cfi_startproc which makes func_dict to have less entries.

Subscribers: nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D42144

llvm-svn: 322725
2018-01-17 18:48:50 +00:00
Volkan Keles f7f2568613 [GlobalISel][TableGen] Add support for SDNodeXForm
Summary:
This patch adds CustomRenderer which renders the matched
operands to the specified instruction.

Targets can enable the matching of SDNodeXForm by adding
a definition that inherits from GICustomOperandRenderer and
GISDNodeXFormEquiv as follows.

def gi_imm8 : GICustomOperandRenderer<"renderImm8”>,
                       GISDNodeXFormEquiv<imm8_xform>;

Custom renderer functions should be of the form:
void render(MachineInstrBuilder &MIB, const MachineInstr &I);

Reviewers: dsanders, ab, rovka

Reviewed By: dsanders

Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet

Differential Revision: https://reviews.llvm.org/D42012

llvm-svn: 322582
2018-01-16 18:44:05 +00:00
George Rimar 83e63d96a9 [FileCheck] - Fix possible buffer out of bounds access when parsing --check-prefix.
FileCheck tool crashes when trying to parse --check-prefix argument if there is no any
data after it.

For example test like following would crash if there are no symbols and no EOL mark after `boom`:

# REQUIRES: x86
# RUN: <skipped few lines>
# RUN: llvm-readobj -t %t | FileCheck %s --check-prefix=boom

Patch fixes the issue.

Differential revision: https://reviews.llvm.org/D42057

llvm-svn: 322536
2018-01-16 08:09:24 +00:00
Craig Topper 7a0c601f95 [X86] Revisit the fix I made years ago to make 'xchgl %eax, %eax' not encode using the 0x90 encoding in 64-bit mode.
Prior to this we had a separate instruction and register class that excluded eax to prevent matching the instruction that would encode with 0x90.

This patch changes this to just use an InstAlias to force xchgl %eax, %eax to use XCHG32rr instruction in 64-bit mode. This gets rid of the separate instruction and register class.

llvm-svn: 322532
2018-01-16 06:07:16 +00:00
Sander de Smalen 886510f350 [TableGen][AsmMatcherEmitter] Generate assembler checks for tied operands
Summary:
This extends TableGen's AsmMatcherEmitter with code that generates
a table with tied-operand constraints. The constraints are checked
when parsing the instruction. If an operand is not equal to its tied operand,
the assembler will give an error.

Patch [2/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB.

Reviewers: olista01, rengolin, mcrosier, fhahn, craig.topper, evandro, echristo

Reviewed By: fhahn

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D41446

llvm-svn: 322166
2018-01-10 10:10:56 +00:00
Max Moroz 975eacada5 [lit] Implement "-r" option for builtin "diff" command + a test using that.
Summary:
That would allow to recursively compare directories in tests using
"diff -r" on Windows in a similar way as it can be done on Linux or Mac.

Reviewers: zturner, morehouse, vsk

Reviewed By: zturner

Subscribers: kcc, llvm-commits

Differential Revision: https://reviews.llvm.org/D41776

llvm-svn: 322102
2018-01-09 18:23:34 +00:00
Aleksandar Beserminji f02ad15ff1 [mips] Improve diagnostics for instruction mapping
This patch improves diagnostic for case when mapped instruction 
does not contain a field listed under RowFields.

Differential Revision: https://reviews.llvm.org/D41778

llvm-svn: 322004
2018-01-08 16:25:40 +00:00
Craig Topper 85657d59a9 [X86] Don't put any EVEX_B instructions in the tablegen generated load folding tables.
EVEX_B means different things for memory and register forms. The instructions should not be considered equivalent.

llvm-svn: 321954
2018-01-07 06:24:28 +00:00
Craig Topper ad89541ae9 [TableGen] Make the ambiguous match debug messages from the AsmMatcherEmitter slightly more useful.
Don't report ambiguous matches on different variants. Print the variant number in the output.

llvm-svn: 321938
2018-01-06 19:20:32 +00:00
Matt Arsenault 05d8f16aa4 Fix missing release metabug in merge-request.sh
llvm-svn: 321753
2018-01-03 18:51:22 +00:00
Tom Stellard d703b198f2 [lit] Bump version number
llvm-svn: 321735
2018-01-03 16:35:51 +00:00
Hans Wennborg 71525f706b The trunk version is now 7.0.0svn
llvm-svn: 321712
2018-01-03 14:52:54 +00:00
Hal Finkel 8b4bdfdbc4 [TableGen] Add support of Intrinsics with multiple returns
This change deals with intrinsics with multiple outputs, for example load
instrinsic with address updated.

DAG selection for Instrinsics could be done either through source code or
tablegen. Handling all intrinsics in source code would introduce a huge chunk
of repetitive code if we have a large number of intrinsic that return multiple
values (see NVPTX as an example). While intrinsic class in tablegen supports
multiple outputs, tablegen only supports Intrinsics with zero or one output on
TreePattern. This appears to be a simple bug in tablegen that is fixed by this
change.

For Intrinsics defined as:

  def int_xxx_load_addr_updated: Intrinsic<[llvm_i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>;

Instruction will be defined as:

  def L32_X: Inst<(outs reg:$d1, reg:$d2), (ins reg:$s1, reg:$s2), "ld32_x $d1, $d2, $s2", [(set i32:$d1, i32:$d2, (int_xxx_load_addr_updated i32:$s1, i32:$s2))]>;

Patch by Wenbo Sun, thanks!

Differential Revision: https://reviews.llvm.org/D32888

llvm-svn: 321704
2018-01-03 11:35:09 +00:00
Benjamin Kramer 3a13ed60ba Avoid int to string conversion in Twine or raw_ostream contexts.
Some output changes from uppercase hex to lowercase hex, no other functionality change intended.

llvm-svn: 321526
2017-12-28 16:58:54 +00:00
Walter Lee b074f1428f [git-llvm] Handle files ignored by svn correctly
Summary: Correctly handle files ignored by svn (such as .o files,
which are ignored by default) by adding "--no-ignore" flag to "svn
status" and "svn add".

Differential Revision: https://reviews.llvm.org/D41404

llvm-svn: 321388
2017-12-22 21:19:13 +00:00
Krzysztof Parzyszek 2e0f7bd0fe [TableGen] Print more helpful information in case of type contradiction
Dump the failing TreePattern.

llvm-svn: 321282
2017-12-21 17:12:43 +00:00
Aaron Ballman 82e17f58f0 Do not generate an empty switch statement as it causes MSVC to issue diagnostics about switch statements without case or default labels.
llvm-svn: 321217
2017-12-20 20:09:30 +00:00
Matt Arsenault 303327d58b TableGen: Allow setting SDNodeProperties on intrinsics
Allows preserving MachineMemOperands on intrinsics
through selection. For reasons I don't understand, this
is a static property of the pattern and the selector
deliberately goes out of its way to drop if not present.

Intrinsics already inherit from SDPatternOperator allowing
them to be used directly in instruction patterns. SDPatternOperator
has a list of SDNodeProperty, but you currently can't set them on
the intrinsic. Without SDNPMemOperand, when the node is selected
any memory operands are always dropped. Allowing setting this
on the intrinsics avoids needing to introduce another equivalent
target node just to have SDNPMemOperand set.

llvm-svn: 321212
2017-12-20 19:36:28 +00:00
Daniel Sanders 32de8bbd30 [globalisel][tablegen] Allow ImmLeaf predicates to use InstructionSelector members
NFC for currently supported targets. This resolves a problem encountered by
targets such as RISCV that reference `Subtarget` in ImmLeaf predicates.

llvm-svn: 321176
2017-12-20 14:41:51 +00:00
Ilya Biryukov 75db08124c Allow to apply cherry-picks when building Docker images.
Reviewers: mehdi_amini, ioeric, klimek

Reviewed By: ioeric

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D41393

llvm-svn: 321175
2017-12-20 14:39:07 +00:00
Sander de Smalen cd6be960ce [AArch64][SVE] Re-submit patch series for ZIP1/ZIP2
This patch resubmits the SVE ZIP1/ZIP2 patch series consisting of
of r320992, r320986, r320973, and r320970 by reverting
https://reviews.llvm.org/rL321024.

The issue that caused r321024 has been addressed in https://reviews.llvm.org/rL321158,
so this patch-series should be safe to resubmit.

llvm-svn: 321163
2017-12-20 11:02:42 +00:00
Adrian Prantl 0e6694d111 Silence a bunch of implicit fallthrough warnings
llvm-svn: 321114
2017-12-19 22:05:25 +00:00
Quentin Colombet 63a328c30c [TableGen][GlobalISel] Reset the internal map of RuleMatchers just before the emission
Between the creation of the last InstructionMatcher and the first
emission of the related Rule, we need to clear the internal map of IDs.
We used to do that right after the creation of the main
InstructionMatcher when building the rule and although that worked, this
is fragile because if for some reason some later code decides to create
more InstructionMatcher before the final call to emit, then the IDs
would be completely messed up.

Move that to the beginning of "emit" so that the IDs are guarantee to be
consistent.

NFC.

llvm-svn: 321053
2017-12-19 02:57:23 +00:00
Justin Bogner 4314f3adc2 update_mir_test_checks: Accept IR as input as well as MIR
We need to handle IR for tests that want to do lowering (or just
-stop-after with IR as input). I've run this on one AArch64 test to
demonstrate what it looks like.

llvm-svn: 321048
2017-12-19 00:49:04 +00:00
Justin Bogner 930a95c269 update_mir_test_checks: Add "mir" to some states and regex names
For tests that do lowering we need to support IR as input, so here we
clarify some names to avoid ambiguity in upcoming commits.

llvm-svn: 321039
2017-12-18 23:31:55 +00:00
Quentin Colombet eba10cbc88 [TableGen][GlobalISel] Make the arguments of the Instruction and Operand Matchers consistent
Move InsnVarID and OpIdx at the beginning of the list of arguments
for all the constructors of the OperandMatcher subclasses.
This matches what we do for the InstructionMatcher.

NFC.

llvm-svn: 321031
2017-12-18 22:12:13 +00:00
Quentin Colombet 34688b9e38 [TableGen][GlobalISel] Refactor optimizeRules related bit to allow code reuse
In theory, reapplying optimizeRules on each group matchers should give
us a second nesting level on the matching table. In practice, we need
more work to make that happen because all the predicates are actually
not directly available through the predicate matchers list.

NFC.

llvm-svn: 321025
2017-12-18 21:25:53 +00:00
Reid Kleckner 37517a2ddd Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turbo
This reverts changes r320992, r320986, r320973, and r320970.

r320970 by itself breaks the test case, and the rest depend on it.

Test case will land soon.

llvm-svn: 321024
2017-12-18 20:58:25 +00:00
Quentin Colombet ec76d9c47f [TableGen][GlobalISel] Optimize MatchTable for faster instruction selection
*** Context ***

Prior to this patchw, the table generated for matching instruction was
straight forward but highly inefficient.

Basically, each pattern generates its own set of self contained checks
and actions.
E.g., TableGen generated:
// First pattern
CheckNumOperand 3
CheckOpcode G_ADD
...
Build ADDrr
// Second pattern
CheckNumOperand 3
CheckOpcode G_ADD
...
Build ADDri
// Third pattern
CheckNumOperand 3
CheckOpcode G_SUB
...
Build SUBrr

*** Problem ***

Because of that generation, a *lot* of check were redundant between each
pattern and were checked every single time until we reach the pattern
that matches.
E.g., Taking the previous table, let say we are matching a G_SUB, that
means we were going to check all the rules for G_ADD before looking at
the G_SUB rule. In particular we are going to do:
check 3 operands; PASS
check G_ADD; FAIL
; Next rule
check 3 operands; PASS (but we already knew that!)
check G_ADD; FAIL (well it is still not true)
; Next rule
check 3 operands; PASS (really!!)
check G_SUB; PASS (at last :P)

*** Proposed Solution ***

This patch introduces a concept of group of rules (GroupMatcher) that
share some predicates and only get checked once for the whole group.

This patch only creates groups with one nesting level. Conceptually
there is nothing preventing us for having deeper nest level. However,
the current implementation is not smart enough to share the recording
(aka capturing) of values. That limits its ability to do more sharing.

For the given example the current patch will generate:
// First group
CheckOpcode G_ADD

 // First pattern
 CheckNumOperand 3
 ...
 Build ADDrr
 // Second pattern
 CheckNumOperand 3
 ...
 Build ADDri

// Second group
CheckOpcode G_SUB

 // Third pattern
 CheckNumOperand 3
 ...
 Build SUBrr

But if we allowed several nesting level, it could create a sub group
for the checknumoperand 3.
(We would need to call optimizeRules on the rules within a group.)

*** Result ***

With only one level of nesting, the instruction selection pass is up
to 4x faster. For instance, one instruction now takes 500 checks,
instead of 24k! With more nesting we could get in the tens I believe.

Differential Revision: https://reviews.llvm.org/D39034

rdar://problem/34670699

llvm-svn: 321017
2017-12-18 19:47:41 +00:00
Sander de Smalen 09f56a54d0 [AArch64][SVE] Asm: Improve diagnostics further when +sve is not specified
Summary: Patch [4/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. This patch further improves diagnostic messages for when the SVE feature is not specified.

Reviewers: rengolin, fhahn, olista01, echristo, efriedma

Reviewed By: fhahn

Subscribers: sdardis, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D40363

llvm-svn: 320992
2017-12-18 16:48:53 +00:00
Sander de Smalen 190979189a [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled instruction
Summary:
When emitting a diagnostic for an invalid operand, a specific diagnostic
should only be reported when the instruction being matched is actually
enabled by the feature flags.

Patch [3/4] in a series to add parsing of predicates and properly parse SVE 
ZIP1/ZIP2 instructions. This patch fixes bogus diagnostic messages for when
the SVE feature is not specified.

Reviewers: rengolin, craig.topper, olista01, sdardis, stoklund

Reviewed By: olista01, sdardis

Subscribers: fhahn, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D40362

llvm-svn: 320986
2017-12-18 14:34:24 +00:00
Quentin Colombet 893e0f15e2 [TableGen][GlobalISel] Make the different Matcher comparable
This opens refactoring opportunities in the match table now that we can
check that two predicates are the same.

NFC.

llvm-svn: 320890
2017-12-15 23:24:39 +00:00
Quentin Colombet a646ef08e8 [TableGen][GlobalISel] Fix unused variable warning in release mode
Introduced in r320887.

NFC.

llvm-svn: 320889
2017-12-15 23:24:36 +00:00
Quentin Colombet aad20be6ca [TableGen][GlobalISel] Have the predicate directly know which data they are dealing with
Prior to this patch, a predicate wouldn't make sense outside of its
rule. Indeed, it was only during emitting a rule that a predicate would
be made aware of the IDs of the data it is checking. Because of that,
predicates could not be moved around or compared between each other.

NFC.

llvm-svn: 320887
2017-12-15 23:07:42 +00:00
Don Hinton 44298f26b6 [debuginfo] Remove obsolete test_debuginfo.pl that was moved to debuginfo-tests.
Summary:
Now that r320495, "[debuginfo-tests] Support moving
debuginfo-tests to llvm/projects," has landed, which includes a local
copy of test_debuginfo.pl, remove the obsolete copy.

Reviewers: zturner, aprantl

Reviewed By: aprantl

Subscribers: llvm-commits, JDevlieghere

Differential Revision: https://reviews.llvm.org/D41260

llvm-svn: 320771
2017-12-15 00:06:26 +00:00
Quentin Colombet 063d798acb [TableGen][GlobalISel] Add a common class for all PredicateMatcher
NFC.

llvm-svn: 320767
2017-12-14 23:44:07 +00:00
Krzysztof Parzyszek 2aaeeb40b3 Add MVT::v128i1, NFC
Hexagon HVX has type v128i8, comparing two vectors of that type will
produce v128i1 types in SelectionDAG.

llvm-svn: 320732
2017-12-14 19:05:21 +00:00
Sander de Smalen 14e36ee5c3 Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.
Summary:
The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand.

This is because the code will only update the diagnostic if it is more 
specific than the previous diagnostic. However, when having validated
operands and 'moved on' to a next operand (for some instruction/alias for
which all previous operands are valid), if the diagnostic is InvalidOperand,
than that should be set as the diagnostic, not the more specific message
about a previous operand for some other instruction/alias candidate.

(Re-committed with an extra whitespace in SVEInstrFormats.td to trigger rebuild 
of AArch64GenAsmMatcher.inc, since the llvm-clang-x86_64-expensive-checks-win
builder does not seem to rebuild AArch64GenAsmMatcher.inc with the
newly built TableGen due to a missing dependency somewhere (see:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119555.html))

Reviewers: craig.topper, olista01, rengolin, stoklund

Reviewed By: olista01

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D40011

llvm-svn: 320711
2017-12-14 16:09:48 +00:00
Michael Zolotukhin 4d6b43ca94 Remove redundant includes from utils/TableGen.
llvm-svn: 320632
2017-12-13 21:31:13 +00:00
Craig Topper ac59db2efe [Targets] Don't automatically include the scheduler class enum from *GenInstrInfo.inc with GET_INSTRINFO_ENUM. Make targets request is separately.
Most of the targets don't need the scheduler class enum.

I have an X86 scheduler model change that causes some names in the enum to become about 18000 characters long. This is because using instregex in scheduler models causes the scheduler class to get named with every instruction that matches the regex concatenated together. MSVC has a limit of 4096 characters for an identifier name. Rather than trying to come up with way to reduce the name length, I'm just going to sidestep the problem by not including the enum in X86.

llvm-svn: 320552
2017-12-13 07:26:17 +00:00
Richard Smith 8a3adc3abb Avoid constructing an out-of-range value for an enumeration (which results in UB).
llvm-svn: 320206
2017-12-08 22:32:35 +00:00