Commit Graph

86868 Commits

Author SHA1 Message Date
Rafael Espindola 6635f9838e Convert getLoadStoreRegOpcode to use a switch.
llvm-svn: 108123
2010-07-12 03:43:04 +00:00
Rafael Espindola 871c724773 Convert the last use of getPhysicalRegisterRegClass and remove it.
AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An
instruction might be using a register that can only be replaced with one from
a subclass of getPhysicalRegisterRegClass.

With this patch we use getMinimalPhysRegClass. This is correct, but
conservative. We should check the uses of the register and select the
largest register class that can be used in all of them.

llvm-svn: 108122
2010-07-12 02:55:34 +00:00
Eric Christopher 856a682de4 Fix up the ocaml kaleidoscope example as well.
Note that the example currently doesn't appear to work.

llvm-svn: 108121
2010-07-12 02:32:44 +00:00
Jakob Stoklund Olesen de7201545e A basic block that only uses RFP registers still needs the FP_REG_KILL marker.
This fixes PR7375.

llvm-svn: 108120
2010-07-12 02:12:47 +00:00
Chris Lattner 0931644922 revert a hunk of code that Argiris added in r106213, which is the
root cause of PR7481 and probably more, and has no apparent 
testcases.  I don't understand the logic here so I can't repair it.

llvm-svn: 108119
2010-07-12 01:48:28 +00:00
Rafael Espindola 01c5a15dde Don't use getPhysicalRegisterRegClass in PBQP. The existing checks that the
physical register can be allocated in the class of the virtual are sufficient.

I think that the test for virtual registers is more strict than it needs to be,
it should be possible to coalesce two virtual registers the class of one
is a subclass of the other.

llvm-svn: 108118
2010-07-12 01:45:38 +00:00
Chris Lattner 25eea4db66 fix PR7311 by avoiding breaking casts when a bitcast from scalar->vector
is involved.

llvm-svn: 108117
2010-07-12 01:19:22 +00:00
Chris Lattner 601e390a3b make the prototypes for CreateMalloc and CreateFree more consistent. Patch
by Hans Vandierendonck from PR7605

llvm-svn: 108116
2010-07-12 00:57:28 +00:00
Rafael Espindola e35d70fafa Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp to
getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.

Update getLoadStoreRegOpcode to handle GR32_AD.

llvm-svn: 108115
2010-07-12 00:52:33 +00:00
Chris Lattner bbc25ff5cc if jump threading is able to infer interesting values on both
the LHS and RHS of an and/or instruction, don't multiply add
known predecessor values.  This fixes the crash on testcase
from PR7498

llvm-svn: 108114
2010-07-12 00:47:34 +00:00
Chris Lattner fd4a09fc0a fix PR7429, a crash turning a load from a string into a float.
llvm-svn: 108113
2010-07-12 00:22:51 +00:00
Chris Lattner f8feba368c convert to filechecconvert to filecheckk
llvm-svn: 108112
2010-07-12 00:21:10 +00:00
Chris Lattner 9338b0a1e2 merge two tests.
llvm-svn: 108111
2010-07-12 00:19:47 +00:00
Chris Lattner cda39c4ee4 improve Path::makeUnique when mkstemp/mktemp are not available
patch by Lasse Kärkkäinen in PR7404.

llvm-svn: 108110
2010-07-12 00:09:55 +00:00
Chris Lattner 0b7ae20a35 change machinelicm to use MachineInstr::isSafeToMove. No
intended functionality change.

The avoidance of hoistiing implicitdef seems wrong though.

llvm-svn: 108109
2010-07-12 00:00:35 +00:00
Chris Lattner 33919e7450 fix PR7280 by making the warning on code like this:
int test1() {
  return;
}

default to an error.

llvm-svn: 108108
2010-07-11 23:34:02 +00:00
Chris Lattner b6df00c29a first part of JIT support for address of labels, part of PR7264,
patch by Yuri!

llvm-svn: 108107
2010-07-11 23:07:28 +00:00
Chris Lattner ef74e2b2a8 change the 'invalid token after top level declarator' message to be
'expected ';' after top level declarator' which is much less vague.

llvm-svn: 108106
2010-07-11 22:46:04 +00:00
Chris Lattner 1390134c18 Fix PR7617 by not entering ParseFunctionDefinition when
a function prototype is followed by a declarator if we
aren't parsing a K&R style identifier list.

Also, avoid skipping randomly after a declaration if a
semicolon is missing.  Before we'd get:

t.c:3:1: error: expected function body after function declarator
void bar();
^

Now we get:

t.c:1:11: error: invalid token after top level declarator
void foo()
          ^
          ;

llvm-svn: 108105
2010-07-11 22:42:07 +00:00
Chris Lattner dbb1e93a9f add a const qualifier, refactor some code.
llvm-svn: 108104
2010-07-11 22:24:20 +00:00
Chris Lattner 2c52b7997c introduce WinCOFFObjectWriter, patch by Michael Spencer!
llvm-svn: 108103
2010-07-11 22:07:02 +00:00
Chris Lattner 56725be9ef introduce WinCOFFStreamer.cpp, patch by Michael Spencer!
llvm-svn: 108102
2010-07-11 22:05:00 +00:00
Nick Lewycky 5d373c2141 If it's safe to speculatively execute load(alloca) the it's safe to execute
load(gep(alloca)) where the gep is all-zeros. There's more we could do here but
this is a common case.

llvm-svn: 108101
2010-07-11 20:36:29 +00:00
Chris Lattner 31bd2de24e fix typo
llvm-svn: 108100
2010-07-11 19:42:53 +00:00
Jakob Stoklund Olesen 0961c55161 RISC architectures get their memory operand folding for free.
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

llvm-svn: 108099
2010-07-11 19:19:13 +00:00
Jakob Stoklund Olesen f6c7d7fb3f Use target independent COPY instructions for the fake fextend and fround
operations in x87 code.

llvm-svn: 108098
2010-07-11 18:19:39 +00:00
Jakob Stoklund Olesen 7c1392a765 Remove redundant branch. Thanks, Anton!
llvm-svn: 108097
2010-07-11 17:17:35 +00:00
Jakob Stoklund Olesen 98ee37d878 Remove obsolete README_SSE note.
We are generating movaps for all XMM register copies, including scalar
floating point values. This is known to be at least as good as movss and movsd
for all known architectures up to and including Nehalem because it avoids a
partial register stall.

The SSEDomainFix pass will switch movaps to movdqa when appropriate (i.e., when
operands come from the integer unit). We don't now that switching movaps to
movapd has any benefit.

The same applies to andps -> pand.

llvm-svn: 108096
2010-07-11 17:13:42 +00:00
Jakob Stoklund Olesen c4227f1362 Remove TargetInstrInfo::copyRegToReg entirely.
Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.

llvm-svn: 108095
2010-07-11 17:01:17 +00:00
Rafael Espindola 1da1cfccb1 Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.
llvm-svn: 108094
2010-07-11 16:49:10 +00:00
Rafael Espindola d7c4963f2f Convert uses of getPhysicalRegisterRegClass in VirtRegRewriter.cpp.
The first one was used just to call isSafeToMoveRegClassDefs. In
general, using a more specific reg class is better, in practice only
x86 implements that method and the results are always the same.

The second one is in FindFreeRegister and is used to check if a register
is in a register class, a much more direct call to contains is better as
it should cover more cases and is faster.

llvm-svn: 108093
2010-07-11 16:45:17 +00:00
Jakob Stoklund Olesen 74e5bf85f7 Replace copyRegToReg with copyPhysReg for SystemZ.
llvm-svn: 108092
2010-07-11 16:40:46 +00:00
Jakob Stoklund Olesen 4806848799 Avoid SSE instructions in FastIsel when it is not available.
llvm-svn: 108091
2010-07-11 16:22:13 +00:00
Chandler Carruth 34e0d14ff4 Remove two other uses of ATTRIBUTE_UNUSED for variables only used within
assert()s, switching to void-casts. Removed an unneeded Compiler.h include as
a result. There are two other uses in LLVM, but they're not due to assert()s,
so I've left them alone.

llvm-svn: 108088
2010-07-11 08:18:12 +00:00
Jakob Stoklund Olesen 928b593486 Replace copyRegToReg with copyPhysReg for XCore.
llvm-svn: 108087
2010-07-11 07:56:13 +00:00
Jakob Stoklund Olesen 976b7b61fc Replace copyRegToReg with copyPhysReg for Sparc.
llvm-svn: 108086
2010-07-11 07:56:09 +00:00
Chandler Carruth 62e5e56dad Switch to void-cast for this. Chris prefers that over the attribute, I'll
probably try and switch more of these if I can.

llvm-svn: 108085
2010-07-11 07:42:13 +00:00
Jakob Stoklund Olesen 1dba6814c9 Replace copyRegToReg with copyPhysReg for CellSPU.
llvm-svn: 108084
2010-07-11 07:31:03 +00:00
Jakob Stoklund Olesen 0d611979a8 Replace copyRegToReg with copyPhysReg for PowerPC.
llvm-svn: 108083
2010-07-11 07:31:00 +00:00
Jakob Stoklund Olesen f889e280b8 Fix PIC16 comments referencing copyRegToReg.
llvm-svn: 108082
2010-07-11 07:30:57 +00:00
Jakob Stoklund Olesen e494d0ff3e Replace copyRegToReg with copyPhysReg for PIC16.
llvm-svn: 108081
2010-07-11 06:53:33 +00:00
Jakob Stoklund Olesen 65306369ae Replace copyRegToReg with copyPhysReg for MSP430.
llvm-svn: 108080
2010-07-11 06:53:30 +00:00
Jakob Stoklund Olesen 37a38f4b28 Replace copyRegToReg with copyPhysReg for MBlaze.
llvm-svn: 108079
2010-07-11 06:53:27 +00:00
Jakob Stoklund Olesen d7b33002dd Replace copyRegToReg with copyPhysReg for ARM.
llvm-svn: 108078
2010-07-11 06:33:54 +00:00
Jakob Stoklund Olesen 52984e1aef Replace copyRegToReg with copyPhysReg for Blackfin.
llvm-svn: 108077
2010-07-11 05:44:34 +00:00
Jakob Stoklund Olesen e46f3eb0c4 X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg!
llvm-svn: 108076
2010-07-11 05:44:30 +00:00
Jakob Stoklund Olesen 8833073758 Remove copyRegToReg from TargetInstrInfo so it is not longer accesible.
Use a COPY instruction instead for register copies, or TII::copyPhysReg() after
COPY instructions are lowered.

Targets should implement copyPhysReg instead of copyRegToReg.

llvm-svn: 108075
2010-07-11 05:17:06 +00:00
Jakob Stoklund Olesen 8969657f0c Use COPY in X86FastISel::X86SelectRet.
Don't try a cross-class copy. That is very unlikely anywy since return value
registers are usually register class friendly. (%EAX, %XMM0, etc).

llvm-svn: 108074
2010-07-11 05:17:02 +00:00
Jakob Stoklund Olesen 51642aea77 Use COPY for fast-isel bitconvert, but don't create cross-class copies.
This doesn't change the behavior of SelectBitcast for X86.

llvm-svn: 108073
2010-07-11 05:16:54 +00:00
Rafael Espindola a76eccf815 Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

llvm-svn: 108072
2010-07-11 04:01:49 +00:00