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Author SHA1 Message Date
Zoran Jovanovic 3a7654c15d [mips][microMIPS] Extending size reduction pass with LWP and SWP 
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
It introduces reduction of two instructions into one instruction:
Two SW instructions are transformed into one SWP instrucition.
Two LW instructions are transformed into one LWP instrucition.
Differential Revision: https://reviews.llvm.org/D39115

llvm-svn: 334595
 2018-06-13 12:51:37 +00:00
Zoran Jovanovic f4f2d084c6 [mips][microMIPS] Extending size reduction pass with XOR16 
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
XOR instruction is transformed into 16-bit instruction XOR16, if possible.
Differential Revision: https://reviews.llvm.org/D34239

llvm-svn: 310579
 2017-08-10 10:27:29 +00:00
Zoran Jovanovic 1c17001235 [mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SP 
Author: milena.vujosevic.janicic
The patch extends size reduction pass for MicroMIPS.
The following instructions are examined and transformed, if possible:
ADDIU instruction is transformed into 16-bit instruction ADDIUSP
ADDIU instruction is transformed into 16-bit instruction ADDIUR1SP
Usage of u_int64_t replaced by uint64_t to avoid issues because of which previous patch version was reverted:
Differential Revision: https://reviews.llvm.org/D34511

llvm-svn: 310044
 2017-08-04 10:18:44 +00:00
Zoran Jovanovic 0e03935182 Reverting commit 308011. 
llvm-svn: 308017
 2017-07-14 10:52:22 +00:00
Zoran Jovanovic d374c5993b [mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SP 
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
The following instructions are examined and transformed, if possible:
ADDIU instruction is transformed into 16-bit instruction ADDIUSP
ADDIU instruction is transformed into 16-bit instruction ADDIUR1SP
Function InRange is changed to avoid left shifting of negative values, since 
that caused some sanitizer tests to fail (so the previous patch 
Differential Revision: https://reviews.llvm.org/D34511

llvm-svn: 308011
 2017-07-14 10:13:11 +00:00
Simon Dardis 5852c4c108 Revert "[mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SP" 
This reverts commit r305455. This commit was reported as breaking one of
the sanitizer buildbots. Reverting until lab.llvm.org comes back online.

llvm-svn: 305557
 2017-06-16 14:00:33 +00:00
Zoran Jovanovic d9299293ad [mips][microMIPS] Extending size reduction pass with ADDIUSP and ADDIUR1SP 
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
The following instructions are examined and transformed, if possible:
ADDIU instruction is transformed into 16-bit instruction ADDIUSP
ADDIU instruction is transformed into 16-bit instruction ADDIUR1SP
Differential Revision: https://reviews.llvm.org/D33887

llvm-svn: 305455
 2017-06-15 09:14:33 +00:00
Zoran Jovanovic 2aae0649a1 [mips][microMIPS] Extending size reduction pass with LBU16, LHU16, SB16 and SH16 
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
The following instructions are examined and transformed, if possible:
LBU instruction is transformed into 16-bit instruction LBU16
LHU instruction is transformed into 16-bit instruction LHU16
SB instruction is transformed into 16-bit instruction SB16
SH instruction is transformed into 16-bit instruction SH16
Differential Revision: https://reviews.llvm.org/D33091

llvm-svn: 304550
 2017-06-02 14:14:21 +00:00
Zoran Jovanovic ffef3e3c6a [mips][microMIPS] Adding code size reduction pass for MicroMIPS 
Author: milena.vujosevic.janicic
Reviewers: sdardis
The code implements size reduction pass for MicroMIPS.
Load and store instructions are examined and transformed, if possible.
lw32 instruction is transformed into 16-bit instruction lwsp
sw32 instruction is transformed into 16-bit instruction swsp
Arithmetic instrcutions are examined and transformed, if possible.
addu32 instruction is transformed into 16-bit instruction addu16
subu32 instruction is transformed into 16-bit instruction subu16
Differential Revision: https://reviews.llvm.org/D15144

llvm-svn: 301540
 2017-04-27 13:10:48 +00:00