Commit Graph

155038 Commits

Author SHA1 Message Date
Jonas Devlieghere a15f25d325 [dwarfdump][NFC] Consistent printing of address ranges
This implement the insertion operator for DWARF address ranges so they
are consistently printed as [LowPC, HighPC).

While a dump method might have felt more consistent, it is used
exclusively for printing error messages in the verifier and never used
for actual dumping. Hence this approach is more intuitive and creates
less clutter at the call sites.

Differential revision: https://reviews.llvm.org/D38395

llvm-svn: 314523
2017-09-29 15:41:22 +00:00
Nicolai Haehnle ce4ddd06da AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC
The hardware will only forward EXEC_LO; the high 32 bits will be zero.

Additionally, inline constants do not work. At least,

   v_addc_u32_e64 v0, vcc, v0, v1, -1

which could conceivably be used to combine (v0 + v1 + 1) into a single
instruction, acts as if all carry-in bits are zero.

The llvm.amdgcn.ps.live test is adjusted; it would be nice to combine

   s_mov_b64 s[0:1], exec
   v_cndmask_b32_e64 v0, v1, v2, s[0:1]

into

   v_mov_b32 v0, v3

but it's not particularly high priority.

Fixes dEQP-GLES31.functional.shaders.helper_invocation.value.*

llvm-svn: 314522
2017-09-29 15:37:31 +00:00
Jun Bum Lim 0e16a59e83 Use the basic cost if a GEP is not used as addressing mode
Summary:
Currently, getGEPCost() returns TCC_FREE whenever a GEP is a legal addressing mode in the target.
However, since it doesn't check its actual users, it will return FREE even in cases
where the GEP cannot be folded away as a part of actual addressing mode.
For example, if an user of the GEP is a call instruction taking the GEP as a parameter,
then the GEP may not be folded in isel.

Reviewers: hfinkel, efriedma, mcrosier, jingyue, haicheng

Reviewed By: hfinkel

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D38085

llvm-svn: 314517
2017-09-29 14:50:16 +00:00
Jonas Paulsson c9e363ac69 [SystemZ] implement shouldCoalesce()
Implement shouldCoalesce() to help regalloc avoid running out of GR128
registers.

If a COPY involving a subreg of a GR128 is coalesced, the live range of the
GR128 virtual register will be extended. If this happens where there are
enough phys-reg clobbers present, regalloc will run out of registers (if
there is not a single GR128 allocatable register available).

This patch tries to allow coalescing only when it can prove that this will be
safe by checking the (local) interval in question.

Review: Ulrich Weigand, Quentin Colombet
https://reviews.llvm.org/D37899
https://bugs.llvm.org/show_bug.cgi?id=34610

llvm-svn: 314516
2017-09-29 14:31:39 +00:00
Simon Pilgrim b6cf279214 Fix spelling in comments. NFCI.
llvm-svn: 314515
2017-09-29 14:13:47 +00:00
Amara Emerson 7d6c55f8aa [X86] Improve codegen for inverted overflow checking intrinsics.
Adds a new combine for: xor(setcc cc, val), 1 --> setcc (invert(cc), val)

Differential Revision: https://reviews.llvm.org/D38161

llvm-svn: 314514
2017-09-29 13:53:44 +00:00
Sam Parker 963da5b119 [ARM] v8.3-a complex number support
New instructions are added to AArch32 and AArch64 to aid
floating-point multiplication and addition of complex numbers, where
the complex numbers are packed in a vector register as a pair of
elements. The Imaginary part of the number is placed in the more
significant element, and the Real part of the number is placed in the
less significant element.

This patch adds assembler for the ARM target.

Differential Revision: https://reviews.llvm.org/D36789

llvm-svn: 314511
2017-09-29 13:11:33 +00:00
Michael Zuckerman 0b5db55b96 Small modification <NFC>
Change-Id: I360abccee12cae29bd2ac4f8399c9ecc92eb7f13
llvm-svn: 314510
2017-09-29 12:45:54 +00:00
Simon Pilgrim dbcad23e50 Fix Wmismatched-tags warning.
InlineAsmIdentifierInfo was declared a class in some places and a class in others.

llvm-svn: 314508
2017-09-29 11:42:05 +00:00
Aleksandar Beserminji 29341b88ac [mips] Reordering callseq* nodes to be linear
Fix nested callseq* nodes by moving callseq_start after the
arguments calculation to temporary registers, so that callseq* nodes
in resulting DAG are linear.

Recommitting r314497. This version does not contain test which fails
when compiler is not build in debug mode.

Differential Revision: https://reviews.llvm.org/D37328

llvm-svn: 314507
2017-09-29 11:05:02 +00:00
Aleksandar Beserminji a0a01e7172 Revert "[mips] Reordering callseq* nodes to be linear"
Added test relies on the compiler being built in debug mode,
which may not be the case.

This reverts commit r314497.

llvm-svn: 314506
2017-09-29 10:52:03 +00:00
Simon Dardis f21d8d6ad5 [mips] Add missing license info, formatting changes. NFCI
Add missing license information to MicroMipsInstrFPU.td and
fix most of the formatting errors present. Others will be
addressed in a follow up commits.

llvm-svn: 314505
2017-09-29 10:08:06 +00:00
Simon Pilgrim 2b96841d1d [X86][SSE] Added more tests for vector multiplications as utility for D37896
Added additional tests for vector multiplications with multipliers that are:
 * powers of 2 displaced by 1,
 * product of a power of 2 displaced by one with another power of 2.

Patch by @pacxx (Michael Haidl)

Differential Revision: https://reviews.llvm.org/D38350

llvm-svn: 314504
2017-09-29 10:02:01 +00:00
Aleksandar Beserminji 0168ef26ec [mips] Add test cases for dext/dins family of instructions
Add missing test cases for dext, dextm, dextu, dins, dinsm and
dinsu instructions.

Differential Revision: https://reviews.llvm.org/D37741

llvm-svn: 314503
2017-09-29 09:53:24 +00:00
Tim Renouf ef1ae8ffac [AMDGPU] calling conventions for AMDPAL OS type
Summary:
This commit adds comments on how the AMDPAL OS type overloads the
existing AMDGPU_ calling conventions used by Mesa, and adds a couple of
new ones.

Reviewers: arsenm, nhaehnle, dstuttard

Subscribers: mehdi_amini, kzhuravl, wdng, yaxunl, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D37752

llvm-svn: 314502
2017-09-29 09:51:22 +00:00
Tim Renouf 132291589f [AMDGPU] AMDPAL scratch buffer support
Summary:
Added support for scratch (including spilling) for OS type amdpal:
generates code to set up the scratch descriptor if it is needed.

With amdpal, the scratch resource descriptor is loaded from offset 0 of
the global information table. The low 32 bits of the address of the
global information table is passed in s0.

Added amdgpu-git-ptr-high function attribute to hard-wire the high 32
bits of the address of the global information table. If the function
attribute is not specified, or is 0xffffffff, then the backend generates
code to use the high 32 bits of pc.

The documentation for the AMDPAL ABI will be added in a later commit.

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye

Differential Revision: https://reviews.llvm.org/D37483

llvm-svn: 314501
2017-09-29 09:49:35 +00:00
Tim Renouf 9f7ead3334 [Triple] Add AMDPAL operating system type
Summary:
This operating system type represents the AMDGPU PAL runtime, and will
be required by the AMDGPU backend in order to generate correct code for
this runtime.

Currently it generates the same code as not specifying an OS at all.
That will change in future commits.

Patch from Tim Corringham.

Subscribers: arsenm, nhaehnle

Differential Revision: https://reviews.llvm.org/D37380

llvm-svn: 314500
2017-09-29 09:48:12 +00:00
Jonas Devlieghere 19fc4d941f [dwarfdump][NFC] Consistent errors and warnings with --verify
This patch introduces 3 helper functions: error(), warn() and note() to
make printing  during verification more consistent. When supported, the
respective prefixes are printed in color using the same color scheme as
clang.

Differential revision: https://reviews.llvm.org/D38368

llvm-svn: 314498
2017-09-29 09:33:31 +00:00
Aleksandar Beserminji 502dcb035a [mips] Reordering callseq* nodes to be linear
Fix nested callseq* nodes by moving callseq_start after the
arguments calculation to temporary registers, so that callseq* nodes
in resulting DAG are linear.

Differential Revision: https://reviews.llvm.org/D37328

llvm-svn: 314497
2017-09-29 09:32:14 +00:00
Coby Tayree c3d24118e8 [X86][MS-InlineAsm] Extended support for variables / identifiers on memory / immediate expressions
Allow the proper recognition of Enum values and global variables inside ms inline-asm memory / immediate expressions, as they require some additional overhead and treated incorrect if doesn't early recognized.
supersedes D33278, D35774

Differential Revision: https://reviews.llvm.org/D37412

llvm-svn: 314493
2017-09-29 07:02:46 +00:00
Adam Nemet 9d57dc6fb1 Make find_opt_files vararg
This is slightly less verbose for the common case of a single build directory
and more intuitive when using this API directly from the interpreter.

llvm-svn: 314491
2017-09-29 05:20:53 +00:00
Lang Hames 13cda49c96 [ORC] Replace decltype with a concrete type to make MSVC happy.
This should fix some build failures on windows bots due to r314486.

llvm-svn: 314490
2017-09-29 05:03:43 +00:00
Brian Gesiak 16b86e7d18 [CMake] Fix typo "Wraning" (NFC)
Summary:
The typo was added in https://reviews.llvm.org/rL247151.
It should be "warning", not "wraning".

llvm-svn: 314486
2017-09-29 02:48:07 +00:00
Saleem Abdulrasool 46ee7330bb llvm-readobj: fix a few typos (NFC)
Correct the spelling of multiple in a couple of sites.

Patch by Alex Langford!

llvm-svn: 314485
2017-09-29 02:45:44 +00:00
Sanjoy Das 0ac5ba5ade Revert "[BypassSlowDivision] Improve our handling of divisions by constants"
This reverts commit r314253.  It causes a miscompile on P100 in an internal
benchmark.  Reverting while I investigate.

llvm-svn: 314482
2017-09-29 00:54:16 +00:00
Adrian Prantl f51e78017d llvm-dwarfdump: support .apple-namespaces in --find
llvm-svn: 314481
2017-09-29 00:52:33 +00:00
Marek Sokolowski 4a765da3e9 [llvm-rc] Import all make_unique invocations from llvm namespace.
Previous patch fixed one of LLVM buildbots (lld-x86_64-win7).
However, some others have already been failing because of make_unique
compilation error (llvm-clang-x86_64-expensive-checks-win).

llvm-svn: 314480
2017-09-29 00:33:57 +00:00
Adrian Prantl 714ee4d536 llvm-dwarfdump: add support for .apple_types in --find
llvm-svn: 314479
2017-09-29 00:33:22 +00:00
Marek Sokolowski b5f39a05a3 [llvm-rc] Add user-defined resources parsing ability. [8/8]
This allows llvm-rc to parse user-defined resources (ref:
msdn.microsoft.com/en-us/library/windows/desktop/aa381054.aspx).
These statements either import files, or put the specified raw data in
the resulting resource file.

Thanks to Nico Weber for his original work in this area.

Differential Revision: https://reviews.llvm.org/D37033

llvm-svn: 314478
2017-09-29 00:14:18 +00:00
Marek Sokolowski 7e89ee7fdc [llvm-rc] Add integer expressions parsing ability. [7/8]
This allows the ints to be written as integer expressions evaluating to
unsigned 16-bit/32-bit integers.

All the expressions may use the following operators: + - & | ~, and
parentheses. Minus token - can be also unary. There is no precedence of
the operators other than the unary operators binding stronger than their
binary counterparts.

Differential Revision: https://reviews.llvm.org/D37022

llvm-svn: 314477
2017-09-28 23:53:25 +00:00
Jessica Paquette 919991690c [MachineOutliner][NFC] Simplify logic in pruneCandidates
This commit yanks out the repeated sections of code in pruneCandidates into
two lambdas: ShouldSkipCandidate and Prune. This simplifies the logic in
pruneCandidates significantly, and reduces the chance of introducing bugs by
folding all of the shared logic into one place.

llvm-svn: 314475
2017-09-28 23:39:36 +00:00
Craig Topper 6255c7b675 [X86] Don't select (cmp (and, imm), 0) to testw
Summary:
X86ISelDAGToDAG tries to analyze ANDs compared with 0 to optimize to narrower immediates using subregisters.

I don't think we should be optimizing to 16-bit test instructions. It goes against our normal behavior of promoting i16 operations to i32. It only saves one byte due to the need to add a 0x66 prefix. I think it would also be subject to a length changing prefix penalty in the decoders on Intel CPUs.

Reviewers: RKSimon, zvi, spatel

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38273

llvm-svn: 314474
2017-09-28 23:35:36 +00:00
Marek Sokolowski 99ead70fea [llvm-rc] Fix-up for r314468 (argument-dependent lookup in make_unique).
llvm-svn: 314472
2017-09-28 23:12:53 +00:00
Matthias Braun 51687912a4 ARM: Fix cases where CSI Restored bit is not cleared
LR is an untypical callee saved register in that it is restored into a
different register (PC) and thus does not live-out of the return block.
This case requires the `Restored` flag in CalleeSavedInfo to be cleared.

This fixes a number of cases where this wasn't handled correctly yet.

llvm-svn: 314471
2017-09-28 23:12:06 +00:00
Yonghong Song ef29a84d48 bpf: fix a bug for disassembling ld_pseudo inst
Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 314469
2017-09-28 22:47:34 +00:00
Marek Sokolowski fb74cb1edf [llvm-rc] Add VERSIONINFO parsing ability. [6/8]
This extends the set of llvm-rc parser's available resources by
another one, VERSIONINFO.

Ref: msdn.microsoft.com/en-us/library/windows/desktop/aa381058.aspx

Thanks to Nico Weber for his original work in this area.

Differential Revision: https://reviews.llvm.org/D37021

llvm-svn: 314468
2017-09-28 22:41:38 +00:00
Eugene Zelenko 3b87336a0c [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 314467
2017-09-28 22:27:31 +00:00
Sanjay Patel 4664d77316 [x86] add tests for possible insertelement to shuffle transform; NFC
See PR34716 and D38316 for more discussion.

llvm-svn: 314466
2017-09-28 22:27:25 +00:00
Ulrich Weigand df86855f61 [SystemZ] Fix fall-out from r314428
The expensive-checks build bot found a problem with the r314428 commit:
if CC is live after a ATOMIC_CMP_SWAPW instruction, it needs to be
marked as live-in to the block after the loop the pseudo gets expanded
to.  This actually fixes a code-gen bug as well, since if the CC isn't
live, the CR and JLH are merged to a CRJLH which doesn't actually set
the condition code any more.

llvm-svn: 314465
2017-09-28 22:08:25 +00:00
Craig Topper ed19350293 [X86] Make use of vpmovwb when possible in LowerMULH
If we have BWI, we can truncate in a much simpler way by using vpmovwb. This even works without VLX by using the wider zmm->ymm truncate with a subvector extract.

Differential Revision: https://reviews.llvm.org/D38375

llvm-svn: 314457
2017-09-28 20:10:34 +00:00
Evgeniy Stepanov fa769be5e7 Fix -Werror build.
/code/llvm-project/llvm/unittests/ExecutionEngine/Orc/RTDyldObjectLinkingLayerTest.cpp:260:38: error: lambda capture 'this' is not used [-Werror,-Wunused-lambda-capture]
                                    [this](decltype(ObjLayer)::ObjHandleT,

llvm-svn: 314454
2017-09-28 19:43:53 +00:00
Martin Storsjo d6218cc385 [ARM] Restore the right frame pointer register in Int_eh_sjlj_longjmp
In setupEntryBlockAndCallSites in CodeGen/SjLjEHPrepare.cpp,
we fetch and store the actual frame pointer, but on return via
the longjmp intrinsic, it always was restored into the r7 variable.

On windows, the frame pointer should be restored into r11 instead of r7.

On Darwin (where sjlj exception handling is used by default), the frame
pointer is always r7, both in arm and thumb mode, and likewise, on
windows, the frame pointer always is r11.

On linux however, if sjlj exception handling is enabled (which it isn't
by default), libcxxabi and the user code can be built in differing modes
using different registers as frame pointer. Therefore, when restoring
registers on a platform where we don't always use the same register
depending on code mode, restore both r7 and r11.

Differential Revision: https://reviews.llvm.org/D38253

llvm-svn: 314451
2017-09-28 19:04:30 +00:00
Martin Storsjo adceba59a2 [ARM] Fix SJLJ exception handling when manually chosen on a platform where it isn't default
Differential Revision: https://reviews.llvm.org/D38252

llvm-svn: 314450
2017-09-28 19:04:14 +00:00
Matthias Braun 5c3e8a450e MIR: Serialize CaleeSavedInfo Restored flag
llvm-svn: 314449
2017-09-28 18:52:14 +00:00
Craig Topper 56bfbfb117 [AVX512] Add avx512bw command lines to 128-bit idiv tests.
The multiply lowering on some of the tests can take advantage of the vpmovwb to simplify the truncate.

llvm-svn: 314448
2017-09-28 18:45:29 +00:00
Craig Topper 3819be6cf6 [X86] Use target independent ZERO_EXTEND/SIGN_EXTEND nodes were possible in LowerMULH
We aren't do any in register extends here so we should be able to just the target independent nodes directly and allow them to be lowered as necessary.

llvm-svn: 314447
2017-09-28 18:45:28 +00:00
Craig Topper fc104bfbc0 [X86] Move a setOperation action for ISD::TRUNCATE near another one in the same if. Remove one that is redundant with another subtarget features.
llvm-svn: 314446
2017-09-28 18:45:27 +00:00
Adrian Prantl 2095e60851 Address further review feedback. (NFC)
llvm-svn: 314443
2017-09-28 18:31:51 +00:00
Adrian Prantl 367064abe4 try and appease gcc
llvm-svn: 314442
2017-09-28 18:27:00 +00:00
Adrian Prantl 99fdb9d927 llvm-dwarfdump: implement --find for .apple_names
This patch implements the dwarfdump option --find=<name>.  This option
looks for a DIE in the accelerator tables and dumps it if found.  This
initial patch only adds support for .apple_names to keep the review
small, adding the other sections and pubnames support should be
trivial though.

Differential Revision: https://reviews.llvm.org/D38282

llvm-svn: 314439
2017-09-28 18:10:52 +00:00
Lang Hames 705db63ce1 [ORC] Fix the type of RTDyldObjectLinkingLayer::NotifyLoadedFtor.
Bug found by Stefan Granitz. Thanks Stefan!

llvm-svn: 314436
2017-09-28 17:43:07 +00:00
Evandro Menezes 3701df55c6 [JumpThreading] Preserve DT and LVI across the pass
JumpThreading now preserves dominance and lazy value information across the
entire pass.  The pass manager is also informed of this preservation with
the goal of DT and LVI being recalculated fewer times overall during
compilation.

This change prepares JumpThreading for enhanced opportunities; particularly
those across loop boundaries.

Patch by: Brian Rzycki <b.rzycki@samsung.com>,
          Sebastian Pop <s.pop@samsung.com>

Differential revision: https://reviews.llvm.org/D37528

llvm-svn: 314435
2017-09-28 17:24:40 +00:00
Craig Topper ceff6da6e9 [X86] Use BWI instructions to improve lowering of v32i8 MULHU/S
Summary: If we have BWI instructions we can widen to v32i16 to do the multiply instead of splitting.

Reviewers: RKSimon, spatel, zvi

Reviewed By: zvi

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38305

llvm-svn: 314432
2017-09-28 17:00:21 +00:00
Craig Topper fd6b8a67fb [X86] Remove dead code from X86ISelDAGToDAG.cpp multiply handling
Summary:
Lowering never creates X86ISD::UMUL for 8-bit types. X86ISD::UMUL8 is used instead. If X86ISD::UMUL 8-bit were ever used it would crash.

DAGCombiner replaces UMUL_LOHI/SMUL_LOHI with a wider MUL and a shift if the type twice as wide is legal. So we should never see i8 UMUL_LOHI/SMUL_LOHI. In fact I think there was a bug in part of the i8 code. Similar is true for i16 though without the bug.

Reviewers: RKSimon, spatel, zvi

Reviewed By: zvi

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38276

llvm-svn: 314430
2017-09-28 16:56:36 +00:00
Craig Topper 71a8cf9f99 [X86] Use correct subvector index when combining two insert subvectors featuring zero vectors.
Previously we were using one of the subvector indices twice. The included test case causes an assert without this change.

Thanks to Simon Pilgrim for catching this.

llvm-svn: 314429
2017-09-28 16:53:16 +00:00
Ulrich Weigand 0f1de04979 [SystemZ] Custom-expand ATOMIC_CMP_AND_SWAP_WITH_SUCCESS
The SystemZ compare-and-swap instructions already provide the "success"
indication via a condition-code value, so the default expansion of those
operations generates an unnecessary extra comparsion.

llvm-svn: 314428
2017-09-28 16:22:54 +00:00
Jonas Devlieghere 35fdaa94f7 [dwarfdump] Verify that CUs have a unit DIE.
This patch adds a check to the DWARF verifier to detect CUs without a
unit DIE.

Differential revision: https://reviews.llvm.org/D38363

llvm-svn: 314426
2017-09-28 15:57:50 +00:00
Simon Pilgrim 2ff339303e Use SDValue::getConstantOperandVal helper. NFCI.
llvm-svn: 314425
2017-09-28 15:53:27 +00:00
Simon Dardis c8e33c5ca1 [mips] Remove codegen support for branch likely instructions.
This patch disables codegen support for branch likely instructions to
address a potential bug. These branches were unselectable as
they had the same patterns as the normal branches but came after them
when ISel was concerned.

The branch likely instructions were marked as having no delay
slots when they have annulling delay slots. The delay slot filler
does not currently handle annulling delay slot branches, so this
would lead to wrong codegen if these branches were generated.

Reviewers: atanasyan, nitesh.jain

Differential Revision: https://reviews.llvm.org/D38169

llvm-svn: 314421
2017-09-28 15:24:07 +00:00
Hans Wennborg 6519562bc6 Docs: fix link to Debugger intrinsic functions
llvm-svn: 314420
2017-09-28 15:16:37 +00:00
Benjamin Kramer c965b30e54 [LoopUnroll] Fix use after poison.
llvm-svn: 314418
2017-09-28 14:47:39 +00:00
Amara Emerson bb16282fb1 [X86] Add overflow intrinsic test in preparation for D38161.
This commit adds the test file before codegen changes as requested in
D38161 to make it easier to see the difference.

llvm-svn: 314416
2017-09-28 13:43:48 +00:00
Bjorn Pettersson 715a5efaad [DebugInfo] Do not extend range for physreg in LiveDebugVariables
Summary:
A DBG_VALUE that is referring to a physical register is
valid up until the next def of the register, or the end
of the basic block that it belongs to.

LiveDebugVariables is computing live intervals (slot index
ranges) for DBG_VALUE instructions, before regalloc, in order
to be able to re-insert DBG_VALUE instructions again after
regalloc. When the DBG_VALUE is mapping a variable to a
physical register we do not need to compute the range. We
should simply re-insert the DBG_VALUE at the start position.

The problem that was found, resulting in this patch, was a
situation when the DBG_VALUE was the last real use of the
physical register. The computeIntervals/extendDef methods
extended the range to cover the whole basic block, even though
the physical register very well could be allocated to some
virtual register inside the basic block. So the extended
range could not be trusted.

This patch is a preparation for https://reviews.llvm.org/D38229,
where the goal is to insert DBG_VALUE after each new definition
of a variable, even if the virtual registers that the variable
was connected to has been coalesced into using the same physical
register (e.g. due to two address instructions). For more info
see https://bugs.llvm.org/show_bug.cgi?id=34545

Reviewers: aprantl, rnk, echristo

Reviewed By: aprantl

Subscribers: Ka-Ka, llvm-commits

Differential Revision: https://reviews.llvm.org/D38140

llvm-svn: 314414
2017-09-28 13:10:06 +00:00
Benjamin Kramer 8df9bfcd8a [LoopInfo] Don't poison random memory regions.
The second argument for Allocator::Deallocate is the number of elements,
not the size of a single element. In asan mode specifying a large number
of elements poisoned random memory regions, leading to crashes
everywhere.

llvm-svn: 314413
2017-09-28 12:53:20 +00:00
Florian Hahn 8af01573a3 [LVI] Move LVILatticeVal class to separate header file (NFC).
Summary:
This allows sharing the lattice value code between LVI and SCCP (D36656). 

It also adds a `satisfiesPredicate` function, used by D36656.

Reviewers: davide, sanjoy, efriedma

Reviewed By: sanjoy

Subscribers: mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D37591

llvm-svn: 314411
2017-09-28 11:09:22 +00:00
Coby Tayree 566348f2a0 [x86][AsmParser] Allow some more MS size directives
MS allows the following size directives: float/double and long as synonymous to dword/qword and dword, respectively.
Differential Revision: https://reviews.llvm.org/D37190

llvm-svn: 314410
2017-09-28 11:04:08 +00:00
Sean Eveson fa8ef35e78 [llvm-cov] Create directory structure when filtering using -name*= options
Before this change using any of the -name*= command line options with an output
directory would result in a single file (functions.txt/functions.html)
containing the coverage for those specific functions. Now you get the same
directory structure as when not using any -name*= options.

Differential Revision: https://reviews.llvm.org/D38280

llvm-svn: 314396
2017-09-28 10:07:30 +00:00
Alex Bradbury 5518cbfc41 Teach TargetInstrInfo::getInlineAsmLength to parse .space directives with integer arguments
It's currently quite difficult to test passes like branch relaxation, which
requires branches with large displacement to be generated. The .space assembler
directive makes it easy to create arbitrarily large basic blocks, but
getInlineAsmLength is not able to parse it and so the size of the block is not
correctly estimated. Other backends (AArch64, AMDGPU) introduce options just
for testing that artificially restrict the ranges of branch instructions (e.g.
aarch64-tbz-offset-bits). Although parsing a single form of the .space
directive feels inelegant, it does allow a more direct testing approach.

This patch adapts the .space parsing code from
Mips16InstrInfo::getInlineAsmLength and removes it now the extra functionality
is provided by the base implementation. I want to move this functionality to
the generic getInlineAsmLength as 1) I need the same for RISC-V, and 2) I feel
other backends will benefit from more direct testing of large branch
displacements.

Differential Revision: https://reviews.llvm.org/D37798

llvm-svn: 314393
2017-09-28 09:31:46 +00:00
Hiroshi Inoue 79c0bec06e [PowerPC] eliminate partially redundant compare instruction
This is a follow-on of D37211.
D37211 eliminates a compare instruction if two conditional branches can be made based on the one compare instruction, e.g.
if (a == 0) { ... }
else if (a < 0) { ... }

This patch extends this optimization to support partially redundant cases, which often happen in while loops.
For example, one compare instruction is moved from the loop body into the preheader by this optimization in the following example.
do {
  if (a == 0) dummy1();
  a = func(a);
} while (a > 0);

Differential Revision: https://reviews.llvm.org/D38236

llvm-svn: 314390
2017-09-28 08:38:19 +00:00
Alex Bradbury 9d3f12501a [RISCV] Add common fixups and relocations
%lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to 
ensure the appropriate fixups and relocations are generated. I've added an 
instruction format field which is used in RISCVMCCodeEmitter to, for 
instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup 
(RISC-V has two 12-bit immediate encodings depending on the instruction 
type).

Differential Revision: https://reviews.llvm.org/D23568

llvm-svn: 314389
2017-09-28 08:26:24 +00:00
Mikael Holmen 07f1e2e2b3 [RegAllocGreedy]: Allow recoloring of done register if it's non-tied
Summary:
If we have a non-allocated register, we allow us to try recoloring of an
already allocated and "Done" register, even if they are of the same
register class, if the non-allocated register has at least one tied def
and the allocated one has none.

It should be easier to recolor the non-tied register than the tied one, so
it might be an improvement even if they use the same regclasses.

Reviewers: qcolombet

Reviewed By: qcolombet

Subscribers: llvm-commits, MatzeB

Differential Revision: https://reviews.llvm.org/D38309

llvm-svn: 314388
2017-09-28 08:22:35 +00:00
Alex Bradbury 52b68efdd4 [RISCV] Define RISC-V specific e_flags
Add RISC-V e_flags as defined in the ABI document:

https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#file-header

Differential Revision: https://reviews.llvm.org/D38310
Patch by Chih-Mao Chen.

llvm-svn: 314386
2017-09-28 07:54:01 +00:00
Jatin Bhateja 75001c9ed8 [X86] Adding more cases to horizontal [f]add/[f]sub for avx512.
Reviewers: jbhateja

Reviewed By: jbhateja

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38344

llvm-svn: 314385
2017-09-28 07:40:52 +00:00
George Burgess IV f8e11b803d [DAGCombiner] Fix an off-by-one error in vector logic
Without this, we could end up trying to get the Nth (0-indexed) element
from a subvector of size N.

Differential Revision: https://reviews.llvm.org/D37880

llvm-svn: 314380
2017-09-28 06:17:19 +00:00
Yonghong Song e9165f8720 bpf: add new insns for bswap_to_le and negation
This patch adds new insn, "reg = be16/be32/be64 reg",
for bswap to little endian for big-endian target (bpfeb).
It also adds new insn for negation "reg = -reg".

Currently, for source code, e.g.,
  b = -a
LLVM still prefers to generate:
  b = 0 - a
But "reg = -reg" format can be used in assembly code.

Signed-off-by: Yonghong Song <yhs@fb.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
llvm-svn: 314376
2017-09-28 02:46:11 +00:00
Sanjoy Das def1729dc4 Use a BumpPtrAllocator for Loop objects
Summary:
And now that we no longer have to explicitly free() the Loop instances, we can
(with more ease) use the destructor of LoopBase to do what LoopBase::clear() was
doing.

Reviewers: chandlerc

Subscribers: mehdi_amini, mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D38201

llvm-svn: 314375
2017-09-28 02:45:42 +00:00
Lang Hames cf771adfea [ORC] Update the GlobalMappingLayer interface to fit the error-ized layer
concept.

Add a unit-test to make sure we don't backslide, and tweak the MockBaseLayer
utility to make it easier to test this kind of thing in the future.

llvm-svn: 314374
2017-09-28 02:17:35 +00:00
Rui Ueyama 5908845a7e Fix a UBsan bot.
If we do not initialize Prefix here, Prefix.data() returns a nullptr.
Later, it is passed to memcpy. memcpy's behavior is undefined if src (or
dst) is a nullptr even if a given size is 0. That's why this code
triggered UBsan.

llvm-svn: 314368
2017-09-28 00:27:39 +00:00
Eugene Zelenko fa57bd0ced [CodeGen] Fix some Clang-tidy modernize-use-default-member-init and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 314363
2017-09-27 23:26:01 +00:00
Justin Lebar 8ea84426c9 Check for overflows when calculating the offset in GetGEPCost.
Summary:
This avoids C++ UB if the GEP is weird and the calculation overflows
int64_t, and it's also observable in the cost model's results.

Such GEPs are almost surely not valid pointers, but LLVM nonetheless
generates them sometimes.

Reviewers: sanjoy

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38337

llvm-svn: 314362
2017-09-27 23:16:56 +00:00
Galina Kistanova 1c6f0bb63e Reverted r313993.
This patch produces a crash and hexagon_vector_loop_carried_reuse_constant.ll test fails on Windows (llvm-clang-x86_64-expensive-checks-win build bot).

llvm-svn: 314361
2017-09-27 23:09:14 +00:00
Craig Topper 0cd25942f7 Revert r314017 '[InstCombine] Simplify check for RHS being a splat constant in foldICmpUsingKnownBits by just checking Op1Min==Op1Max rather than going through m_APInt.'
This reverts r314017 and similar code added in later commits. It seems to not work for pointer compares and is causing a bot failure for the last several days.

llvm-svn: 314360
2017-09-27 22:57:18 +00:00
Dylan McKay dffaaa3017 Update the description of AVR32 for the ELFDumper
AVR32 is an unrelated architecture with 32-bit addressing.

llvm-svn: 314359
2017-09-27 22:39:37 +00:00
Rui Ueyama 0dbb0f107e Fix -Wunused-variable for Release build.
llvm-svn: 314353
2017-09-27 22:03:15 +00:00
Sanjoy Das 4f3ebd537c Return the LoopUnrollResult from tryToUnrollLoop; NFC
I will use this in a later change.

llvm-svn: 314352
2017-09-27 21:45:22 +00:00
Sanjoy Das 8e8c1bc490 LoopDeletion: use return value instead of passing in LPMUpdater; NFC
I will use this refactoring in a later patch.

llvm-svn: 314351
2017-09-27 21:45:21 +00:00
Sanjoy Das 3567d3d2ec Rename LoopUnrollStatus to LoopUnrollResult; NFC
A "Result" suffix is more appropriate here

llvm-svn: 314350
2017-09-27 21:45:19 +00:00
Rui Ueyama 283f56ac03 Fix off-by-one error in TarWriter.
The tar format originally supported up to 99 byte filename. The two
extensions are proposed later: Ustar or PAX.

In the UStar extension, a pathanme is split at a '/' and its "prefix"
and "suffix" are stored in different locations in the tar header. Since
"prefix" can be up to 155 byte, it can represent up to 254 byte
filename (but exact limit depends on the location of '/' character in
a pathname.)

Our TarWriter first attempt to use UStar extension and then fallback to
PAX extension.

But there's a bug in UStar header creation. "Suffix" part must be a NUL-
terminated string, but we didn't handle it correctly. As a result, if
your filename just 100 characters long, the last character was droppped.

This patch fixes the issue.

Differential Revision: https://reviews.llvm.org/D38149

llvm-svn: 314349
2017-09-27 21:38:02 +00:00
Brian Gesiak 88f2aa12d9 [CMake] Fix typo: "in-tree" -> "in-source" (NFC)
Summary:
*In-source builds* of LLVM, in which a user invokes `cmake` from within the
LLVM source directory, or invokes `cmake -B/path/to/source/dir/of/llvm`,
are explicitly checked for and disallowed by LLVM's `CMakeLists.txt`.

*In-tree builds*, on the other hand, refer to when the source directories
of projects such as Clang are nested within the `llvm/tools` source
directory. These are not disallowed, and are in fact a common way of
building LLVM and Clang.

Revise the comment to match the logic underneath it: it checks for an
"in-source build", not an "in-tree build".

Reviewers: beanz

Reviewed By: beanz

Subscribers: mgorny

Differential Revision: https://reviews.llvm.org/D38317

llvm-svn: 314348
2017-09-27 21:37:33 +00:00
Don Hinton 53eb637115 Cleanup some problems with LLVM_ENABLE_DUMP in release builds, and
always set LLVM_ENABLE_DUMP=ON for +Asserts builds.

Differential Revision: https://reviews.llvm.org/D38306

llvm-svn: 314346
2017-09-27 21:19:56 +00:00
Rui Ueyama 23fa4de2db Do not remove a target file in FileOutputBuffer::create().
FileOutputBuffer::create() attempts to remove a target file if the file
is a regular one, which results in an unexpected result in a failure
scenario.

If something goes wrong and the user of FileOutputBuffer decides to not
call commit(), it leaves nothing. An existing file is removed, and no
new file is created.

What we should do is to atomically replace an existing file with a new
file using rename(), so that it wouldn't remove an existing file without
creating a new one.

Differential Revision: https://reviews.llvm.org/D38283

llvm-svn: 314345
2017-09-27 21:19:24 +00:00
Jessica Paquette 4cf187b5b4 [MachineOutliner] AArch64: Avoid saving + restoring LR if possible
This commit allows the outliner to avoid saving and restoring the link register
on AArch64 when it is dead within an entire class of candidates.

This introduces changes to the way the outliner interfaces with the target.
For example, the target now interfaces with the outliner using a
MachineOutlinerInfo struct rather than by using getOutliningCallOverhead and
getOutliningFrameOverhead.

This also improves several comments on the outliner's cost model.

https://reviews.llvm.org/D36721

llvm-svn: 314341
2017-09-27 20:47:39 +00:00
Craig Topper c16a472966 Revert r314249 "Recommit r314151 "[X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like the NOREX version of TEST."""
This caused PR34751

llvm-svn: 314339
2017-09-27 20:34:17 +00:00
Craig Topper e0d8290094 Revert r314248 "[X86] Don't emit X86::MOV8rr_NOREX from X86InstrInfo::copyPhysReg."
This contributed to PR34751

llvm-svn: 314338
2017-09-27 20:34:13 +00:00
Simon Pilgrim 870007b4f8 [X86][SSE] Pull out variable shuffle mask combine logic. NFCI.
Hopefully this will make it easier to vary the combine depth threshold per-target.

llvm-svn: 314337
2017-09-27 20:19:53 +00:00
Than McIntosh dee2cf67ea [CodeGen] Emit necessary .note sections for -fsplit-stack
Summary:
According to https://gcc.gnu.org/wiki/SplitStacks, the linker expects a zero-sized .note.GNU-split-stack section if split-stack is used (and also .note.GNU-no-split-stack section if it also contains non-split-stack functions), so it can handle the cases where a split-stack function calls non-split-stack function.

This change adds the sections if needed.

Fixes PR .

Reviewers: thanm, rnk, luqmana

Reviewed By: rnk

Subscribers: llvm-commits

Patch by Cherry Zhang <cherryyz@google.com>

Differential Revision: https://reviews.llvm.org/D38051

llvm-svn: 314335
2017-09-27 19:34:00 +00:00
Craig Topper 7b1d503d7f [X86] Rewrite the zero vector checks in lowerV2X128VectorShuffle to use the Zeroable APInt
We already have zeroable bits in an APInt. We might as well use that instead of checking for an all zero BUILD_VECTOR.

Differential Revision: https://reviews.llvm.org/D37950

llvm-svn: 314332
2017-09-27 18:56:20 +00:00
Craig Topper 05f71dd036 [X86] In combineLoopSADPattern, pad result with zeros and use full size add instead of using a smaller add and inserting.
In some cases the result psadbw is smaller than the type of the add that started the match. Currently in these cases we are using a smaller add and inserting the result.

If we instead combine the psadbw with zeros and use the full size add we can take advantage of implicit zeroing we get if we emit a narrower move before the add.

In a future patch, I want to make isel aware that the psadbw itself already zeroed the upper bits and remove the move entirely.

Differential Revision: https://reviews.llvm.org/D37453

llvm-svn: 314331
2017-09-27 18:36:45 +00:00
Alexey Bataev 022cc6c41e [SLP] Fix crash on propagate IR flags for undef operands of min/max
reductions.

If both operands of the newly created SelectInst are Undefs the
resulting operation is also Undef, not SelectInst. It may cause crashes
when trying to propagate IR flags because function expects exactly
SelectInst instruction, nothing else.

llvm-svn: 314323
2017-09-27 17:42:49 +00:00
Roman Lebedev 1e053ab09a [support] mapped_file_region: and fix the windows code too
Followup for r314312 / r314313
Sorry, i really failed to fully grep all the codebase :/

llvm-svn: 314321
2017-09-27 17:24:34 +00:00
Chad Rosier d8b4b06f5d [InstCombine] Gating select arithmetic optimization.
These changes faciliate positive behavior for arithmetic based select
expressions that match its translation criteria, keeping code size gated to
neutral or improved scenarios.

Patch by Michael Berg <michael_c_berg@apple.com>!

Differential Revision: https://reviews.llvm.org/D38263

llvm-svn: 314320
2017-09-27 17:16:51 +00:00
Geoff Berry c032b2beb0 [AArch64][Falkor] Ignore SP based loads in HW prefetch fixups.
Reviewers: mcrosier

Subscribers: aemerson, rengolin, javed.absar, kristof.beyls

Differential Revision: https://reviews.llvm.org/D38301

llvm-svn: 314319
2017-09-27 17:14:10 +00:00
Javed Absar 6c5605e772 [Misched] : Fix typo in comment. NFC.
llvm-svn: 314316
2017-09-27 16:39:17 +00:00
Sanjay Patel fee80d5e65 [SLP] fix typos/formatting; NFC
llvm-svn: 314315
2017-09-27 16:32:56 +00:00
Sean Eveson 1439fa6236 Revert "[llvm-cov] Create directory structure when filtering using -name*= options"
Test failures.

llvm-svn: 314314
2017-09-27 16:20:07 +00:00
Roman Lebedev 21b013ebc1 [Support] mapped_file_region::size() returns size_t
Fixup last commit, found by clang-stage1-cmake-RA-incremental bot.

llvm-svn: 314313
2017-09-27 16:08:33 +00:00
Roman Lebedev 7c983671f2 [Support] mapped_file_region: store size as size_t
Summary:
Found when testing stage-2 build with D38101.

```
In file included from /build/llvm/lib/Support/Path.cpp:1045:
/build/llvm/lib/Support/Unix/Path.inc:648:14: error: comparison 'uint64_t' (aka 'unsigned long') > 18446744073709551615 is always false [-Werror,-Wtautological-constant-compare]
  if (length > std::numeric_limits<size_t>::max()) {
      ~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```

`size_t` is `uint64_t` here, apparently, thus any `uint64_t` value
always fits into `size_t`.

Initial patch was to use some preprocessor logic to
not check if the size is known to fit at compile time.
But Zachary Turner suggested using this approach.

Reviewers: Bigcheese, rafael, zturner, mehdi_amini

Reviewed by (via email): zturner

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38132

llvm-svn: 314312
2017-09-27 15:59:16 +00:00
Sean Eveson 51b817479b [llvm-cov] Create directory structure when filtering using -name*= options
Before this change using any of the -name*= command line options with an output
directory would result in a single file (functions.txt/functions.html)
containing the coverage for those specific functions. Now you get the same
directory structure as when not using any -name*= options.

Differential Revision: https://reviews.llvm.org/D38280

llvm-svn: 314310
2017-09-27 15:37:40 +00:00
Sanjay Patel 0f9b4773c1 [SimplifyCFG] add a struct to house optional folds (PR34603)
This was intended to be no-functional-change, but it's not - there's a test diff.

So I thought I should stop here and post it as-is to see if this looks like what was expected 
based on the discussion in PR34603:
https://bugs.llvm.org/show_bug.cgi?id=34603

Notes:
 1. The test improvement occurs because the existing 'LateSimplifyCFG' marker is not carried 
    through the recursive calls to 'SimplifyCFG()->SimplifyCFGOpt().run()->SimplifyCFG()'. 
    The parameter isn't passed down, so we pick up the default value from the function signature 
    after the first level. I assumed that was a bug, so I've passed 'Options' down in all of the 
    'SimplifyCFG' calls.

 2. I split 'LateSimplifyCFG' into 2 bits: ConvertSwitchToLookupTable and KeepCanonicalLoops. 
    This would theoretically allow us to differentiate the transforms controlled by those params 
    independently.

 3. We could stash the optional AssumptionCache pointer and 'LoopHeaders' pointer in the struct too. 
    I just stopped here to minimize the diffs.

 4. Similarly, I stopped short of messing with the pass manager layer. I have another question that 
    could wait for the follow-up: why is the new pass manager creating the pass with LateSimplifyCFG 
    set to true no matter where in the pipeline it's creating SimplifyCFG passes?

    // Create an early function pass manager to cleanup the output of the
    // frontend.
    EarlyFPM.addPass(SimplifyCFGPass());

    -->

    /// \brief Construct a pass with the default thresholds
    /// and switch optimizations.
    SimplifyCFGPass::SimplifyCFGPass()
       : BonusInstThreshold(UserBonusInstThreshold),
         LateSimplifyCFG(true) {}   <-- switches get converted to lookup tables and loops may not be in canonical form

    If this is unintended, then it's possible that the current behavior of dropping the 'LateSimplifyCFG' 
    setting via recursion was masking this bug.

Differential Revision: https://reviews.llvm.org/D38138

llvm-svn: 314308
2017-09-27 14:54:16 +00:00
Haicheng Wu 3ec848bc50 [InlineCost] add visitSelectInst()
InlineCost can understand Select IR now.  This patch finds free Select IRs and
continue the propagation of SimplifiedValues, ConstantOffsetPtrs, and
SROAArgValues.

Differential Revision: https://reviews.llvm.org/D37198

llvm-svn: 314307
2017-09-27 14:44:56 +00:00
Gadi Haber 87337a2bb9 [X86][SKX][KNL] Updated regression tests to use -mattr instead of -mcpu flag.NFC.
NFC.
 Updated 8 regression tests to use -mattr instead of -mcpu flag as follows:
 -mcpu=knl --> -mattr=+avx512f
 -mcpu=skx --> -mattr=+avx512f,+avx512bw,+avx512vl,+avx512dq

The updates are as part of the preparation of a large commit to add all instruction scheduling for the SKX target.

Reviewers: delena, zvi, RKSimon
Differential Revision: https://reviews.llvm.org/D38222

Change-Id: I2381c9b5bb75ecacfca017243c22d054f6eddd14
llvm-svn: 314306
2017-09-27 14:44:15 +00:00
Zvi Rackover eb7a0bf847 X86 Tests: Unsigned saturation subtraction tests. NFC.
Summary:
Adding tests for D37534.

Commit on behalf of julia.koval@intel.com

Reviewers: n.bozhenov, zvi, spatel, DavidKreitzer

Reviewed By: zvi

Differential Revision: https://reviews.llvm.org/D37510

llvm-svn: 314305
2017-09-27 14:38:05 +00:00
Krzysztof Parzyszek d0b6ceb2a0 Typo: const MCSchedModel SchedModel -> const MCSchedModel &SchedModel
llvm-svn: 314301
2017-09-27 12:48:48 +00:00
Mikael Holmen 3bcc9f0c1f [RegAllocGreedy] Fix spelling error, "inteference" -> "interference", NFC
llvm-svn: 314299
2017-09-27 11:27:50 +00:00
Hiroshi Inoue ed1ffa49a4 [PowerPC] eliminate unconditional branch to the next instruction
This patch makes analyzeBranch eliminate unconditional branch to the next instruction.
After basic blocks are re-organized by optimizers, such as machine block placement, a BB may end with an unconditional branch to the next (fallthrough) BB. This patch removes such redundant branch instruction.

Differential Revision: https://reviews.llvm.org/D37730

llvm-svn: 314297
2017-09-27 10:33:02 +00:00
Javed Absar 1a77bcc0d2 [Misched]: Remove double call getMicroOpFactor.NFC.
Reviewed by: @MatzeB
Differential Revision: https://reviews.llvm.org/D38176

llvm-svn: 314296
2017-09-27 10:31:58 +00:00
Coby Tayree 836c50cc2f [X86][AsmParser] fix PR32035
Differential Revision: https://reviews.llvm.org/D37473

llvm-svn: 314295
2017-09-27 10:29:29 +00:00
Jonas Devlieghere 2bc4c5411f [test] Don't verify .debug_line offsets in bitcode tests.
The exact values of the .debug_line offsets should not be hard-coded in
the checks for bitcode tests.

Fixes: http://bb.pgr.jp/builders/test-llvm-i686-linux-RA/builds/543
llvm-svn: 314294
2017-09-27 10:23:34 +00:00
Simon Pilgrim 3b0d9e789e [X86][AVX] Improve (i4 bitcast (v4i1 x)) handling for 256-bit vector compare results.
As commented on D37849 and rL313547, AVX1 targets were missing a chance to use vmovmskpd for v4f64/v4i64 results for bool vector bitcasts

llvm-svn: 314293
2017-09-27 10:10:17 +00:00
Simon Pilgrim a932bfcc93 Use const where possible. NFCI.
llvm-svn: 314292
2017-09-27 10:03:17 +00:00
Jonas Devlieghere 777731ab2b [dwarfdump] Fix printing of .debug_line offset.
Fixes 32-bit buildbots:
  http://bb.pgr.jp/builders/test-llvm-i686-linux-RA/builds/542
  http://lab.llvm.org:8011/builders/clang-cmake-thumbv7-a15/builds/11533
  http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15/builds/11494

llvm-svn: 314291
2017-09-27 10:00:27 +00:00
Jonas Devlieghere 65af0f9584 [dwarfdump] Add support for -debug-line=OFFSET
This patch adds support for passing an offset to -debug-line.

Differential revision: https://reviews.llvm.org/D38240

llvm-svn: 314288
2017-09-27 09:33:45 +00:00
Jonas Devlieghere 622c563b5a [dwarfdump] Add support for -debug-loc=OFFSET
This patch adds support for passing an offset to -debug-loc.

Differential revision: https://reviews.llvm.org/D38237

llvm-svn: 314286
2017-09-27 09:33:36 +00:00
Sean Eveson 25ea19ea86 [llvm-cov] Improve const-correctness of filters. NFC.
llvm-svn: 314281
2017-09-27 08:32:36 +00:00
Sam Parker 211f47aa37 [ARM] isTruncateFree fix
I implemented isTruncateFree in rL313533, this patch fixes the logic
to match my comment, as the previous logic was too general. Now the
only truncates that are free are i64 -> i32.

Differential Revision: https://reviews.llvm.org/D38234

llvm-svn: 314280
2017-09-27 08:30:45 +00:00
Martin Pelikan de4806d321 [XRay] initialize all members of YAMLXRayRecord for -Wmissing-field-initializers
llvm-svn: 314278
2017-09-27 07:30:48 +00:00
Martin Storsjo aa1533bf9b [X86] Fix SJLJ struct offsets for x86_64
This is necessary, but not sufficient, for having working SJLJ exception
handling on x86_64.

Differential Revision: https://reviews.llvm.org/D38254

llvm-svn: 314277
2017-09-27 06:08:23 +00:00
Martin Storsjo eccaf04e40 [X86] Remove erroneous callsite offsetting in SJLJ landing pads
The callsite value is already stored indexed from 0 in
the _Unwind_Context struct. When accessed via the functions
_Unwind_GetIP and _Unwind_SetIP, the value is indexed from 1,
but those functions handle the offseting. When reading directly
from the struct here, we shouldn't subtract 1.

This matches the code generated by the ARM target, where SJLJ
exception handling is used by default on iOS.

This makes clang-built object files for 32 bit x86 mingw work when
linked with libgcc/libstdc++.

Differential Revision: https://reviews.llvm.org/D38251

llvm-svn: 314276
2017-09-27 06:08:16 +00:00
Martin Storsjo 233349fe51 [X86] Correct byte offsets and data types in a comment. NFC.
This matches the types of the struct members defined in
lib/CodeGen/SjLjEHPrepare.cpp, and the definition of this struct in libgcc.

Differential Revision: https://reviews.llvm.org/D38248

llvm-svn: 314275
2017-09-27 06:08:04 +00:00
Craig Topper 177a3923ce [X86] Use extract128BitVector in LowerMULH so we can extract from constant build vectors.
llvm-svn: 314274
2017-09-27 06:04:55 +00:00
Daniel Berlin 97f34e887f MemorySSAUpdater: Only add phis to insertedphis if we actually inserted them, not if we just found existing ones
llvm-svn: 314273
2017-09-27 05:35:19 +00:00
Craig Topper 31ccd4727b [X86] Add avx512bw command lines to the 256-bit vector idiv tests.
Some of the operations are being sign extended to 512 bits with avx512bw.

llvm-svn: 314272
2017-09-27 05:17:15 +00:00
Craig Topper 1c781338ee [SelectionDAG] Make NewSDValueDbgMsg print target specific nodes correctly by passing in the SelectionDAG.
llvm-svn: 314271
2017-09-27 05:17:14 +00:00
Martin Pelikan 8b0cdbfb1d [XRay] fix the -Werror build by handling all enum cases in switches
Followup to D32840.

llvm-svn: 314270
2017-09-27 05:10:31 +00:00
Martin Pelikan 10c873f1d9 [XRay] convert FDR arg1 log entries
Summary:
A new FDR metadata record will support logging a function call argument;
appending multiple metadata records will represent a sequence of arguments
meaning that "holes" are not representable by the buffer format.  Each
call argument is currently a 64-bit value (useful for "this" pointers and
synchronization objects).

If present, we put this argument to the function call "entry" record it
belongs to, and alter its type to notify the user of its presence.

Reviewers: dberris

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D32840

llvm-svn: 314269
2017-09-27 04:48:03 +00:00
Hongbin Zheng d1b7b2efba [SimplifyIndVar] Constant fold IV users
This patch tries to transform cases like:

for (unsigned i = 0; i < N; i += 2) {
  bool c0 = (i & 0x1) == 0;
  bool c1 = ((i + 1) & 0x1) == 1;
}
To

for (unsigned i = 0; i < N; i += 2) {
  bool c0 = true;
  bool c1 = true;
}

This commit also update test/Transforms/IndVarSimplify/replace-srem-by-urem.ll to prevent constant folding.

Differential Revision: https://reviews.llvm.org/D38272

llvm-svn: 314266
2017-09-27 03:11:46 +00:00
Jake Ehrlich ed95fce228 Reland: [llvm-objcopy] Add support for dynamic relocations
This change adds support for dynamic relocations (allocated
SHT_REL/SHT_RELA sections with a dynamic symbol table as their link).

I had to reland this because of a I wasn't initilizing some pointers.

llvm-svn: 314263
2017-09-27 00:44:00 +00:00
James Y Knight 2ea995adf0 Initialize the RelocationSectionBase::Section member.
In r314227, it wasn't always, and would thus contain random garbage.

llvm-svn: 314256
2017-09-26 22:44:01 +00:00
Jakub Kuderski 1e584a7082 [Dominators] Invalidate DFS numbers upon edge deletions
This patch makes DeleteEdge correctly invalidate DFS numbers in the
incremental updater. This should fix PR34466 and related bugs.

llvm-svn: 314254
2017-09-26 21:56:55 +00:00
Sanjoy Das eda7a86d42 [BypassSlowDivision] Improve our handling of divisions by constants
Summary:
Don't bail out on constant divisors for divisions that can be narrowed without
introducing control flow .  This gives us a 32 bit multiply instead of an
emulated 64 bit multiply in the generated PTX assembly.

Reviewers: jlebar

Subscribers: jholewinski, mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D38265

llvm-svn: 314253
2017-09-26 21:54:27 +00:00
Geoff Berry bbfa246ad3 [AArch64][Falkor] Fix bug in falkor prefetcher fix pass.
Summary:
In rare cases, loads that don't get prefetched that were marked as
strided loads could cause a crash if they occurred in a loop with other
colliding loads.

Reviewers: mcrosier

Subscribers: aemerson, rengolin, javed.absar, kristof.beyls

Differential Revision: https://reviews.llvm.org/D38261

llvm-svn: 314252
2017-09-26 21:40:46 +00:00
Geoff Berry a4b2f5df5e [AArch64][Falkor] Fix correctness bug in falkor prefetcher fix pass and correct some opcode tag computations.
Summary:
This addresses a correctness bug for LD[1234]*_POST opcodes that have
the prefetcher fix applied to them: the base register was not being
written back from the temp after being incremented, so it would appear
to never be incremented.

Also, fix some opcode tag computations based on some updated HW details
to get better tag avoidance and thus better prefetcher performance.

Reviewers: mcrosier

Subscribers: aemerson, rengolin, javed.absar, kristof.beyls

Differential Revision: https://reviews.llvm.org/D38256

llvm-svn: 314251
2017-09-26 21:40:41 +00:00
Craig Topper b7e4c94c6c [X86] Fix register class name in a comment. NFC
llvm-svn: 314250
2017-09-26 21:35:11 +00:00
Craig Topper 7f0eeb428b Recommit r314151 "[X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like the NOREX version of TEST.""
The late MOV8rr_NOREX that caused the crash has been removed.

llvm-svn: 314249
2017-09-26 21:35:09 +00:00
Craig Topper ab3c0075b8 [X86] Don't emit X86::MOV8rr_NOREX from X86InstrInfo::copyPhysReg.
This hook is called after register allocation with two physical registers. We don't need a separate instruction at that time to force register class constraints. I left in the assert though. We also have a fatal error in X86MCCodeEmitter if we ever encode an H-reg and a REX prefix.

llvm-svn: 314248
2017-09-26 21:35:06 +00:00
Craig Topper 0768bced39 [X86] Fix typo in comment. NFC
llvm-svn: 314247
2017-09-26 21:35:04 +00:00
Sam Clegg ba9fa9fd16 [WebAssembly] Model weakly defined symbols as wasm exports
Previously these were being included as both imports and
exports, with the import being satisfied by the export
(or some strong symbol) at runtime.  However proved
unnecessary and actually complicated linking as it meant
there was not a 1-to-1 mapping between a wasm function
/global index and a linker symbol.

Differential Revision: https://reviews.llvm.org/D38246

llvm-svn: 314245
2017-09-26 21:10:09 +00:00
Nemanja Ivanovic e22ebeab1a [PowerPC] Reverting sequence of patches for elimination of comparison instructions
In the past while, I've committed a number of patches in the PowerPC back end
aimed at eliminating comparison instructions. However, this causes some failures
in proprietary source and these issues are not observed in SPEC or any open
source packages I've been able to run.
As a result, I'm pulling the entire series and will refactor it to:
- Have a single entry point for easy control
- Have fine-grained control over which patterns we transform

A side-effect of this is that test cases for these patches (and modified by
them) are XFAIL-ed. This is a temporary measure as it is counter-productive
to remove/modify these test cases and then have to modify them again when
the refactored patch is recommitted.
The failure will be investigated in parallel to the refactoring effort and
the recommit will either have a fix for it or will leave this transformation
off by default until the problem is resolved.

llvm-svn: 314244
2017-09-26 20:42:47 +00:00
Michael Zuckerman 645f777e40 [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess (VF{8|16|32} stride 3)
This patch expands the support of lowerInterleavedStore to {8|16|32}x8i stride 3.

LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=3 VF={8|16|32}) .
This patch is part two of two patches and it covers the store (interlevaed) side.

The patch goal is to optimize the following sequence:
a0 a1 a2 a3 a4 a5 a6 a7
b0 b1 b2 b3 b4 b5 b6 b7
c0 c1 c2 c3 c4 c5 c6 c7

into
a0 b0 c0 a1 b1 c1 a2 b2
c2 a3 b3 c3 a4 b4 c4 a5
b5 c5 a6 b6 c6 a7 b7 c7

Reviewers:
zvi
guyblank
dorit
Ayal

Differential Revision: https://reviews.llvm.org/D37117

Change-Id: I56ced8bcbea809a37654060771911ade20246ccc
llvm-svn: 314234
2017-09-26 18:49:11 +00:00
Craig Topper 8bf622174d [InstCombine] Remove one use restriction on the shift for calls to foldICmpAndShift.
If this transformation succeeds, we're going to remove our dependency on the shift by rewriting the and. So it doesn't matter how many uses the shift has.

This distributes the one use check to other transforms in foldICmpAndConstConst that do need it.

Differential Revision: https://reviews.llvm.org/D38206

llvm-svn: 314233
2017-09-26 18:47:25 +00:00
Sam Clegg afd34c6df7 [WebAssembly] Use function/global index space in WasmSymbol
It is useful for the symbol to contain the index of the
function of global it represents in the function/global
index space.

For imports we also store the import index so that the
linker can find, for example, the signature of the
corresponding function, which is defined by the import

In the long run we need to decide whether this API
surface should be closer to binary (where imported
functions are seperate) or the wasm spec (where the
function index space is unified).

Differential Revision: https://reviews.llvm.org/D38189

llvm-svn: 314230
2017-09-26 18:21:12 +00:00
Jake Ehrlich 9f1a390f72 [llvm-objcopy] Add support for dynamic relocations
This change adds support for dynamic relocations (allocated
SHT_REL/SHT_RELA sections with a dynamic symbol table as their link).

The binary I added for the test is here:
https://drive.google.com/file/d/0B3gtIAmiMwZXSjJUZE9pUjd4M0k/view?usp=sharing

Unless support for dynamic symbol tables in yaml2obj is added this is
needed.

Differential Revision: https://reviews.llvm.org/D37915

llvm-svn: 314227
2017-09-26 18:02:25 +00:00
Artem Belevich bab95c7087 [NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins.
Differential Revision: https://reviews.llvm.org/D38191

llvm-svn: 314223
2017-09-26 17:07:23 +00:00
Simon Atanasyan 62b8ebb5ca [mips] Use llvm-dwarfdump to simplify the test. NFC
llvm-svn: 314222
2017-09-26 17:02:35 +00:00
Craig Topper f51913155c [X86] Add support for v16i32 UMUL_LOHI/SMUL_LOHI
Summary: This patch extends the v8i32/v4i32 custom lowering to support v16i32

Reviewers: zvi, RKSimon

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38274

llvm-svn: 314221
2017-09-26 16:43:57 +00:00
Krzysztof Parzyszek 9801d7fd9f [Hexagon] Fix a typo: #ifndef DEBUG -> #ifndef NDEBUG
llvm-svn: 314216
2017-09-26 15:31:15 +00:00
Krzysztof Parzyszek 1665b3db40 [Hexagon] Fix initialization of HexagonSubtarget
Make sure that "initializeSubtargetDependencies" sets all members that
InstrInfo and the like may depend on.

llvm-svn: 314214
2017-09-26 15:06:37 +00:00
Jonas Devlieghere 8af2387b91 [dwarfdump] Skip 'stripped' sections
When dsymutil generates the companion file, its strips all unnecessary
sections by omitting their body and setting the offset in their
corresponding load command to zero.

One such section is the .eh_frame section, as it contains runtime
information rather than debug information and is part of the __TEXT
segment. When reading this section, we would just read the number of
bytes specified in the load command, starting from offset 0 (i.e. the
beginning of the file).

Rather than trying to parse this obviously invalid section, dwarfdump
now skips this.

Differential revision: https://reviews.llvm.org/D38135

llvm-svn: 314208
2017-09-26 14:22:35 +00:00
Simon Pilgrim dac6fd4170 [X86][XOP] Merge rotation opcodes with AVX512 equivalents. NFCI.
The XOP rotations act as ROTL with +ve values and ROTR with -ve values, which means that we can treat them all as ROTL with unsigned modulo. We already check that we're only trying to lower as ROTL for XOP rotations.

Differential Revision: https://reviews.llvm.org/D37949

llvm-svn: 314207
2017-09-26 14:12:50 +00:00
Sanjay Patel 1d04b5bacf [DSE] Merge stores when the later store only writes to memory locations the early store also wrote to (2nd try)
This is a 2nd attempt at:
https://reviews.llvm.org/rL310055
...which was reverted at rL310123 because of PR34074:
https://bugs.llvm.org/show_bug.cgi?id=34074

In this version, we break out of the inner loop after we successfully merge and kill a pair of stores. In the
earlier rev, we were continuing instead, which meant we could process the invalid info from a now dead store.

Original commit message (authored by Filipe Cabecinhas):

This fixes PR31777.

If both stores' values are ConstantInt, we merge the two stores
(shifting the smaller store appropriately) and replace the earlier (and
larger) store with an updated constant.

In the future we should also support vectors of integers. And maybe
float/double if we can.  

Differential Revision: https://reviews.llvm.org/D30703

llvm-svn: 314206
2017-09-26 13:54:28 +00:00
Coby Tayree f191fdc3fb [x86] fix pr29061
https://bugs.llvm.org//show_bug.cgi?id=29061
Don't try referencing REX-needed regs when not on 64bit mode
Aligns to GCC

Differetial Revision: https://reviews.llvm.org/D37801

llvm-svn: 314203
2017-09-26 13:28:05 +00:00
Simon Pilgrim 40687014ea Tidyup P->getComplexPatternInfo call by moving it inside if( != NULL) test. NFCI.
llvm-svn: 314202
2017-09-26 12:59:01 +00:00
Sylvestre Ledru e7d4cd639b Don't move llvm.localescape outside the entry block in the GCOV profiling pass
Summary:
This fixes https://bugs.llvm.org/show_bug.cgi?id=34714.

Patch by Marco Castelluccio

Reviewers: rnk

Reviewed By: rnk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38224

llvm-svn: 314201
2017-09-26 11:56:43 +00:00
Benjamin Kramer 4b2113a303 Revert "[X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like the NOREX version of TEST."
Makes llc crash. This reverts commit r314151.

llvm-svn: 314199
2017-09-26 10:25:27 +00:00
Jonas Devlieghere 4a5a6337f7 [dsymutil] Better support for symbol aliases
This patch adds logic to follow a symbol's aliases when the symbol name
cannot be found in the current object file. It checks the main binary
for the symbol's address and queries the current object for its aliases
(symbols with the same address) before printing out a warning.

Differential revision: https://reviews.llvm.org/D38230

llvm-svn: 314198
2017-09-26 08:17:28 +00:00
Uriel Korach 0ecc984b1b [X86] Finishing broadcastf32x2 and broadcasti32x2 intrinsics lowering to IR. llvm side.
Removing X86 broadcast(f/i)32x2 intrinsics from llvm.
Adding autoUpgrade support.
Moving matching tests from avx512dq-intrinsics.ll to avx512dq-intrinsics-upgrade.ll and from avx512dqvl-intrinsics.ll to avx512dqvl-intrinsics-upgrade.ll.

Differential Revision: https://reviews.llvm.org/D38220

llvm-svn: 314195
2017-09-26 07:39:39 +00:00
Matthias Braun c9e458ca3f CMake: Add option to set LLVM_ENABLE_DUMP
Differential Revision: https://reviews.llvm.org/D38267

llvm-svn: 314186
2017-09-26 02:36:58 +00:00
Matthias Braun cc603ee3d5 TargetLibraryInfo: Stop guessing wchar_t size
Usually the frontend communicates the size of wchar_t via metadata and
we can optimize wcslen (and possibly other calls in the future). In
cases without the wchar_size metadata we would previously try to guess
the correct size based on the target triple; however this is fragile to
keep up to date and may miss users manually changing the size via flags.
Better be safe and stop guessing and optimizing if the frontend didn't
communicate the size.

Differential Revision: https://reviews.llvm.org/D38106

llvm-svn: 314185
2017-09-26 02:36:57 +00:00
Dylan McKay f2c83670f7 [AVR] Fix the build after setting alignment to 1 in r314179
Changing all types to be byte-aligned broke a small number of tests.

llvm-svn: 314183
2017-09-26 02:07:54 +00:00
Dylan McKay 1446eedbc2 [AVR] Prefer BasicBlock::getIterator over Function::begin()
Thanks to Eli Friedman for the suggestion.

llvm-svn: 314182
2017-09-26 01:37:53 +00:00
Dylan McKay dada014781 [AVR] When lowering shifts into loops, put newly generated MBBs in the same
spot as the original MBB

Discovered in 
https://github.com/avr-rust/rust/issues/62

Patch by Gergo Erdi.

llvm-svn: 314180
2017-09-26 00:51:03 +00:00
Dylan McKay 832c4a65c0 [AVR] Use 1-byte alignment for all data types
This was an oversight in the original backend data layout.

The AVR architecture does not have the concept of unaligned loads - all
loads/stores from all addresses are aligned to one byte.

Discovered in avr-rust issue 
https://github.com/avr-rust/rust/issues/64

Patch By Gergo Erdi.

llvm-svn: 314179
2017-09-26 00:45:27 +00:00
Vedant Kumar 305e1b56e3 [docs] llvm-cov: Make docs for boolean options more consistent
llvm-svn: 314176
2017-09-25 23:10:04 +00:00
Vedant Kumar feb3f5272f [llvm-cov] Warn if -show-functions is used without query files
llvm-cov's report mode does not print any output when -show-functions is
specified and no source files are specified. This can be surprising, so
the tool should at least print out an error message when this happens.

rdar://problem/34636859

llvm-svn: 314175
2017-09-25 23:10:03 +00:00
Adrian Prantl cbbcf2f843 Modernize comments
llvm-svn: 314174
2017-09-25 22:51:26 +00:00
Adrian Prantl 4bdf4d1835 Modernize comments
llvm-svn: 314173
2017-09-25 22:51:15 +00:00
Vlad Tsyrklevich 998b220e97 Add section headers to SpecialCaseLists
Summary:
Sanitizer blacklist entries currently apply to all sanitizers--there
is no way to specify that an entry should only apply to a specific
sanitizer. This is important for Control Flow Integrity since there are
several different CFI modes that can be enabled at once. For maximum
security, CFI blacklist entries should be scoped to only the specific
CFI mode(s) that entry applies to.

Adding section headers to SpecialCaseLists allows users to specify more
information about list entries, like sanitizer names or other metadata,
like so:

  [section1]
  fun:*fun1*
  [section2|section3]
  fun:*fun23*

The section headers are regular expressions. For backwards compatbility,
blacklist entries entered before a section header are put into the '[*]'
section so that blacklists without sections retain the same behavior.

SpecialCaseList has been modified to also accept a section name when
matching against the blacklist. It has also been modified so the
follow-up change to clang can define a derived class that allows
matching sections by SectionMask instead of by string.

Reviewers: pcc, kcc, eugenis, vsk

Reviewed By: eugenis, vsk

Subscribers: vitalybuka, llvm-commits

Differential Revision: https://reviews.llvm.org/D37924

llvm-svn: 314170
2017-09-25 22:11:11 +00:00
Eli Friedman edee9999c4 Revert r312724 ("[ARM] Remove redundant vcvt patterns.").
It leads to some improvements, but also a regression for the simple
case, so it's not clearly a good idea.

test/CodeGen/ARM/vcvt.ll now has test coverage to show the difference.

Ultimately, the right solution is probably to custom-lower fp-to-int
conversions, to something like ARMISD::VCVT_F32_S32 plus a bitcast.
It's hard to do the right thing when the implicit bitcast isn't visible
to DAG transforms.

llvm-svn: 314169
2017-09-25 22:07:33 +00:00
Quentin Colombet b7f45eb609 [GlobalISel] Update the documentation and comment for G_[UN]MERGE_VALUES
In r296921, we added the G_[UN]MERGE_VALUES node, but did not update the
documentation. Fixing that.

NFC.

llvm-svn: 314168
2017-09-25 22:03:06 +00:00
Quentin Colombet 1d22e943fe [GlobalISel] Update the documentation for G_SEQUENCE
This instruction has been removed in r306120.

NFC.

llvm-svn: 314167
2017-09-25 22:03:05 +00:00
Quentin Colombet 513a93d0e1 [GlobalISel] Update the documentation and comments for G_EXTRACT
In r297100, G_EXTRACT changed from a multiple results instruction to a
single result one. Update the documentation accordingly.

NFC.

llvm-svn: 314166
2017-09-25 22:03:01 +00:00
Saleem Abdulrasool 2e0d72311b X86: remove R12 from CSR on Windows x64 SwiftCC
R12 is used for the SwiftError parameter.  It is no longer a CSR as it
is used for transfer the SwiftError, and the caller must preserve it if
they need to.

llvm-svn: 314165
2017-09-25 22:00:17 +00:00
Eli Friedman 48853741ad [ARM] Fix tests for vcvt+store to return void.
This is what I meant to do in r314161; I didn't realize I'd messed up
because the generated assembly is currently identical.

llvm-svn: 314163
2017-09-25 21:55:27 +00:00
Eli Friedman 7961112df9 [ARM] Add tests for vcvt followed by store.
llvm-svn: 314161
2017-09-25 21:37:52 +00:00
Eli Friedman 7404fad205 [ARM] Regenerate vcvt test checks.
llvm-svn: 314160
2017-09-25 21:34:29 +00:00
Craig Topper 30dc9797e9 [InstCombine] Move an optimization from foldICmpAndConstConst to foldICmpUsingKnownBits
All this optimization cares about is knowing how many low bits of LHS is known to be zero and whether that means that the result is 0 or greater than the RHS constant. It doesn't matter where the zeros in the low bits came from. So we don't need to specifically look for an AND. Instead we can use known bits.

Differential Revision: https://reviews.llvm.org/D38195

llvm-svn: 314153
2017-09-25 21:15:00 +00:00
Craig Topper 5124a14d9c [X86] Don't select anyext GR32->GR64 to SUBREG_TO_REG. Use INSERT_SUBREG instead.
As far as I know SUBREG_TO_REG is stating that the upper bits are 0. But if we are just converting the GR32 with no checks, then we have no reason to say the upper bits are 0.

I don't really know how to test this today since I can't find anything that looks that closely at SUBREG_TO_REG. The test changes here seems to be some perturbance of register allocation.

Differential Revision: https://reviews.llvm.org/D38001

llvm-svn: 314152
2017-09-25 21:14:59 +00:00
Craig Topper d830f276c1 [X86] Make all the NOREX CodeGenOnly instructions into postRA pseudos like the NOREX version of TEST.
llvm-svn: 314151
2017-09-25 21:14:55 +00:00
Jake Ehrlich f5a4377333 [llvm-objcopy] Refactor code to include initialize method
This change refactors some of the code to allow for some code
deduplication in later diffs as well as just to make adding a new
section type more self contained to the class itself. The idea for this
was first mentioned by James in D 37915 and will be used in that change
as recommended.

This change follows changes for dynamic sections but precedes support
for dynamic relocations.

Differential Revision: https://reviews.llvm.org/D38008

llvm-svn: 314148
2017-09-25 20:37:28 +00:00
Sanjay Patel ecb175608f [InstCombine] remove extract-of-select vector transform (2nd try)
The 1st attempt at this:
https://reviews.llvm.org/rL314117
was reverted at:
https://reviews.llvm.org/rL314118

because of bot fails for clang tests that were checking optimized IR. That should be fixed with:
https://reviews.llvm.org/rL314144
...so try again. 

Original commit message:

The transform to convert an extract-of-a-select-of-vectors was added at:
https://reviews.llvm.org/rL194013

And a question about the validity of this transform was raised in the review:
https://reviews.llvm.org/D1539:
...but not answered AFAICT>

Most of the motivating cases in that patch are now handled by other combines. These are the tests that were added with
the original commit, but they are not regressing even after we remove the transform in this patch.

The diffs we see after removing this transform cause us to avoid increasing the instruction count, so we don't want to do
those transforms as canonicalizations.

The motivation for not turning a vector-select-of-vectors into a scalar operation is shown in PR33301:
https://bugs.llvm.org/show_bug.cgi?id=33301
...in those cases, we'll get vector ops with this patch rather than the vector/scalar mix that we currently see.

Differential Revision: https://reviews.llvm.org/D38006

llvm-svn: 314147
2017-09-25 20:30:53 +00:00
Benjamin Kramer 82b7103a69 [Hexagon] Avoid unused variable warnings in Release builds.
No functionality change intended.

llvm-svn: 314143
2017-09-25 19:42:20 +00:00
Justin Lebar d31d5e6aa2 Revert "[NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins.", rL314135.
Causing assertion failures on macos:

> Assertion failed: (Num < NumOperands && "Invalid child # of SDNode!"),
> function getOperand, file
> /Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/llvm/include/llvm/CodeGen/SelectionDAGNodes.h,
> line 835.

http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/42739/testReport/LLVM/CodeGen_NVPTX/surf_read_cuda_ll/

llvm-svn: 314142
2017-09-25 19:41:56 +00:00
Konstantin Belochapka 741099bc0f [X86] [ASM INTEL SYNTAX] fix for incorrect assembler code generation when x86-asm-syntax=intel (PR34617).
Fix for incorrect code generation when x86-asm-syntax=intel.
Differential Revision: https://reviews.llvm.org/D37945

llvm-svn: 314140
2017-09-25 19:26:48 +00:00
Craig Topper 5bc10ede53 [SelectionDAG] Teach simplifyDemandedBits to handle shifts by constant splat vectors
This teach simplifyDemandedBits to handle constant splat vector shifts.

This required changing some uses of getZExtValue to getLimitedValue since we can't rely on legalization using getShiftAmountTy for the shift amount.

I believe there may have been a bug in the ((X << C1) >>u ShAmt) handling where we didn't check if the inner shift was too large. I've fixed that here.

I had to add new patterns to ARM because the zext/sext the patterns were trying to look for got turned into an any_extend with this patch. Happy to split that out too, but not sure how to test without this change.

Differential Revision: https://reviews.llvm.org/D37665

llvm-svn: 314139
2017-09-25 19:26:08 +00:00
Alexey Bataev b3aec7a636 [SLP] Add a test for PR32086, NFC.
llvm-svn: 314137
2017-09-25 19:12:59 +00:00
Krzysztof Parzyszek 7e604deca9 [Hexagon] Better determination of register classes in bit tracker
Add two callbacks to MachineEvaluator, so that specific implementations
can specify more details about register classes:
- composeWithSubRegIndex(RC,Idx), to provide the register class for a
  register from RC used in conjunction with a subregister index Idx.
- getPhysRegBitWidth(Reg), to provide the size in bits of the given
  physical register.

llvm-svn: 314136
2017-09-25 19:12:55 +00:00
Artem Belevich 9941ee9529 [NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins.
Differential Revision: https://reviews.llvm.org/D38191

llvm-svn: 314135
2017-09-25 18:53:57 +00:00
Krzysztof Parzyszek d72bd83479 [Hexagon] Make getHexagonSubRegIndex take reference instead of pointer
llvm-svn: 314134
2017-09-25 18:49:42 +00:00
Craig Topper ba3cc2e0da [AVX-512] Replace large number of explicit patterns that check for insert_subvector with zero after masked compares with fewer patterns with predicate
This replaces the large number of patterns that handle every possible case of zeroing after a masked compare with a few simpler patterns that use a predicate to check for a masked compare producer.

This is similar to what we do for detecting free GR32->GR64 zero extends and free xmm->ymm/zmm zero extends.

This shrinks the isel table from ~590k to ~531k. This is a roughly 10% reduction in size.

Differential Revision: https://reviews.llvm.org/D38217

llvm-svn: 314133
2017-09-25 18:43:13 +00:00
Hongbin Zheng bbe448abd8 [SimplifyIndvar] Minor change to refine r314125, NFC
llvm-svn: 314130
2017-09-25 18:10:36 +00:00
Arnold Schwaighofer b45717adda ARM: One more fix for swifterror CSR set
We use a differently ordered CSR set if the frame pointer is pushed. Add a
matching ..._SwiftError version.

llvm-svn: 314128
2017-09-25 17:51:33 +00:00
Hongbin Zheng f0093e45c4 [SimplifyIndvar] Replace the srem used by IV if we can prove both of its operands are non-negative
Since now SCEV can handle 'urem', an 'urem' is a better canonical form than an 'srem' because it has well-defined behavior

This is a follow up of D34598

Differential Revision: https://reviews.llvm.org/D38072

llvm-svn: 314125
2017-09-25 17:39:40 +00:00
Benjamin Kramer a23c1a37d0 [ARM] Fix -Wdangling-else warning.
A ternary is clearer here. No functionality change.

llvm-svn: 314123
2017-09-25 17:35:38 +00:00
Arnold Schwaighofer ae4de58a5b ARM: Use the proper swifterror CSR list on platforms other than darwin
Noticed by inspection

llvm-svn: 314121
2017-09-25 17:19:50 +00:00
Sanjay Patel aa7f750bec revert r314117 because there are bogus clang tests that depend on the optimizer
llvm-svn: 314118
2017-09-25 17:00:04 +00:00
Sanjay Patel 9639897d77 [InstCombine] remove extract-of-select vector transform
The transform to convert an extract-of-a-select-of-vectors was added at:
rL194013

And a question about the validity of this transform was raised in the review:
https://reviews.llvm.org/D1539:
...but not answered AFAICT>

Most of the motivating cases in that patch are now handled by other combines. These are the tests that were added with
the original commit, but they are not regressing even after we remove the transform in this patch.

The diffs we see after removing this transform cause us to avoid increasing the instruction count, so we don't want to do
those transforms as canonicalizations.

The motivation for not turning a vector-select-of-vectors into a scalar operation is shown in PR33301:
https://bugs.llvm.org/show_bug.cgi?id=33301
...in those cases, we'll get vector ops with this patch rather than the vector/scalar mix that we currently see.

Differential Revision: https://reviews.llvm.org/D38006

llvm-svn: 314117
2017-09-25 16:41:34 +00:00
Michael Liao b30286d81c Remove trailing whitespaces.
llvm-svn: 314115
2017-09-25 16:21:21 +00:00
Reid Kleckner 8898cd8dcf [DebugInfo] Sort the SDDbgValue list before assuming it is in IR order
Summary:
This code iterates the 'Orders' vector in parallel with the DbgValue
list, emitting all DBG_VALUEs that occurred between the last IR order
insertion point and the next insertion point. This assumes the
SDDbgValue list is sorted in IR order, which it usually is. However, it
is not sorted when a node with a debug value is replaced with another
one. When this happens, TransferDbgValues is called, and the new value
is added to the end of the list.

The problem can be solved by stably sorting the list by IR order.

Reviewers: aprantl, Ka-Ka

Reviewed By: aprantl

Subscribers: MatzeB, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D38197

llvm-svn: 314114
2017-09-25 16:14:53 +00:00
Reid Kleckner 09e75c9399 Use {} instead of make_pair and an iterator for the insertion point, NFC
llvm-svn: 314113
2017-09-25 16:14:39 +00:00
Michael Zuckerman 4a97df01c4 [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess (VF8 stride 4):
This patch expands the support of lowerInterleavedStore to 8x8i stride 4.

LLVM creates suboptimal shuffle code-gen for AVX2.
In overall, this patch is a specific fix for the pattern (Strid=4 VF=8) and we plan to include more patterns in the future.

The patch goal is to optimize the following sequence:
At the end of the computation, we have xmm2, xmm0, xmm12 and xmm3 holding
each 8 chars:

c0, c1, , c7
m0, m1, , m7
y0, y1, , y7
k0, k1, ., k7

And these need to be transposed/interleaved and stored like so:

c0 m0 y0 k0 c1 m1 y1 k1 c2 m2 y2 k2 c3 m3 y3 k3 ....

Reviewers
DavidKreitzer
Farhana
zvi
igorb
guyblank
RKSimon
Ayal

Differential Revision: https://reviews.llvm.org/D36058

Change-Id: I3cc5c2ca5d6318901c192a4428493b99ef424c32
llvm-svn: 314109
2017-09-25 14:50:38 +00:00
Nemanja Ivanovic f7bc9ce378 [PowerPC] Eliminate compares - add i64 sext/zext handling for SETLT/SETGT
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential review.

llvm-svn: 314106
2017-09-25 14:05:46 +00:00
Chad Rosier 71070856e6 [AArch64] Add basic support for Qualcomm's Saphira CPU.
llvm-svn: 314105
2017-09-25 14:05:00 +00:00
Michael Zuckerman ac1d20dea7 Adding missing feature to goldmont.
Change-Id: I1ddc619169fae6a56308deef8dae5db3da702cf4
llvm-svn: 314103
2017-09-25 13:45:31 +00:00
Alexey Bataev ccce7afee8 [SLP] Support for horizontal min/max reduction.
Summary:
SLP vectorizer supports horizontal reductions for Add/FAdd binary operations. Patch adds support for horizontal min/max reductions.
Function getReductionCost() is split to getArithmeticReductionCost() for binary operation reductions and getMinMaxReductionCost() for min/max reductions.
Patch fixes PR26956.

Reviewers: spatel, mkuper, hfinkel, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D27846

llvm-svn: 314101
2017-09-25 13:34:59 +00:00
Clement Courbet 2807c0a442 [CodeGenPrepare][NFC] Rename TargetTransformInfo::expandMemCmp -> TargetTransformInfo::enableMemCmpExpansion.
Summary:
Right now there are two functions with the same name, one does the work
and the other one returns true if expansion is needed. Rename
TargetTransformInfo::expandMemCmp to make it more consistent with other
members of TargetTransformInfo.

Remove the unused Instruction* parameter.

Differential Revision: https://reviews.llvm.org/D38165

llvm-svn: 314096
2017-09-25 06:35:16 +00:00
Craig Topper 47e14ead54 [X86] Make IFMA instructions during isel so we can fold broadcast loads.
This required changing the ISD opcode for these instructions to have the commutable operands first and the addend last. This way tablegen can autogenerate the additional patterns for us.

llvm-svn: 314083
2017-09-24 19:30:55 +00:00
Craig Topper 4ffd90c504 [X86] Add tests to show missed opportunities to fold broadcast loads into IFMA instructions when the load is on operand1 of the instrinsic.
We need to enable commuting during isel to catch this since the load folding tables can't handle broadcasts.

llvm-svn: 314082
2017-09-24 19:30:54 +00:00
Craig Topper 23f1830748 [X86] Add IFMA instructions to the load folding tables and make them commutable for the multiply operands.
llvm-svn: 314080
2017-09-24 17:28:14 +00:00
Simon Pilgrim 6ef8a7ed74 Fix signed/unsigned warning
llvm-svn: 314078
2017-09-24 14:00:52 +00:00
Simon Pilgrim e1335b1c75 [X86][SSE] Add more tests for shuffle combining with extracted vector elements (PR22415)
llvm-svn: 314077
2017-09-24 13:45:49 +00:00
Simon Pilgrim a705db9a9e [X86][SSE] Add support for extending bool vectors bitcasted from scalars
This patch acts as a reverse to combineBitcastvxi1 - bitcasting a scalar integer to a boolean vector and extending it 'in place' to the requested legal type.

Currently this doesn't handle AVX512 at all - but the current mask register approach is lacking for some cases.

Differential Revision: https://reviews.llvm.org/D35320

llvm-svn: 314076
2017-09-24 13:42:31 +00:00
Nemanja Ivanovic f894ce35d0 [PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential review.

llvm-svn: 314073
2017-09-24 05:48:11 +00:00
Craig Topper eb5c411218 [AVX-512] Add pattern for selecting masked version of v8i32/v8f32 compare instructions when VLX isn't available.
We use a v16i32/v16f32 compare instead and truncate the result. We already did this for the unmasked version, but were missing the version with 'and'.

llvm-svn: 314072
2017-09-24 05:24:52 +00:00
Craig Topper 675bdd30c6 [X86] Make sure we still mark the full register as implicitly defined when we shrink 256/512 bit zeroing xors to 128-bit.
Not sure if anything really cares, but this seems like the right thing to do.

llvm-svn: 314071
2017-09-24 05:24:51 +00:00
Dylan McKay f9e291a2f6 [AVR] Implement getCmpLibcallReturnType().
This fixes the avr-rust issue () with floating-point comparisons generating broken code.
By default, LLVM assumes these comparisons return 32-bit values, but ours are 8-bit.

Patch By Thomas Backman.

llvm-svn: 314070
2017-09-24 01:07:26 +00:00
Davide Italiano 2122119150 [Verifier] Stop accepting broken DIGlobalVariable(s).
The code wasn't yelling at the user when there's a reference
from a DIGlobalVariableExpression. Thanks to Adrian for the
reduced testcase. Fixes PR34672.

llvm-svn: 314069
2017-09-24 01:06:35 +00:00
Simon Pilgrim 026727f861 [X86] Regenerate i64 to v2f32 bitcast test
llvm-svn: 314068
2017-09-23 19:18:29 +00:00
Sanjay Patel fa8bad8a0f [x86] reduce 64-bit mask constant to 32-bits by right shifting
This is a follow-up from D38181 (r314023). We have to put 64-bit
constants into a register using a separate instruction, so we
should try harder to avoid that.

From what I see, we're not likely to encounter this pattern in the 
DAG because the upstream setcc combines from this don't (usually?) 
produce this pattern. If we fix that, then this will become more 
relevant. Since the cost of handling this case is just loosening 
the predicate of the existing fold, we might as well do it now.

llvm-svn: 314064
2017-09-23 14:32:07 +00:00
Sanjay Patel 5ca9f7a0cb [x86] add an add+shift test for follow-up suggestion from D38181; NFC
llvm-svn: 314063
2017-09-23 14:24:07 +00:00
Nemanja Ivanovic 35db4f956a [PowerPC] Eliminate compares - add i32 sext/zext handling for SETULT/SETUGT
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential revision.

llvm-svn: 314062
2017-09-23 12:53:03 +00:00
Nemanja Ivanovic c4980799ab [PowerPC] Eliminate compares - add i32 sext/zext handling for SETULE/SETUGE
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential revision.

llvm-svn: 314060
2017-09-23 09:50:12 +00:00
Craig Topper 092c2f4357 [X86] Move the getInsertVINSERTImmediate and getExtractVEXTRACTImmediate helper functions over to X86ISelDAGToDAG.cpp
Redefine them to call getI8Imm and return that directly.

llvm-svn: 314059
2017-09-23 05:34:07 +00:00
Craig Topper 492282d4e2 [X86] Remove is the isVINSERT*Index/isVEXTRACT*Index predicates from isel.
The only insert_subvector/extract_subvector nodes that make it to isel are guaranteed to match.

llvm-svn: 314058
2017-09-23 05:34:06 +00:00
Nemanja Ivanovic 41c4a109d8 [PowerPC] Eliminate compares - add i32 sext/zext handling for SETLT/SETGT
As mentioned in https://reviews.llvm.org/D33718, this simply adds another
pattern to the compare elimination sequence and is committed without a
differential revision.

llvm-svn: 314055
2017-09-23 04:41:34 +00:00
Reid Kleckner 2590edf615 Commit missing fixes for tool_file_rename
llvm-svn: 314051
2017-09-23 01:04:42 +00:00
Reid Kleckner 3fc649cb76 [Support] Rename tool_output_file to ToolOutputFile, NFC
This class isn't similar to anything from the STL, so it shouldn't use
the STL naming conventions.

llvm-svn: 314050
2017-09-23 01:03:17 +00:00
Eugene Zelenko 8e30a1c607 [CodeGen] Fix build bots which uses old Clang broken in r314046. (NFC)
llvm-svn: 314049
2017-09-22 23:55:32 +00:00
Eugene Zelenko f193332994 [CodeGen] Fix some Clang-tidy modernize-use-default-member-init and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 314046
2017-09-22 23:46:57 +00:00
Konstantin Belochapka 3477711ec7 [X86] [MC] fixed non optimal encoding of instruction memory operand (PR24038).
Fixed suboptimal encoding of instruction memory operand when assembler is used to select 32 bit fixup rather than 8 bit immediate for encoding memory offset value.
Differential Revision: https://reviews.llvm.org/D38117

llvm-svn: 314044
2017-09-22 23:37:48 +00:00
Reid Kleckner 8db6260098 Fix uninteneded fallthrough detected by GCC warning
llvm-svn: 314043
2017-09-22 23:19:52 +00:00
Craig Topper ea927baee2 [InstCombine] Teach foldICmpUsingKnownBits to simplify SLE/SGE/ULE/UGE to equality comparisons when the min/max ranges intersect in a single value.
This is the inverse of what we do for SGT/SLT/UGT/ULT.

llvm-svn: 314032
2017-09-22 21:47:22 +00:00
Craig Topper 73a998908f [InstCombine] Add test cases for known bits simplifications for comparisons that don't depend on constant RHS. NFC
This shows some missing simplifications for sge/sle/uge/ule relative to their non-equality counterparts.

llvm-svn: 314031
2017-09-22 21:47:21 +00:00
Craig Topper 615729b305 [InstCombine] Remove a FIXME from a test that was fixed in r314025.
llvm-svn: 314030
2017-09-22 21:47:20 +00:00
Ilya Biryukov a423c738b1 Fixed broken links in docs.
Replaced references to `llvm.org/klaus` with `git.llvm.org/klaus`.

llvm-svn: 314028
2017-09-22 21:10:37 +00:00
Sanjay Patel ac76201d4e [x86] remove over-specified platform from test config
llvm-svn: 314027
2017-09-22 21:07:13 +00:00
Stefan Pintilie 590eb2755d [PowerPC] Mark P9 scheduling model complete
This patch just adds the missing information to the P9 scheduling model to allow
the model to be marked as complete.

The model has been verified against P9 documentation. The model was verified
with utils/schedcover.py.

Differential Revision: https://reviews.llvm.org/D35695

llvm-svn: 314026
2017-09-22 20:17:25 +00:00
Craig Topper 3f364aa908 [InstCombine] Add constant splat handling to one of the ICMP_SLT/SGT cases in foldICmpUsingKnownBits.
llvm-svn: 314025
2017-09-22 19:54:15 +00:00
Sanjay Patel 0c723bb017 [x86] shiftRightAlgebraic -> shiftRightArithmetic; NFC
x86 re-education camp is in session. The LLVM LangRef agrees with x86 too.
The DAG nodes are undocumented and ambiguous as always. :)

llvm-svn: 314024
2017-09-22 19:49:37 +00:00
Sanjay Patel 3339954fa3 [x86] swap order of srl (and X, C1), C2 when it saves size
The (non-)obvious win comes from saving 3 bytes by using the 0x83 'and' opcode variant instead of 0x81. 
There are also better improvements based on known-bits that allow us to eliminate the mask entirely.

As noted, this could be extended. There are potentially other wins from always shifting first, but doing
that reveals a tangle of problems in other pattern matching. We do this transform generically in 
instcombine, but we often have icmp IR that doesn't match that pattern, so we must account for this
in the backend.

Differential Revision: https://reviews.llvm.org/D38181

llvm-svn: 314023
2017-09-22 19:37:21 +00:00
Craig Topper 3edda87c42 [InstCombine] Move the call to isSignBitCheck into getDemandedBitsLHSMask instead of calling it outside and passing its result through a flag. NFCI
The result of the isSignBitCheck isn't used anywhere else and this allows us to share the m_APInt call in the likely case that it isn't a sign bit check.

llvm-svn: 314018
2017-09-22 18:57:23 +00:00
Craig Topper 5b35b68785 [InstCombine] Simplify check for RHS being a splat constant in foldICmpUsingKnownBits by just checking Op1Min==Op1Max rather than going through m_APInt.
llvm-svn: 314017
2017-09-22 18:57:22 +00:00
Craig Topper 2c9b7d7894 [InstCombine] Make cases for ICMP_UGT/ICMP_ULT use similar formatting since they use similar code. NFC
llvm-svn: 314016
2017-09-22 18:57:20 +00:00
Rafael Espindola d901deee6e Move code to a helper function. NFC.
Part of a patch by Jake Ehrlich!

llvm-svn: 314012
2017-09-22 18:40:14 +00:00
Rafael Espindola 0bd982b79f llvm-ar: align the first archive member consistently.
Before we were aligning the member after the symbol table to 4 but
other members to 8.

llvm-svn: 314010
2017-09-22 18:36:00 +00:00
Tim Shen cee7536188 [XRay] support conditional return on PPC.
Summary: Conditional returns were not taken into consideration at all. Implement them by turning them into jumps and normal returns. This means there is a slightly higher performance penalty for conditional returns, but this is the best we can do, and it still disturbs little of the rest.

Reviewers: dberris, echristo

Subscribers: sanjoy, nemanjai, hiraditya, kbarton, llvm-commits

Differential Revision: https://reviews.llvm.org/D38102

llvm-svn: 314005
2017-09-22 18:30:02 +00:00
Krzysztof Parzyszek 7725e497d1 [TableGen] Replace InfoByHwMode::getAsString with writeToStream
Also add operator<< for use with raw_ostream to InfoByHwMode and its
derived classes.

Recommitting r313989 with the fix for unresolved references: explicitly
define the operator<< in namespace llvm.

llvm-svn: 314004
2017-09-22 18:29:37 +00:00
Guozhi Wei bce228ca42 [TargetTransformInfo] Handle intrinsic call in getInstructionLatency()
Usually an intrinsic is a simple target instruction, it should have a small latency. A real function call has much larger latency. So handle the intrinsic call in function getInstructionLatency().

Differential Revision: https://reviews.llvm.org/D38104

llvm-svn: 314003
2017-09-22 18:25:53 +00:00
Rafael Espindola d5d77372d4 llvm-ar: Don't add an unnecessary alignment in gnu mode.
This is mostly for getting stricter testing in preparation for future
changes.

llvm-svn: 314000
2017-09-22 18:16:13 +00:00
Balaram Makam a1e7ecc734 [Falkor] Add falkor CPU to host detection
This returns "falkor" for Falkor CPU.

llvm-svn: 313998
2017-09-22 17:46:36 +00:00
Simon Pilgrim 8c4d061562 Remove trailing whitespace. NFCI.
llvm-svn: 313996
2017-09-22 16:57:28 +00:00
Pranav Bhandarkar 09273239d1 Check vector elements for equivalence in the HexagonVectorLoopCarriedReuse pass
If the two instructions being compared for equivalence have corresponding operands
that are integer constants, then check their values to determine equivalence.

Patch by Suyog Sarda!

llvm-svn: 313993
2017-09-22 16:43:31 +00:00
Krzysztof Parzyszek 9b64c51739 Revert "[TableGen] Replace InfoByHwMode::getAsString with writeToStream"
This reverts commit r313989: it breaks Windows bots.

llvm-svn: 313990
2017-09-22 16:18:35 +00:00
Krzysztof Parzyszek d55727e873 [TableGen] Replace InfoByHwMode::getAsString with writeToStream
Also add operator<< for use with raw_ostream to InfoByHwMode and its
derived classes.

llvm-svn: 313989
2017-09-22 16:06:35 +00:00
Daniel Neilson 1341ac2ced [SCEV] Generalize folding of trunc(x)+n*trunc(y) into folding m*trunc(x)+n*trunc(y)
Summary:
A SCEV such as:
 {%v2,+,((-1 * (trunc i64 (-1 * %v1) to i32)) + (-1 * (trunc i64 %v1 to i32)))}<%loop>

can be folded into, simply, {%v2,+,0}. However, the current code in ::getAddExpr()
will not try to apply the simplification m*trunc(x)+n*trunc(y) -> trunc(trunc(m)*x+trunc(n)*y)
because it only keys off having a non-multiplied trunc as the first term in the simplification.

This patch generalizes this code to try to do a more generic fold of these trunc
expressions.

Reviewers: sanjoy

Reviewed By: sanjoy

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37888

llvm-svn: 313988
2017-09-22 15:47:57 +00:00
Sanjay Patel ae42181db4 [x86] remove unnecessary OS specifier from test
llvm-svn: 313986
2017-09-22 14:38:57 +00:00
Sanjay Patel 04fd5b8cdc [x86] auto-generate complete checks; NFC
llvm-svn: 313985
2017-09-22 14:30:52 +00:00
Sanjay Patel 8dca7080b0 [x86] update test to use FileCheck; NFC
llvm-svn: 313984
2017-09-22 14:29:47 +00:00
Simon Pilgrim 6f05a743f7 [TableGen] Return StringRef from ValueTypeByHwMode::getMVTName
Avoid unnecessary std::string creations during TypeSetByHwMode::writeToStream.

Found during investigations into PR28222

Differential Revision: https://reviews.llvm.org/D38174

llvm-svn: 313983
2017-09-22 13:32:26 +00:00
Alexander Ivchenko 34498ba052 [X86] Combining CMOVs with [ANY,SIGN,ZERO]_EXTEND for cases where CMOV has constant arguments
Combine CMOV[i16]<-[SIGN,ZERO,ANY]_EXTEND to [i32,i64] into CMOV[i32,i64].
One example of where it is useful is:

before (20 bytes)
    <foo>:
    test $0x1,%dil
    mov $0x307e,%ax
    mov $0xffff,%cx
    cmovne %ax,%cx
    movzwl %cx,%eax
    retq

after (18 bytes)
    <foo>:
    test $0x1,%dil
    mov $0x307e,%ecx
    mov $0xffff,%eax
    cmovne %ecx,%eax
    retq

Reviewers: craig.topper, aaboud, spatel, RKSimon, zvi

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D36711

llvm-svn: 313982
2017-09-22 13:21:39 +00:00
Artur Pilipenko 889dc1e3a5 Rework loop predication pass
We've found a serious issue with the current implementation of loop predication.
The current implementation relies on SCEV and this turned out to be problematic.
To fix the problem we had to rework the pass substantially. We have had the
reworked implementation in our downstream tree for a while. This is the initial
patch of the series of changes to upstream the new implementation.

For now the transformation is limited to the following case:
  * The loop has a single latch with either ult or slt icmp condition.
  * The step of the IV used in the latch condition is 1.
  * The IV of the latch condition is the same as the post increment IV of the guard condition.
  * The guard condition is ult.

See the review or the LoopPredication.cpp header for the details about the
problem and the new implementation.

Reviewed By: sanjoy, mkazantsev

Differential Revision: https://reviews.llvm.org/D37569

llvm-svn: 313981
2017-09-22 13:13:57 +00:00
Nemanja Ivanovic cea42b7fff Remove the default clause from a fully-covering switch
to appease bots that use a compiler that warns about this
and use -Werror.

llvm-svn: 313980
2017-09-22 12:26:00 +00:00
Andre Vieira 640527f7f1 [ARM] Fix assembly and disassembly for VMRS/VMSR
Reviewed by: t.p.northover
Differential Revision: https://reviews.llvm.org/D36306

llvm-svn: 313979
2017-09-22 12:17:42 +00:00
Nemanja Ivanovic d6f93f5143 Recommit r310809 with a fix for the spill problem
This patch re-commits the patch that was pulled out due to a
problem it caused, but with a fix for the problem. The fix
was reviewed separately by Eric Christopher and Hal Finkel.

Differential Revision: https://reviews.llvm.org/D38054

llvm-svn: 313978
2017-09-22 11:50:25 +00:00
Simon Pilgrim 2b1c3bb25d [ARM] Add missing selection patterns for vnmla
For the following function:

  double fn1(double d0, double d1, double d2) {
    double a = -d0 - d1 * d2;
    return a;
  }

on ARM, LLVM generates code along the lines of

  vneg.f64  d0, d0
  vmls.f64  d0, d1, d2

i.e., a negate and a multiply-subtract.

The attached patch adds instruction selection patterns to allow it to generate the single instruction

  vnmla.f64  d0, d1, d2

(multiply-add with negation) instead, like GCC does.

Committed on behalf of @gergo- (Gergö Barany)

Differential Revision: https://reviews.llvm.org/D35911

llvm-svn: 313972
2017-09-22 09:50:52 +00:00
Jonas Devlieghere 489604cd11 [dwarfdump] Fix ambiguous call to make_unique
Fix buildbot failures:
 - http://lab.llvm.org:8011/builders/lldb-x86-windows-msvc2015/builds/13153
 - http://lab.llvm.org:8011/builders/lld-x86_64-win7/builds/13566

llvm-svn: 313971
2017-09-22 09:38:52 +00:00
Alexander Richardson c46750ef42 [obj2yaml] Don't crash for input files without symbol table
Summary: Previously we would dereference Symtab without checking for null.

Reviewers: davide, atanasyan, rafael

Reviewed By: davide, atanasyan

Differential Revision: https://reviews.llvm.org/D38080

llvm-svn: 313970
2017-09-22 09:30:40 +00:00
Jonas Devlieghere 8f719bacd0 [dwarfdump] Add support for redirecting output to a file
This patch adds the -o and --out-file options for compatibility with
Darwin's dwarfdump.

Differential revision: https://reviews.llvm.org/D38125

llvm-svn: 313969
2017-09-22 09:20:57 +00:00
Alexander Richardson eb5ce8b92a [mips] clang-format MipsTargetMachine.cpp
This is my test commit as it only changes two lines

llvm-svn: 313968
2017-09-22 08:52:03 +00:00
Dylan McKay b7926ba50a [AVR] Remove the 'IsN64' argument to 'MCELFObjectWriter'
This has since been removed.

llvm-svn: 313965
2017-09-22 06:32:23 +00:00
Jatin Bhateja c034d36024 [X86] Updating the test case for FMF propagation.
Differential Revision: https://reviews.llvm.org/D38163

llvm-svn: 313964
2017-09-22 05:48:20 +00:00
Yonghong Song d2e0d1fa11 bpf: initial 32-bit ALU encoding support in assembler
This patch adds instruction patterns for operations in BPF_ALU. After this,
assembler could recognize some 32-bit ALU statement. For example, those listed
int the unit test file.

Separate MOV patterns are unnecessary as MOV is ALU operation that could reuse
ALU encoding infrastructure, this patch removed those redundant patterns.

Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
llvm-svn: 313961
2017-09-22 04:36:36 +00:00
Yonghong Song 3c63b101de bpf: add 32bit register set
Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
llvm-svn: 313960
2017-09-22 04:36:35 +00:00
Yonghong Song d03fef970b bpf: refactor inst patterns with better inheritance
Arithmetic and jump instructions, load and store instructions are sharing
the same 8-bit code field encoding,

A better instruction pattern implemention could be the following inheritance
relationships, and each layer only encoding those fields which start to
diverse from that layer. This avoids some redundant code.

  InstBPF -> TYPE_ALU_JMP -> ALU/JMP
  InstBPF -> TYPE_LD_ST -> Load/Store

Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
llvm-svn: 313959
2017-09-22 04:36:34 +00:00
Yonghong Song 3bf1a8d04e bpf: refactor inst patterns with more mnemonics
Currently, eBPF backend is using some constant directly in instruction patterns,
This patch replace them with mnemonics and removed some unnecessary temparary
variables.

Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
llvm-svn: 313958
2017-09-22 04:36:32 +00:00
Saleem Abdulrasool ba7a75c7b2 AArch64: support SwiftCC properly on AAPCS64
The previous SwiftCC support for AAPCS64 was partially correct.  It
setup swiftself parameters in the proper register but failed to setup
swifterror in the correct register.  This would break compilation of
swift code for non-Darwin AAPCS64 conforming environments.

llvm-svn: 313956
2017-09-22 04:31:44 +00:00
Sanjoy Das 388b012f4e Rename markAsErased to erase, as pointed out in a previous review; NFC
llvm-svn: 313951
2017-09-22 01:47:41 +00:00
NAKAMURA Takumi fec5e10890 HexagonVectorLoopCarriedReuse.cpp: Apply LLVM_ATTRIBUTE_UNUSED. [-Wunused-function]
llvm-svn: 313947
2017-09-22 01:01:33 +00:00
NAKAMURA Takumi 05f6015fbd Reformat.
llvm-svn: 313946
2017-09-22 01:01:31 +00:00
Richard Trieu cc10e633d9 Fix unused variable warning.
Move function call into debug macro to suppress unused variable warning
in non-debug builds.

llvm-svn: 313942
2017-09-21 23:48:01 +00:00
Eugene Zelenko fb7f792f55 [CodeGen] Fix some Clang-tidy modernize-use-bool-literals and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 313941
2017-09-21 23:20:16 +00:00
Adrian Prantl f3a0e8e84e Fix a bug in a historic bitcode testcase.
llvm-svn: 313940
2017-09-21 23:14:55 +00:00
Adrian Prantl ba17c241b9 Fix a bug in a historic bitcode testcase. NFC.
llvm-svn: 313939
2017-09-21 23:14:52 +00:00
Rafael Espindola 25cbdf25a6 Convert the archive writer to use Error.
This found one place in lld that was not checking the error.

llvm-svn: 313937
2017-09-21 23:13:36 +00:00
Pranav Bhandarkar 3306fff625 [Hexagon] - Fix testcase for the HexagonVectorLoopCarriedReuse pass.
llvm-svn: 313936
2017-09-21 23:11:28 +00:00
Rafael Espindola fa08397f20 Use raw_ostream in functions that don't need to seek. NFC.
llvm-svn: 313935
2017-09-21 23:06:23 +00:00
Rafael Espindola 540a8c7fad Simplify the logic for truncating UID and GID. NFC.
llvm-svn: 313933
2017-09-21 23:00:55 +00:00
Rafael Espindola 8f094c94fd Revert "Add a testfile that I missed in a previous commit that added HexagonVectorLoopCarriedReuse pass"
This reverts commit r313926.

It was failing in some bots.

llvm-svn: 313931
2017-09-21 22:57:43 +00:00
Zachary Turner 0aa02c08a7 Resubmit "[lit] Refactor out some more common lit configuration code."
There were two issues, one Python 3 specific related to Unicode,
and another which is that the tool substitution for lld no longer
rejected matches where a / preceded the tool name.

llvm-svn: 313928
2017-09-21 22:16:40 +00:00
Pranav Bhandarkar 91ebfac486 Add a testfile that I missed in a previous commit that
added HexagonVectorLoopCarriedReuse pass

llvm-svn: 313926
2017-09-21 21:52:24 +00:00
Pranav Bhandarkar 931d0b7aff Enable the reuse of values computed in a previous loop iteration.
This patch adds a pass that removes the computation of provably redundant
expressions that have been computed earlier in a previous iteration. It
relies on the use of PHIs to identify loop carried dependences.

This is scalar replacement for vector types.

llvm-svn: 313925
2017-09-21 21:48:23 +00:00