Commit Graph

37241 Commits

Author SHA1 Message Date
Alex Lorenz b853fa6bff [macCatalyst] Print out macCatalyst in llvm-objdump for the platform
'macCatalyst' is more readable than 'maccatalyst'.

llvm-svn: 365064
2019-07-03 17:46:30 +00:00
Robert Lougher 720baf0416 [X86] Avoid SFB - Skip meta instructions
This patch generalizes the fix in D61680 to ignore all meta instructions,
not just debug info.

Patch by Chris Dawson.

Differential Revision: https://reviews.llvm.org/D62605

llvm-svn: 365061
2019-07-03 17:43:55 +00:00
Francis Visoiu Mistrih 83bbe2f418 [CodeGen] Make branch funnels pass the machine verifier
We previously marked all the tests with branch funnels as
`-verify-machineinstrs=0`.

This is an attempt to fix it.

1) `ICALL_BRANCH_FUNNEL` has no defs. Mark it as `let OutOperandList =
(outs)`

2) After that we hit an assert: ``` Assertion failed: (Op.getValueType()
!= MVT::Other && Op.getValueType() != MVT::Glue && "Chain and glue
operands should occur at end of operand list!"), function AddOperand,
file
/Users/francisvm/llvm/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp,
line 461.  ```

The chain operand was added at the beginning of the operand list. Move
that to the end.

3) After that we hit another verifier issue in the pseudo expansion
where the registers used in the cmps and jmps are not added to the
livein lists. Add the `EFLAGS` to all the new MBBs that we create.

PR39436

Differential Review: https://reviews.llvm.org/D54155

llvm-svn: 365058
2019-07-03 17:16:45 +00:00
Teresa Johnson 79e50166f8 [ThinLTO] Fix gcc warnings from commit
Remove an unnecessary const from an Optional return type introduced
in r364960 that gcc 7.4.0 warns about. It is unnecessary and possibly
incorrect.

llvm-svn: 365047
2019-07-03 15:12:38 +00:00
James Molloy fa4aac7335 [SelectionDAG] Propagate alias metadata to target intrinsic nodes
When a target intrinsic has been determined to touch memory, we construct a MachineMemOperand during SDAG construction. In this case, we should propagate AAMDNodes metadata to the MachineMemOperand where available.

Differential revision: https://reviews.llvm.org/D64131

llvm-svn: 365043
2019-07-03 14:33:29 +00:00
Eugene Leviant 5cacb91475 [ThinLTO] Optimize writeonly globals out
Differential revision: https://reviews.llvm.org/D63444

llvm-svn: 365040
2019-07-03 14:14:52 +00:00
Oliver Stannard 830b20344b [ARM] Thumb2: favor R4-R7 over R12/LR in allocation order when opt for minsize
For Thumb2, we prefer low regs (costPerUse = 0) to allow narrow
encoding. However, current allocation order is like:
  R0-R3, R12, LR, R4-R11

As a result, a lot of instructs that use R12/LR will be wide instrs.

This patch changes the allocation order to:
  R0-R7, R12, LR, R8-R11
for thumb2 and -Osize.

In most cases, there is no extra push/pop instrs as they will be folded
into existing ones. There might be slight performance impact due to more
stack usage, so we only enable it when opt for min size.

https://reviews.llvm.org/D30324

llvm-svn: 365014
2019-07-03 09:58:52 +00:00
Roman Lebedev c4b83a6054 [Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)
Summary:
This is the backend part of [[ https://bugs.llvm.org/show_bug.cgi?id=42457 | PR42457 ]].
In middle-end, we'd want to prefer the form with two adds - D63992,
but as this diff shows, not every target will prefer that pattern.

Out of 4 targets for which i added tests all seem to be ok with inc-of-add for scalars,
but only X86 prefer that same pattern for vectors.

Here i'm adding a new TLI hook, always defaulting to the inc-of-add,
but adding AArch64,ARM,PowerPC overrides to prefer inc-of-add only for scalars.

Reviewers: spatel, RKSimon, efriedma, t.p.northover, hfinkel

Reviewed By: efriedma

Subscribers: nemanjai, javed.absar, kristof.beyls, kbarton, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64090

llvm-svn: 365010
2019-07-03 09:41:35 +00:00
Amara Emerson cac1151845 [AArch64][GlobalISel] Overhaul legalization & isel or shifts to select immediate forms.
There are two main issues preventing us from generating immediate form shifts:
1) We have partial SelectionDAG imported support for G_ASHR and G_LSHR shift
immediate forms, but they currently don't work because the amount type is
expected to be an s64 constant, but we only legalize them to have homogenous
types.

To deal with this, first we introduce a custom legalizer to *only* custom legalize
s32 shifts which have a constant operand into a s64.

There is also an additional artifact combiner to fold zexts(g_constant) to a
larger G_CONSTANT if it's legal, a counterpart to the anyext version committed
in an earlier patch.

2) For G_SHL the importer can't cope with the pattern. For this I introduced an
early selection phase in the arm64 selector to select these forms manually
before the tablegen selector pessimizes it to a register-register variant.

Differential Revision: https://reviews.llvm.org/D63910

llvm-svn: 364994
2019-07-03 01:49:06 +00:00
Chen Zheng dfdccbb26b [PowerPC] exclude ICmpZero in LSR if icmp can be replaced in later hardware loop.
Differential Revision: https://reviews.llvm.org/D63477

llvm-svn: 364993
2019-07-03 01:49:03 +00:00
Alex Lorenz 3dbdbbec84 [triple] Use 'macabi' environment name for the Mac Catalyst triples
The 'macabi' environment name is preferred instead of 'maccatalyst'.

llvm-svn: 364988
2019-07-03 01:02:43 +00:00
Nilanjana Basu c0b557744a Revert Changing CodeView debug info type record representation in assembly files to make it more human-readable & editable
This reverts r364982 (git commit 2082bf28eb)

llvm-svn: 364987
2019-07-03 00:51:49 +00:00
Jonas Devlieghere efe21088d7 [VFS] Add reverse iterator to OverlayFileSystem
Add a reverse iterator to the overlay file system. This makes it
possible to take overlays from one OverlayFileSystem, and add them to
another.

Differential revision: https://reviews.llvm.org/D64113

llvm-svn: 364986
2019-07-03 00:45:53 +00:00
Matt Arsenault 4f3472deb2 CodeGen: Set hasSideEffects = 0 on BUNDLE
The BUNDLE itself should not have side effects, and this is a property
of instructions inside the bundle. The hasProperty check already
searches for any member instructions, which was pointless since it was
overridden by this bit.

Allows me to distinguish bundles that have side effects vs. do not in
a future patch. Also fixes an unnecessary scheduling barrier in the
bundle AMDGPU uses to get PC relative addresses.

llvm-svn: 364984
2019-07-03 00:30:47 +00:00
Nilanjana Basu 2082bf28eb Changing CodeView debug info type record representation in assembly files to make it more human-readable & editable
llvm-svn: 364982
2019-07-03 00:26:23 +00:00
Alex Lorenz da1dfecd32 Add support for the 'macCatalyst' MachO platform
Mac Catalyst is a new MachO platform in macOS Catalina.
It always uses the build_version MachO load command.

Differential Revision: https://reviews.llvm.org/D64107

llvm-svn: 364981
2019-07-02 23:47:11 +00:00
Alex Lorenz 31dee6d6ed [triple] add 'macCatalyst' environment type
Mac Catalyst is a new deployment platform in macOS Catalina.

Differential Revision: https://reviews.llvm.org/D64097

llvm-svn: 364971
2019-07-02 21:37:00 +00:00
Teresa Johnson a700436323 [ThinLTO] Add summary entries for index-based WPD
Summary:
If LTOUnit splitting is disabled, the module summary analysis computes
the summary information necessary to perform single implementation
devirtualization during the thin link with the index and no IR. The
information collected from the regular LTO IR in the current hybrid WPD
algorithm is summarized, including:
1) For vtable definitions, record the function pointers and their offset
within the vtable initializer (subsumes the information collected from
IR by tryFindVirtualCallTargets).
2) A record for each type metadata summarizing the vtable definitions
decorated with that metadata (subsumes the TypeIdentiferMap collected
from IR).

Also added are the necessary bitcode records, and the corresponding
assembly support.

The follow-on index-based WPD patch is D55153.

Depends on D53890.

Reviewers: pcc

Subscribers: mehdi_amini, Prazek, inglorion, eraman, steven_wu, dexonsmith, arphaman, llvm-commits

Differential Revision: https://reviews.llvm.org/D54815

llvm-svn: 364960
2019-07-02 19:38:02 +00:00
Erik Pilkington eee944e7f9 [C++2a] Add __builtin_bit_cast, used to implement std::bit_cast
This commit adds a new builtin, __builtin_bit_cast(T, v), which performs a
bit_cast from a value v to a type T. This expression can be evaluated at
compile time under specific circumstances.

The compile time evaluation currently doesn't support bit-fields, but I'm
planning on fixing this in a follow up (some of the logic for figuring this out
is in CodeGen). I'm also planning follow-ups for supporting some more esoteric
types that the constexpr evaluator supports, as well as extending
__builtin_memcpy constexpr evaluation to use the same infrastructure.

rdar://44987528

Differential revision: https://reviews.llvm.org/D62825

llvm-svn: 364954
2019-07-02 18:28:13 +00:00
Serge Guelton 4137aeb4bf Provide basic Full LTO extension points
Differential Revision: https://reviews.llvm.org/D61738

llvm-svn: 364937
2019-07-02 15:52:39 +00:00
Matt Arsenault dd7ca4faa5 GlobalISel: Define GINodeEquiv for G_UMULH/G_SMULH
llvm-svn: 364931
2019-07-02 14:49:29 +00:00
Matt Arsenault ce690544a6 GlobalISel: Add G_FENCE
The pattern importer is for some reason emitting checks for G_CONSTANT
for the immediate operands.

llvm-svn: 364926
2019-07-02 14:16:39 +00:00
Kristof Umann 32d467041e Removed extra ; after function definition
llvm-svn: 364923
2019-07-02 13:25:41 +00:00
Roman Lebedev 7c8ee375d8 [NFC][TargetLowering] Some preparatory cleanups around 'prepareUREMEqFold()' from D63963
llvm-svn: 364921
2019-07-02 13:21:23 +00:00
Kristof Umann 6c0dcf65e7 Attempt to fix buildbot failures with MSVC
llvm-svn: 364914
2019-07-02 12:40:29 +00:00
Kristof Umann 9353421ecd [IDF] Generalize IDFCalculator to be used with Clang's CFG
I'm currently working on a GSoC project that aims to improve the the bug reports
of the analyzer. The main heuristic I plan to use is to explain values that are
a control dependency of the bug location better.

01 bool b = messyComputation();
02 int i = 0;
03 if (b) // control dependency of the bug site, let's explain why we assume val
04        // to be true
05   10 / i; // warn: division by zero

Because of this, I'd like to generalize IDFCalculator so that I could use it for
Clang's CFG: D62883.

In detail:

* Rename IDFCalculator to IDFCalculatorBase, make it take a general CFG node
  type as a template argument rather then strictly BasicBlock (but preserve
  ForwardIDFCalculator and ReverseIDFCalculator)
* Move IDFCalculatorBase from llvm/include/llvm/Analysis to
  llvm/include/llvm/Support (but leave the BasicBlock variants in
  llvm/include/llvm/Analysis)
* clang-format the file since this patch messes up git blame anyways
* Change typedef to using
* Add the new type ChildrenGetterTy, and store an instance of it in
  IDFCalculatorBase. This is important because I'll have to specialize it for
  Clang's CFG to filter out nullpointer successors, similarly to D62507.

Differential Revision: https://reviews.llvm.org/D63389

llvm-svn: 364911
2019-07-02 11:30:12 +00:00
George Rimar 9df825f429 [yaml2obj] - Allow overriding sh_offset field from the YAML.
Some of our test cases are using objects which
has sections with a broken sh_offset field.

There was no way to set it from YAML until this patch.

Differential revision: https://reviews.llvm.org/D63879

llvm-svn: 364898
2019-07-02 10:20:12 +00:00
Matt Arsenault 1410e86986 Fix broken C++ mode comment
llvm-svn: 364858
2019-07-01 22:00:59 +00:00
Aditya Nandakumar 1023a2eca3 [GlobalISel]: Allow backends to custom legalize Intrinsics
https://reviews.llvm.org/D31359

Add a hook "legalizeInstrinsic" to allow backends to override this
and custom lower/legalize intrinsics.

llvm-svn: 364821
2019-07-01 17:53:50 +00:00
Matt Arsenault 6f74f55750 GlobalISel: Implement lower for min/max
llvm-svn: 364816
2019-07-01 17:18:03 +00:00
Nicolai Haehnle 10c911db63 AMDGPU/GFX10: implement ds_ordered_count changes
Summary:
ds_ordered_count can now simultaneously operate on up to 4 dwords
in a single instruction, which are taken from (and returned to)
lanes 0..3 of a single VGPR.

Change-Id: I19b6e7b0732b617c10a779a7f9c0303eec7dd276

Reviewers: mareko, arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63716

llvm-svn: 364815
2019-07-01 17:17:52 +00:00
Matt Arsenault 1094e6a814 AMDGPU/GlobalISel: RegBankSelect for DS ordered add/swap
llvm-svn: 364811
2019-07-01 17:04:57 +00:00
Matt Arsenault 01bb075c1f GlobalISel: Add GINodeEquiv for min/max
llvm-svn: 364759
2019-07-01 13:22:04 +00:00
Matt Arsenault fbf67d88de GlobalISel: Add DAG compat for G_FCANONICALIZE
llvm-svn: 364758
2019-07-01 13:22:00 +00:00
Jeremy Morse d2b6665e33 [DebugInfo] Avoid adding too much indirection to pointer-valued variables
This patch addresses PR41675, where a stack-pointer variable is dereferenced
too many times by its location expression, presenting a value on the stack as
the pointer to the stack.

The difference between a stack *pointer* DBG_VALUE and one that refers to a
value on the stack, is currently the indirect flag. However the DWARF backend
will also try to guess whether something is a memory location or not, based
on whether there is any computation in the location expression. By simply
prepending the stack offset to existing expressions, we can accidentally
convert a register location into a memory location, which introduces a
suprise (and unintended) dereference.

The solution is to add DW_OP_stack_value whenever we add a DIExpression
computation to a stack *pointer*. It's an implicit location computed on the
expression stack, thus needs to be flagged as a stack_value.

For the edge case where the offset is zero and the location could be a register
location, DIExpression::prepend will still generate opcodes, and thus
DW_OP_stack_value must still be added.

Differential Revision: https://reviews.llvm.org/D63429

llvm-svn: 364736
2019-07-01 09:38:23 +00:00
Fangrui Song 78ee2fbf98 Cleanup: llvm::bsearch -> llvm::partition_point after r364719
llvm-svn: 364720
2019-06-30 11:19:56 +00:00
Fangrui Song 2d2cb77e45 [ADT] Implement llvm::bsearch() with std::partition_point()
Summary:
Delete the begin-end form because the standard std::partition_point
can be easily used as a replacement.

The ranges-style llvm::bsearch will be renamed to llvm::partition_point
in the next clean-up patch.

The name "bsearch" doesn't meet people's expectation because in C:

> If two or more members compare equal, which member is returned is unspecified.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D63718

llvm-svn: 364719
2019-06-30 09:17:59 +00:00
Roman Lebedev fe107fcde4 [IR][Patternmatch] Add m_SpecificInt_ULT() predicate
Summary:
Match an integer or vector with every element unsigned less than the
Threshold. For vectors, this includes constants with undefined elements.

FIXME: is it worth generalizing this to simply take ICmpInst::Predicate?

Reviewers: craig.topper, spatel, nikic

Reviewed By: spatel

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63811

llvm-svn: 364711
2019-06-29 11:51:37 +00:00
Erik Pilkington 9a6cef74d8 [demangle] Support for C++2a char8_t
llvm-svn: 364677
2019-06-28 19:54:19 +00:00
Fangrui Song 02e743586e [DebugInfo] Fix setStartAddress after r364637
llvm-svn: 364638
2019-06-28 10:10:10 +00:00
Fangrui Song 493a120259 [DebugInfo] Simplify GSYM::AddressRange and GSYM::AddressRanges
Delete unnecessary getters of AddressRange.
Simplify AddressRange::size(): Start <= End check should be checked in an upper layer.
Delete isContiguousWith() that doesn't make sense.
Simplify AddressRanges::insert. Delete commented code. Fix it when more than 1 ranges are to be deleted.
Delete trailing newline.

llvm-svn: 364637
2019-06-28 10:06:11 +00:00
Fangrui Song e662b6985a [DebugInfo] GSYM cleanups after D63104/r364427
llvm-svn: 364634
2019-06-28 08:58:05 +00:00
Sam Parker 9a92be1b35 [HardwareLoops] Loop counter guard intrinsic
Introduce llvm.test.set.loop.iterations which sets the loop counter
and also produces an i1 after testing that the count is not zero.

Differential Revision: https://reviews.llvm.org/D63809

llvm-svn: 364628
2019-06-28 07:38:16 +00:00
Alex Brachet 3b715d67dd [Support] Add fs::getUmask() function and change fs::setPermissions
Summary: This patch changes fs::setPermissions to optionally set permissions while respecting the umask. It also adds the function fs::getUmask() which returns the current umask.

Reviewers: jhenderson, rupprecht, aprantl, lhames

Reviewed By: jhenderson, rupprecht

Subscribers: sanaanajjar231288, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63583

llvm-svn: 364621
2019-06-28 03:21:00 +00:00
Matt Arsenault 3018d1845b GlobalISel: Use Register
llvm-svn: 364618
2019-06-28 01:47:44 +00:00
Matt Arsenault 5e66db6b8c GlobalISel: Convert rest of MachineIRBuilder to using Register
llvm-svn: 364615
2019-06-28 01:16:41 +00:00
Amara Emerson ecb7ac35f9 [GlobalISel][IRTranslator] Fix some PHI bugs related to jump tables when optimizations are used.
The new switch lowering code that tries to generate jump tables and range checks
were tested at -O0 on arm64, but on -O3 the generic switch lowering code goes to
town on trying to generate optimized lowerings, e.g. multiple jump tables, range
checks etc. This exposed bugs in the way PHI nodes are handled because the CFG
looks even stranger after all of this is done.

llvm-svn: 364613
2019-06-27 23:56:34 +00:00
Fedor Sergeev 92e625c223 [InlineCost] make InlineCost assignable
Summary:
Current InlineCost is not assignable because of const members Cost and Threshold.
I dont see practical benefits from having them const (access to these members is
private and internal interactions are rather simple). On other hand that makes
it hard to use as a member in some other data structure where assignability is necessary.

I'm going to use InlineCost in a downstream inliner that maintains a complex queue
of candidate call-sites and thus keeping and recalculating InlineCost is necessary.

This patch just removes 'const' from both members, making InlineCost assignable.

Reviewers: eraman, greened, chandlerc, yrouban, apilipenko
Reviewed By: apilipenko
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63823

llvm-svn: 364612
2019-06-27 23:41:03 +00:00
Roman Lebedev 29d05c005f [CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 3)
Summary:
I'm submitting a new revision since i don't understand how to reclaim/reopen/take over the existing one, D50222.
There is no such action in "Add Action" menu...

This implements an optimization described in Hacker's Delight 10-17: when `C` is constant,
the result of `X % C == 0` can be computed more cheaply without actually calculating the remainder.
The motivation is discussed here: https://bugs.llvm.org/show_bug.cgi?id=35479.

This is a recommit, the original commit rL364563 was reverted in rL364568
because test-suite detected miscompile - the new comparison constant 'Q'
was being computed incorrectly (we divided by `D0` instead of `D`).

Original patch D50222 by @hermord (Dmytro Shynkevych)

Notes:
- In principle, it's possible to also handle the `X % C1 == C2` case, as discussed on bugzilla.
  This seems to require an extra branch on overflow, so I refrained from implementing this for now.
- An explicit check for when the `REM` can be reduced to just its LHS is included:
  the `X % C` == 0 optimization breaks `test1` in `test/CodeGen/X86/jump_sign.ll` otherwise.
  I hadn't managed to find a better way to not generate worse output in this case.
- The `test/CodeGen/X86/jump_sign.ll` regresses, and is being fixed by a followup patch D63390.

Reviewers: RKSimon, craig.topper, spatel, hermord, xbolva00

Reviewed By: RKSimon, xbolva00

Subscribers: dexonsmith, kristina, xbolva00, javed.absar, llvm-commits, hermord

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63391

llvm-svn: 364600
2019-06-27 21:52:10 +00:00
Alexandre Ganea fa36593f4c Convert line endings to LF.
llvm-svn: 364590
2019-06-27 20:46:11 +00:00