Commit Graph

227 Commits

Author SHA1 Message Date
Jim Grosbach d74560b170 ARM aliases for pre-unified syntax fcmpz[sd] mnemonics.
rdar://11056647

llvm-svn: 152834
2012-03-15 20:48:18 +00:00
Kristof Beyls 327d2f9da5 Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton.
llvm-svn: 152814
2012-03-15 17:50:29 +00:00
Lang Hames 718cfbe05a Split fpscr into two registers: FPSCR and FPSCR_NZCV.
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.

llvm-svn: 152076
2012-03-06 00:19:55 +00:00
Jim Grosbach 8dc347fc27 ARM vpush/vpop assembler mnemonics accept an optional size suffix.
rdar://10988114

llvm-svn: 152068
2012-03-05 23:16:31 +00:00
Sebastian Pop 957a6583f1 updated patch for the ARM fused multiply add/sub
In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.

Patch by Ana Pazos <apazos@codeaurora.org>

llvm-svn: 152036
2012-03-05 17:39:52 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
Anton Korobeynikov 5482b9f535 Add fused multiple+add instructions from VFPv4.
Patch by Ana Pazos!

llvm-svn: 148658
2012-01-22 12:07:33 +00:00
Jim Grosbach ea2319112f ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
rdar://10558523

llvm-svn: 147189
2011-12-22 22:19:05 +00:00
Jim Grosbach b65dd04923 Remove some bogus comments.
llvm-svn: 147169
2011-12-22 19:45:01 +00:00
Jim Grosbach 489ed5929e ARM pre-UAL aliases. fcmp[sd].
llvm-svn: 147158
2011-12-22 19:20:45 +00:00
Jim Grosbach 7869d8c01e ARM VFP optional data type on VMOV GPR<-->SPR.
llvm-svn: 147104
2011-12-21 23:24:15 +00:00
Jim Grosbach e16acacc3a ARM VFP pre-UAL mnemonic aliases for fmul[sd].
llvm-svn: 146892
2011-12-19 19:43:50 +00:00
Jim Grosbach 92a939ae73 ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
llvm-svn: 146887
2011-12-19 19:02:41 +00:00
Jim Grosbach 4b0844e191 ARM NEON two-operand aliases for VQDMULH.
llvm-svn: 146514
2011-12-13 20:40:37 +00:00
Jim Grosbach 2a2348e6c2 ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
llvm-svn: 146508
2011-12-13 20:13:48 +00:00
Jim Grosbach 9227f39c53 ARM add more 'gas' compatibility aliases for NEON instructions.
llvm-svn: 146507
2011-12-13 20:08:32 +00:00
Jim Grosbach 54337b8617 ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
llvm-svn: 146300
2011-12-10 00:01:02 +00:00
Jim Grosbach 8be2f6577e ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
llvm-svn: 146296
2011-12-09 23:34:09 +00:00
Jim Grosbach 8cc83fa1b7 ARM convenience aliases for VSQRT.
llvm-svn: 146201
2011-12-08 22:51:25 +00:00
Jim Grosbach 9a6ba3c94e ARM VFP support 'fmrs/fmsr' aliases for 'vldr'
llvm-svn: 146116
2011-12-08 00:52:55 +00:00
Jim Grosbach 086d013e56 ARM VFP support 'flds/fldd' aliases for 'vldr'
llvm-svn: 146115
2011-12-08 00:49:29 +00:00
Jim Grosbach 2cf294a213 ARM tidy up and remove no longer needed InstAlias definitions.
The TokenAlias handling of data type suffices renders these unnecessary.

llvm-svn: 146010
2011-12-07 01:50:36 +00:00
Jim Grosbach a01033709f ARM VFP assembly parsing for VADD and VSUB two-operand forms.
llvm-svn: 144710
2011-11-15 22:15:10 +00:00
Jim Grosbach 84f0ba5747 ARM size suffix on VFP single-precision 'vmov' is optional.
rdar://10435114

llvm-svn: 144698
2011-11-15 21:18:35 +00:00
Jim Grosbach 5803f6d5a2 ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
Yet more of rdar://10435076.

llvm-svn: 144691
2011-11-15 20:29:42 +00:00
Jim Grosbach c5b1bc561e ARM assembly parsing for two-operand form of 'mul' instruction.
rdar://10449856.

llvm-svn: 144689
2011-11-15 20:14:51 +00:00
Jim Grosbach 3e2c6f380c ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

llvm-svn: 144583
2011-11-14 23:03:21 +00:00
Jim Grosbach 7996b15724 ARM assembly parsing type suffix options for VLDR/VSTR.
rdar://10435076

llvm-svn: 144575
2011-11-14 22:28:39 +00:00
Jim Grosbach 609d113874 ARM optional size suffix for VLDR/VSTR syntax.
llvm-svn: 144427
2011-11-11 23:34:43 +00:00
Jim Grosbach e7fbce7acb ARM assembly parsing and encoding for VMOV immediate.
llvm-svn: 141046
2011-10-03 23:38:36 +00:00
Jim Grosbach 4ab23b5273 ARM assembly parsing and encoding for VMRS/FMSTAT.
llvm-svn: 141025
2011-10-03 21:12:43 +00:00
Jim Grosbach efc761a1eb ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834
2011-09-30 00:50:06 +00:00
Owen Anderson 3e0aa03fe9 Add missing encoding information for some of the GPR<->FP register moves.
llvm-svn: 138780
2011-08-29 23:15:25 +00:00
Owen Anderson 061738a680 Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
llvm-svn: 138273
2011-08-22 21:34:00 +00:00
Owen Anderson df698b032c Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
llvm-svn: 138269
2011-08-22 20:27:12 +00:00
Owen Anderson 713406f88d Fix the broken encodings for the VFP vmov.f32 and vmov.f64 instructions, as well as the comments that explain them incorrectly.
llvm-svn: 136707
2011-08-02 18:30:00 +00:00
Owen Anderson 651b230ca0 Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
llvm-svn: 135106
2011-07-13 23:22:26 +00:00
Cameron Zwarich 148220306f The VMLA instruction and its friends are not actually fused; they're plain old
multiply-accumulate instructions with separate rounding steps.

llvm-svn: 134609
2011-07-07 08:28:52 +00:00
Jim Grosbach 29882a75eb ARM assembler support for vpush/vpop.
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.

rdar://9683231

llvm-svn: 133932
2011-06-27 20:00:07 +00:00
Jim Grosbach 7ef7ddd2df Clean up a few 80 column violations.
llvm-svn: 132946
2011-06-13 22:54:22 +00:00
Bob Wilson 3e5944d96b Some single-precision VFP instructions can execute in either the VPF or Neon
pipelines, at least on Cortex-A9.

llvm-svn: 129771
2011-04-19 18:11:38 +00:00
Owen Anderson d6c5a741b5 Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
llvm-svn: 128461
2011-03-29 16:45:53 +00:00
Jim Grosbach bb0547d9c4 Pseudo-ize VMOVDcc and VMOVScc.
llvm-svn: 127506
2011-03-11 23:09:50 +00:00
Bob Wilson 00d09428fe Remove unused conditional negate operations.
llvm-svn: 127090
2011-03-05 16:54:31 +00:00
Evan Cheng 04ad35b53f VFP single precision arith instructions can go down to NEON pipeline, but on Cortex-A8 only.
llvm-svn: 126238
2011-02-22 19:53:14 +00:00
Evan Cheng 4a8c43fe6d Some single precision VFP instructions may be executed on NEON pipeline, but not double precision ones.
llvm-svn: 125624
2011-02-16 00:35:02 +00:00
Bruno Cardoso Lopes 2082057b18 Create two new generic classes to represent the following VMRS/VMSR variations:
vmrs  reg, fpexc
vmrs  reg, fpsid
vmsr  fpexc, reg
vmsr  fpsid, reg

llvm-svn: 123783
2011-01-18 21:58:20 +00:00
Bob Wilson e5863d6639 Fix a comment: We now have intrinsics for vcvtr.
llvm-svn: 123246
2011-01-11 17:56:41 +00:00
Chris Lattner 2a0a3b43d7 Flag -> Glue, the ongoing saga
llvm-svn: 122513
2010-12-23 18:28:41 +00:00
Evan Cheng 62c7b5bf76 Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
   of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
   additional pipeline stall. So it's frequently better to single codegen
   vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
   stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
   vmla + vmla is very bad. But this isn't ideal either:
     vmul
     vadd
     vmla
   Instead, we want to expand the second vmla:
     vmla
     vmul
     vadd
   Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
   faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
   compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
   fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
   vmla / vmls will trigger one of the special hazards.

Work in progress, only A+B are enabled.

llvm-svn: 120960
2010-12-05 22:04:16 +00:00
Bill Wendling 9898ac97fd Proper encoding for VLDM and VSTM instructions. The register lists for these
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.

llvm-svn: 119460
2010-11-17 04:32:08 +00:00
Bill Wendling 02089a39a0 vldm and vstm are mnemonics for vldmia and vstmia resp.
llvm-svn: 119321
2010-11-16 02:00:24 +00:00
Bill Wendling a68e3a5397 Encode the multi-load/store instructions with their respective modes ('ia',
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>

llvm-svn: 119310
2010-11-16 01:16:36 +00:00
Bill Wendling 705ec77ab5 Add uses of the *_ldst_multi multiclasses. These aren't used yet.
llvm-svn: 118999
2010-11-13 10:57:02 +00:00
Bill Wendling c4c642832d Convert the modes to lower case.
llvm-svn: 118998
2010-11-13 10:43:34 +00:00
Bill Wendling e69afc6bb7 Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.

llvm-svn: 118995
2010-11-13 09:09:38 +00:00
Evan Cheng 2d59ee34f1 Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
llvm-svn: 118922
2010-11-12 20:32:20 +00:00
Bill Wendling a91d02bc61 Add "write back" bit encoding.
llvm-svn: 118446
2010-11-08 21:28:03 +00:00
Bill Wendling c002463ac4 Add encoding for VSTR.
llvm-svn: 118220
2010-11-04 00:59:42 +00:00
Bill Wendling e84eb99cbb The MC code couldn't handle ARM LDR instructions with negative offsets:
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144
2010-11-03 01:49:29 +00:00
Jim Grosbach c6af2b4066 Break ARM addrmode4 (load/store multiple base address) into its constituent
parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137
2010-11-03 01:01:43 +00:00
Bill Wendling 603bd8f54c Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094
2010-11-02 22:31:46 +00:00
Bill Wendling 3f37ade36e Missed reverting this bit.
llvm-svn: 117971
2010-11-01 23:17:54 +00:00
Bill Wendling f7e176a3ec Minor cleanup.
llvm-svn: 117969
2010-11-01 23:11:22 +00:00
Bill Wendling 418bd53008 Move the machine operand MC encoding patterns to the parent classes.
llvm-svn: 117956
2010-11-01 21:17:06 +00:00
Bill Wendling 2623343625 Move instruction encoding bits into the parent class and remove the temporary
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906
2010-11-01 06:00:39 +00:00
Chris Lattner 33fc3e095b reapply r117858 with apparent editor malfunction fixed (somehow I
got a dulicated line).

llvm-svn: 117860
2010-10-31 19:10:56 +00:00
Chris Lattner e59eef3dd1 revert r117858 while I check out a failure I missed.
llvm-svn: 117859
2010-10-31 19:05:32 +00:00
Chris Lattner 9293008e90 the asm matcher can't handle operands with modifiers (like ${foo:bar}).
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the 
instruction 'isCodeGenOnly'.

Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are 
doing this.

llvm-svn: 117858
2010-10-31 18:48:12 +00:00
Jim Grosbach bbe2bbd7f7 Add FIXME.
llvm-svn: 117787
2010-10-30 14:54:23 +00:00
Bill Wendling a65f914bb0 Add encoding for moving a value between two ARM core registers and a doublework
extension register.

llvm-svn: 116970
2010-10-20 23:37:40 +00:00
Bill Wendling 058190507b Add encodings for movement between ARM core registers and single-precision
registers.

llvm-svn: 116961
2010-10-20 22:44:54 +00:00
Bill Wendling 399add01d4 Reformatting. No functionalogicality changes.
llvm-svn: 116625
2010-10-15 21:50:45 +00:00
Bill Wendling 6f52f8a87d Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.

llvm-svn: 116471
2010-10-14 02:33:26 +00:00
Bill Wendling 0441c6cba0 Add encoding for 'fmstat'.
llvm-svn: 116466
2010-10-14 01:19:34 +00:00
Bill Wendling 0825f3e441 - Add encodings for multiply add/subtract instructions in all their glory.
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.

llvm-svn: 116464
2010-10-14 01:02:08 +00:00
Bill Wendling f106ecfa59 Add MC encodings for VCVT* instrunctions.
llvm-svn: 116431
2010-10-13 20:58:46 +00:00
Bill Wendling 6e27b4f530 Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
just yet.

llvm-svn: 116386
2010-10-13 01:17:33 +00:00
Bill Wendling 576fd0b110 Add encodings for VCVT instructions.
llvm-svn: 116385
2010-10-13 00:56:35 +00:00
Bill Wendling da4ddf0fcf Add VCMPZ and VABS.
llvm-svn: 116383
2010-10-13 00:38:07 +00:00
Bill Wendling f9ca535495 Refactor VCMP instructions.
llvm-svn: 116379
2010-10-13 00:04:29 +00:00
Bill Wendling 7dd8c0b991 Add encodings for VNMUL[SD].
llvm-svn: 116375
2010-10-12 23:47:37 +00:00
Bill Wendling a06aee826c Add encodings for VDIV and VMUL.
llvm-svn: 116370
2010-10-12 23:22:27 +00:00
Bill Wendling 42200bcaea Refactor some of the encoding logic into a base class. This keeps us from having
to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.

llvm-svn: 116362
2010-10-12 23:06:54 +00:00
Bill Wendling 646a506724 Add encoding for VSUB and VCMP.
Fear not! I'm going to try a refactoring right now. :)

llvm-svn: 116359
2010-10-12 22:55:35 +00:00
Bill Wendling ac6cd00706 Encoding for VADDD. Plus a test for the VFP instructions.
llvm-svn: 116348
2010-10-12 22:08:41 +00:00
Jim Grosbach 576640f0e3 Encoding for ARM-mode VADD.F32 instruction.
llvm-svn: 116338
2010-10-12 21:22:40 +00:00
Evan Cheng 1958cefd69 Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
llvm-svn: 115898
2010-10-07 01:50:48 +00:00
Eric Christopher e68635acdb Fix typo.
llvm-svn: 114931
2010-09-28 00:35:33 +00:00
Jim Grosbach abcbe2474d VFP/NEON load/store multiple instructions are addrmode4, not 5.
llvm-svn: 113322
2010-09-08 00:25:50 +00:00
Bob Wilson 13ce07fa92 Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like
all the other LDM/STM instructions.  This fixes asm printer crashes when
compiling with -O0.  I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.

Prior to this change VLDM/VSTM used addressing mode #5, but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier.  Much of the backend
was not aware of these special cases.  The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode.  I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON.  Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.

llvm-svn: 112322
2010-08-27 23:18:17 +00:00
Daniel Dunbar 07cc87438f ARM: Mark some disassembler only instructions as not available for matching --
for some reason they have a very odd MCInst form where the operands overlap, but
I haven't dug in to find out why yet.

llvm-svn: 110781
2010-08-11 04:46:13 +00:00
Nate Begeman b69b182191 Add support for getting & setting the FPSCR application register on ARM when VFP is enabled.
Add support for using the FPSCR in conjunction with the vcvtr instruction, for controlling fp to int rounding.
Add support for the FLT_ROUNDS_ node now that the FPSCR is exposed.

llvm-svn: 110152
2010-08-03 21:31:55 +00:00
Jim Grosbach 84511e1526 Clean up 80 column violations. No functional change.
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
Evan Cheng dd7f566597 Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
llvm-svn: 104111
2010-05-19 06:07:03 +00:00
Evan Cheng 79efd71962 Mark some pattern-less instructions as neverHasSideEffects.
llvm-svn: 103683
2010-05-13 00:16:46 +00:00
Anton Korobeynikov 2063705d91 Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :(
llvm-svn: 100650
2010-04-07 18:20:02 +00:00
Anton Korobeynikov c1e7a6feac FCONST{S,D} behaves the same way as FP unary instructions. This is true for both A8 and A9.
llvm-svn: 100649
2010-04-07 18:19:56 +00:00
Anton Korobeynikov 4c1da0f82a Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9.
llvm-svn: 100647
2010-04-07 18:19:46 +00:00
Jim Grosbach 34de7768bf Make the use of the vmla and vmls VFP instructions controllable via cmd line.
Preliminary testing shows significant performance wins by not using these
instructions.

llvm-svn: 99436
2010-03-24 22:31:46 +00:00