Commit Graph

3785 Commits

Author SHA1 Message Date
Hans Wennborg 9565cf581e Widen EHScope::ClenupBitFields::FixupDepth to avoid overflowing it (PR23490)
It currently only takes 2048 gotos to overflow the FixupDepth bitfield,
causing silent miscompilation. Apparently some parser generators run into
this (see PR).

I don't know that that data structure is terribly size sensitive anyway,
and since there's no room to widen the bitfield, let's just use a separate
word in EHCatchScope for it.

Differential Revision: http://reviews.llvm.org/D21566

llvm-svn: 273434
2016-06-22 16:21:14 +00:00
Michael Zuckerman 716859aa64 [Clang][bmi][intrinsics] Adding _mm_tzcnt_64 _mm_tzcnt_32 intrinsics to clang.
Differential Revision: http://reviews.llvm.org/D21373

llvm-svn: 273401
2016-06-22 12:32:43 +00:00
Craig Topper 08181f795f [AVX512] Fix _mm_setzero_di to not require avx512vl since its used by the avx512dqintrin.h. Also update the avx512dq test to not enable avx512vl feature so we can ensure correct dependencies.
llvm-svn: 273388
2016-06-22 06:36:21 +00:00
Craig Topper d1691c7026 [AVX512] Replace masked integer cmp and ucmp builtins with native IR.
llvm-svn: 273378
2016-06-22 04:47:58 +00:00
Craig Topper c56f0f8485 [AVX512] Use correct types for mask parameters in avx512vlbw cmp builtin tests.
llvm-svn: 273377
2016-06-22 04:47:55 +00:00
Peter Collingbourne aa463c2a18 Require an x86 target for the thinlto_backend.ll test.
llvm-svn: 273361
2016-06-22 01:40:47 +00:00
Peter Collingbourne 2ff9c25d93 Specify a target triple to fix the test on non-Linux.
llvm-svn: 273356
2016-06-22 01:17:30 +00:00
Peter Collingbourne 91227f2195 CodeGen: Replace test/CodeGen/thinlto_backend.c with a functional test.
This new test tests that functions are capable of being imported, rather than
that the import pass is run. This new test is compatible with the approach
being developed in D20268 which runs the importer on its own rather than in
a pass.

Differential Revision: http://reviews.llvm.org/D21542

llvm-svn: 273347
2016-06-22 00:57:26 +00:00
Pirama Arumuga Nainar a7484c9180 Emit the DWARF tag for the RenderScript language
Summary:
If the RenderScript LangOpt is set, either via '-x renderscript' or the '.rs'
file extension, set the DWARF language tag to be that of RenderScript.

Reviewers: rsmith

Subscribers: cfe-commits, srhines

Differential Revision: http://reviews.llvm.org/D21451

llvm-svn: 273321
2016-06-21 21:35:11 +00:00
Sanjay Patel a4d156980e [x86] AVX FP compare builtins should require AVX target feature (PR28112)
This is a fix for PR28112:
https://llvm.org/bugs/show_bug.cgi?id=28112

The FP comparison intrinsics that take an immediate parameter (rather than specifying
a comparison predicate in the function name) were added with AVX; these are macros in
avxintrin.h. This patch makes clang behavior match gcc (error if a program tries to use 
these without -mavx) and matches the Intel documentation, eg:
VCMPPS: m128 _mm_cmp_ps(m128 a, __m128 b, const int imm)

'V' means this is intended to only work with the AVX form of the instruction.

Differential Revision: http://reviews.llvm.org/D21306

llvm-svn: 273311
2016-06-21 20:22:55 +00:00
Dehao Chen 1997d8684f Invoke PruneEH pass before Sample Profile pass.
Summary: We need to call PruneEH pass before AutoFDO pass so that some EH-related calls can get inlined in Sample Profile pass.

Reviewers: davidxl, dnovillo

Subscribers: junbuml, llvm-commits

Differential Revision: http://reviews.llvm.org/D21197

llvm-svn: 273298
2016-06-21 19:16:41 +00:00
Artem Belevich 4987dc85b4 [aarch64] Update datalayout for aarch64 tests
This brings the tests in sync with the changes in r273280.

llvm-svn: 273289
2016-06-21 17:35:31 +00:00
Craig Topper 879b0978f4 [AVX512] Move the 128-bit and 256-bit lzcnt intrinsics to avx512vlcdintrin.h where they belong.
llvm-svn: 273249
2016-06-21 06:53:58 +00:00
Simon Pilgrim 03a899957f [X86][XOP] Refreshed builtin tests ready for creation of llvm fast-isel tests
llvm-svn: 273090
2016-06-18 18:20:14 +00:00
Simon Pilgrim c44a3b9599 [X86][TBM] Refreshed builtin tests ready for creation of llvm fast-isel tests
llvm-svn: 273086
2016-06-18 17:09:40 +00:00
David Majnemer 3370c20c7e [CodeGen] Use pointer-sized integers for ptrtoint sources
Given something like:
void *v = (void *)100;

We need to synthesize a ptrtoint operation from 100.  During constant
emission, we choose i64 as the type for our constant because it
guaranteed not to drop any bits from our CharUnits representation of the
value.  However, this is suboptimal for 32-bit targets: LLVM passes like
GlobalOpt will get confused by these sorts of casts resulting in
pessimization.

Instead, make sure the ptrtoint operand has a pointer-sized integer
type.

llvm-svn: 273020
2016-06-17 17:47:24 +00:00
Simon Pilgrim d39d026324 [X86][SSE4A] Use native IR for mask movntsd/movntss intrinsics.
Depends on llvm side commit r273002.

llvm-svn: 273003
2016-06-17 14:28:16 +00:00
Ranjeet Singh ca2b3e7b5c [ARM] Add mrrc/mrrc2 intrinsics and update existing mcrr/mcrr2 intrinsics.
Reapplying patch in r272777 which was reverted
because the llvm patch which added support
for generating the mcrr/mcrr2 instructions
from the intrinsic was causing an assertion
failure. This has now been fixed in llvm.

llvm-svn: 272983
2016-06-17 00:59:41 +00:00
George Burgess IV 419996ccb5 [CodeGen] Fix a segfault caused by pass_object_size.
This patch fixes a bug where we'd segfault (in some cases) if we saw a
variadic function with one or more pass_object_size arguments.

Differential Revision: http://reviews.llvm.org/D17462

llvm-svn: 272971
2016-06-16 23:06:04 +00:00
Sanjay Patel dbd68dd09d [x86] generate IR for AVX2 integer min/max builtins
Sibling patch to r272932:
http://reviews.llvm.org/rL272932

llvm-svn: 272933
2016-06-16 18:45:01 +00:00
Marcin Koscielnicki a46fade624 [Builtin] Make __builtin_thread_pointer target-independent.
This is now supported for ARM, AArch64, PowerPC, SystemZ, SPARC, Mips.

Differential Revision: http://reviews.llvm.org/D19589

llvm-svn: 272893
2016-06-16 13:41:54 +00:00
Sanjay Patel 280cfd1a69 [x86] translate SSE packed FP comparison builtins to IR
As noted in the code comment, a potential follow-on would be to remove
the builtins themselves. Other than ord/unord, this already works as 
expected. Eg:

  typedef float v4sf __attribute__((__vector_size__(16)));
  v4sf fcmpgt(v4sf a, v4sf b) { return a > b; }

Differential Revision: http://reviews.llvm.org/D21268

llvm-svn: 272840
2016-06-15 21:20:04 +00:00
Sanjay Patel 7495ec026e [x86] generate IR for SSE integer min/max builtins
Sibling patch to r272806:
http://reviews.llvm.org/rL272806

llvm-svn: 272807
2016-06-15 17:18:50 +00:00
Ranjeet Singh d48760da64 Reverting r272777 because one of the tests
added in the llvm patch is causing an assertion
to fail.

llvm-svn: 272790
2016-06-15 14:21:28 +00:00
Craig Topper a54c21e742 [AVX512] Use native IR for mask pcmpeq/pcmpgt intrinsics.
llvm-svn: 272787
2016-06-15 14:06:34 +00:00
Ranjeet Singh 8d5ad5bdf2 [ARM] Add mrrc/mrrc2 intrinsics and update existing mcrr/mcrr2 intrinsics.
Patch adds intrinsics for mrrc/mrrc2. The
intrinsics for mrrc/mrrc2 return a single
uint64_t to represent two 32 bit values.

The mcrr/mcrr2 intrinsic was changed to
accept a single uint64_t instead of two
32 bit values as the input for consistency.

Differential Revision: http://reviews.llvm.org/D21179

llvm-svn: 272777
2016-06-15 11:32:18 +00:00
Peter Collingbourne bcf909d737 Update clang for D20348
Differential Revision: http://reviews.llvm.org/D20339

llvm-svn: 272710
2016-06-14 21:02:05 +00:00
Hans Wennborg f8b91f8336 s/Intrin.h/intrin.h/, trying to fix the build after r272701
llvm-svn: 272702
2016-06-14 20:14:24 +00:00
Michael Zuckerman c49f6ce3e1 [Clang][avx512][Intrinsics] adding prefetch gather intrinsics
Differential Revision: http://reviews.llvm.org/D21322

llvm-svn: 272667
2016-06-14 13:45:17 +00:00
Michael Zuckerman 223676d2cc [Clang][AVX512][intrinsics] Adding missing intrinsics div_pd and div_ps
Differential Revision: http://reviews.llvm.org/D20626

llvm-svn: 272658
2016-06-14 12:38:58 +00:00
Artem Belevich 6530a3e73f Test fix -- use captured call result instead of hardcoded %2.
llvm-svn: 272573
2016-06-13 18:44:22 +00:00
David Majnemer d423574fde [immintrin] Reimplement _bit_scan_{forward,reverse}
There is no need to use a target-specific intrinsic to implement
_bit_scan_forward or _bit_scan_reverse, reimplementing them using
generic intrinsics makes it more likely that the middle end will
understand what's going on.

llvm-svn: 272564
2016-06-13 17:26:16 +00:00
Asaf Badouh 880f0c252b [X86][AVX512F] bugfix - sqrtps should get __mask16 as mask parameter
CR: Michael Zuckerman
llvm-svn: 272549
2016-06-13 15:15:57 +00:00
Simon Pilgrim beca5f295c [Clang][X86] Convert non-temporal store builtins to generic __builtin_nontemporal_store in headers
We can now use __builtin_nontemporal_store instead of target specific builtins for naturally aligned nontemporal stores which avoids the need for handling in CGBuiltin.cpp

The scalar integer nontemporal (unaligned) store builtins will have to wait as __builtin_nontemporal_store currently assumes natural alignment and doesn't accept the 'packed struct' trick that we use for normal unaligned load/stores.

The nontemporal loads require further backend support before we can safely convert them to __builtin_nontemporal_load

Differential Revision: http://reviews.llvm.org/D21272

llvm-svn: 272540
2016-06-13 09:57:52 +00:00
Craig Topper fc07498e4a [AVX512] Masked pcmpeqd, pcmpeqq, pcmpgtd, and pcmpgtq don't require avx512bw, just avx512vl.
llvm-svn: 272532
2016-06-13 04:15:11 +00:00
Simon Pilgrim 778a7eddb5 [X86][BMI] Improved bmi intrinsics checks
Ready for matching with llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll (to be added shortly)

llvm-svn: 272490
2016-06-11 22:40:01 +00:00
Craig Topper 46422562f5 [AVX512] Use a regular expression instead of checking for a specific name in a CHECK line in test.
llvm-svn: 272470
2016-06-11 13:35:43 +00:00
Craig Topper 7cc9263ec2 [AVX512] Implement masked and 512-bit pshufd intrinsics directly with __builtin_shufflevector and __builtin_ia32_select.
llvm-svn: 272467
2016-06-11 12:50:19 +00:00
Chandler Carruth c41e081f71 Fix this test to handle NDEBUG builds which don't have a name for the
basic block.

llvm-svn: 272456
2016-06-11 06:32:56 +00:00
Craig Topper 68738332b8 [AVX512] Implement 512-bit and masked shufflelo and shufflehi intrinsics directly with __builtin_shufflevector and __builtin_ia32_select. Also improve the formatting of the AVX2 version.
llvm-svn: 272452
2016-06-11 03:31:13 +00:00
Craig Topper d4273a425e [AVX512] Add _mm512_bsrli_epi128 and _mm512_bslli_epi128 intrinsics.
llvm-svn: 272451
2016-06-11 03:31:07 +00:00
Pirama Arumuga Nainar 8b788d013c RenderScript support in the Frontend
Summary:

Create a new Frontend LangOpt to specify the renderscript language. It
is enabled by the "-x renderscript" option from the driver.

Add a "kernel" function attribute only for RenderScript (an "ignored
attribute" warning is generated otherwise).

Make the NativeHalfType and NativeHalfArgsAndReturns LangOpts be implied
by the RenderScript LangOpt.

Reviewers: rsmith

Subscribers: cfe-commits, srhines

Differential Revision: http://reviews.llvm.org/D21198

llvm-svn: 272342
2016-06-09 23:34:20 +00:00
Craig Topper 2769bb5753 [X86] Handle AVX2 pslldqi and psrldqi intrinsics shufflevector creation directly in the header file instead of in CGBuiltin.cpp. Simplify the sse2 equivalents as well.
llvm-svn: 272246
2016-06-09 05:15:12 +00:00
Vitaly Buka 9d1b12c091 Specify target in lifetime-asan test.
Summary: Some target platforms -fsanitize=address.

Reviewers: pcc, eugenis

Subscribers: cfe-commits, christof, chapuni, kubabrecka

Differential Revision: http://reviews.llvm.org/D21117

llvm-svn: 272185
2016-06-08 18:18:08 +00:00
Chris Dewhurst ea61147fc7 [Sparc] Complex return value ABI compliance.
According to the Sparc V8 ABI, complex numbers should be passed and returned as pairs of registers:

https://docs.oracle.com/cd/E26502_01/html/E28387/gentextid-2734.html

This fix ensures this is the case. Without this, complex numbers are returned as a struct of two floats, which breaks the ABI rules.

Differential Review: http://reviews.llvm.org/D20955

llvm-svn: 272148
2016-06-08 14:46:05 +00:00
Igor Breger aadb876200 [AVX512] Emit select instruction instead of using x86 specific instrinsics.
This will allow us to remove the x86 instrinics from the backend.

Differential Revision: http://reviews.llvm.org/D21060

llvm-svn: 272141
2016-06-08 13:59:20 +00:00
Michael Zuckerman c4ae8537cf [Clang][AVX512][BUILTIN]Adding intrinsics for range_round_{sd|ss}
Differential Revision: http://reviews.llvm.org/D21002

llvm-svn: 272123
2016-06-08 08:19:27 +00:00
Michael Zuckerman 96d0399658 [clang][AVX512][Intrinsics] Adding intrinsics reduce_[round]_{ss|sd} to clang
Differential Revision: http://reviews.llvm.org/D21014

llvm-svn: 272012
2016-06-07 14:00:20 +00:00
Craig Topper f51cc07719 [AVX512] Convert masked palignr builtins directly to native IR similar to the other palignr builtins, but with a select to handle masking.
llvm-svn: 271873
2016-06-06 06:13:01 +00:00
Michael Zuckerman 95721ac863 [Clang][AVX512]Adding set4 intrinsics
Differential Revision: http://reviews.llvm.org/D20866

llvm-svn: 271835
2016-06-05 15:43:30 +00:00
Michael Zuckerman f36f6eb036 [Clang][AVX512][Intrinsics] Adding two definitions _mm512_setzero and _mm512_setzero_epi32
Differential Revision: http://reviews.llvm.org/D20871

llvm-svn: 271832
2016-06-05 15:12:52 +00:00
Craig Topper 4d302448ae [AVX512] Remove 512-bit andnot tests from the avx512vl test file.
llvm-svn: 271795
2016-06-04 16:37:38 +00:00
NAKAMURA Takumi 7f74dedb39 Suppress clang/test/CodeGen/lifetime-asan.c for targeting mingw.
clang.EXE: error: unsupported option '-fsanitize=address' for target 'x86_64-w64-windows-gnu'

llvm-svn: 271509
2016-06-02 10:54:45 +00:00
Sjoerd Meijer 90df4a7c31 This adds target support and tests for Cortex-A73
Differential Revision: http://reviews.llvm.org/D20864

llvm-svn: 271507
2016-06-02 10:48:37 +00:00
Asaf Badouh 89f657611c [X86][AVX512] add intrinsics of Scalar FP to integer
Differential Revision: http://reviews.llvm.org/D20861

llvm-svn: 271499
2016-06-02 08:11:35 +00:00
Michael Zuckerman 9e7d0a98fa [Clang][AVX512][INTRINSICS] adding round cvt and fix regular cvtps_ph
Differential Revision: http://reviews.llvm.org/D20870

llvm-svn: 271498
2016-06-02 07:44:08 +00:00
Vitaly Buka 9d4eb6f389 [asan] Added -fsanitize-address-use-after-scope flag
Summary:
Also emit lifetime markers for -fsanitize-address-use-after-scope.
Asan uses life-time markers for use-after-scope check.

PR27453

Reviewers: kcc, eugenis, aizatsky

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D20759

llvm-svn: 271451
2016-06-02 00:24:20 +00:00
Simon Pilgrim 00880511b1 [X86][SSE] Replace (V)CVTTPS2DQ and VCVTTPD2DQ truncating (round to zero) f32/f64 to i32 with generic IR (clang)
The 'cvtt' truncation (round to zero) conversions can be safely represented as generic __builtin_convertvector (fptosi) calls instead of x86 intrinsics. We already do this (implicitly) for the scalar equivalents.

Note: I looked at updating _mm_cvttpd_epi32 as well but this still requires a lot more backend work to correctly lower (both for debug and optimized builds).

Differential Revision: http://reviews.llvm.org/D20859

llvm-svn: 271436
2016-06-01 21:46:51 +00:00
Michael Zuckerman 6170c15fc6 [Clang][Intrinsics][avx512] Continue Adding round cvt to clang
And remove trailing spaces in intrinsic f test
Differential Revision: http://reviews.llvm.org/D20810

llvm-svn: 271398
2016-06-01 14:41:41 +00:00
Michael Zuckerman e54093fcc0 Adding front-end support to several intrinsics (bit scanning, conversion and state reading intrinsics)
Adding LLVM front-end support to two intrinsics dealing with bit scan: _bit_scan_forward and _bit_scan_reverse.
 Their functionality is as described in Intel intrinsics guide:
 https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_forward&expand=371,370
 https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bit_scan_reverse&expand=371,370

 Furthermore, adding clang front-end support to these conversion intrinsics: _mm256_cvtsd_f64, _mm256_cvtsi256_si32 and _mm256_cvtss_f32.

 Finally, adding tests to all of the above, as well as to the state reading intrinsics _rdpmc and _rdtsc.
  Their functionality is also specified in the Intel intrinsics guide.


Commit on behalf of Omer Paparo Bivas

llvm-svn: 271387
2016-06-01 12:21:00 +00:00
Michael Zuckerman e6aa66a53d [Clang][Intrinsics][avx512] Adding round intrinsics fot max/min/sqrt instruction set to clang
Differential Revision: http://reviews.llvm.org/D20812

llvm-svn: 271373
2016-06-01 08:34:03 +00:00
Michael Zuckerman c301c194ec [Clang][Intrinsics][avx512] Adding round roundscale to clang
Differential Revision: http://reviews.llvm.org/D20815

llvm-svn: 271368
2016-06-01 07:35:44 +00:00
Saleem Abdulrasool 4976634208 CodeGen: tweak CFString emission for COFF targets
The `isa' member was previously not given the correct DLL Storage.  Ensure that
we give the `isa' constant `__CFConstantStringClassReference' the correct DLL
storage.  Default to dllimport unless an explicit specification gives it a
dllexport storage.

llvm-svn: 271361
2016-06-01 04:22:24 +00:00
Matt Arsenault 6dc455fb93 AMDGPU: Update datalayout string
llvm-svn: 271297
2016-05-31 16:58:18 +00:00
Ranjeet Singh 61c47fd86a [ARM] Add load/store co-processor intrinsics.
Differential Revision: http://reviews.llvm.org/D20563

llvm-svn: 271275
2016-05-31 13:31:25 +00:00
Michael Zuckerman 186d86738d [Clang][Intrinsics][avx512] Adding round cvt to clang
Differential Revision: http://reviews.llvm.org/D20790

llvm-svn: 271265
2016-05-31 11:27:34 +00:00
Craig Topper 4b060e31c9 [AVX512] Convert masked load builtins to generic masked load intrinsics instead of the x86 specific ones.
This will allow the x86 intrinsics to be removed from the backend.

llvm-svn: 271253
2016-05-31 06:58:07 +00:00
Craig Topper 6e891fbdd2 [AVX512] Emit generic masked store instrinsics instead of using x86 specific intrinsics.
This will allow us to remove the x86 instrinics from the backend.

llvm-svn: 271246
2016-05-31 01:50:10 +00:00
Simon Pilgrim 0e90936fea [X86] Ensure load/store tests unaligned pointers really are align 1
llvm-svn: 271227
2016-05-30 19:20:55 +00:00
Simon Pilgrim 43439bd33d [X86][SSE] Added missing tests (merge failure)
Differential Revision: http://reviews.llvm.org/D20617

llvm-svn: 271219
2016-05-30 17:58:38 +00:00
Simon Pilgrim 645e1ad33a [X86][SSE] _mm_store1_ps/_mm_store1_pd should require an aligned pointer
According to the gcc headers, intel intrinsics docs and msdn codegen the _mm_store1_pd (and its _mm_store_pd1 equivalent) should use an aligned pointer - the clang headers are the only implementation I can find that assume non-aligned stores (by storing with _mm_storeu_pd).

Additionally, according to the intel intrinsics docs and msdn codegen the _mm_store1_ps (_mm_store_ps1) requires a similarly aligned pointer.

This patch raises the alignment requirements to match the other implementations by calling _mm_store_ps/_mm_store_pd instead.

I've also added the missing _mm_store_pd1 intrinsic (which maps to _mm_store1_pd like _mm_store_ps1 does to _mm_store1_ps).

As a followup I'll update the llvm fast-isel tests to match this codegen.

Differential Revision: http://reviews.llvm.org/D20617

llvm-svn: 271218
2016-05-30 17:55:25 +00:00
Craig Topper 09175dab31 [X86] Replace unaligned store builtins in SSE/AVX intrinsic files with code that will compile to a native unaligned store. Remove the builtins since they are no longer used.
Intrinsics will be removed from llvm in a future commit.

llvm-svn: 271214
2016-05-30 17:10:30 +00:00
Saleem Abdulrasool 2460a36f53 test: add explicit targets for some tests
These tests currently expect MachO section names and do not provide a target.
Explicitly provide one.

llvm-svn: 271212
2016-05-30 16:36:48 +00:00
Saleem Abdulrasool f7444e645b CodeGen: tweak CFConstantStrings for COFF and ELF
Adjust the constant CFString emission to emit into more appropriate sections on
ELF and COFF targets.  It would previously try to use MachO section names
irrespective of the file format.

llvm-svn: 271211
2016-05-30 16:23:07 +00:00
Michael Zuckerman 9fcf3552ad [Clang][avx512][builtin] Adding missing intrinsics for cvt
Differential Revision: http://reviews.llvm.org/D20618

llvm-svn: 271205
2016-05-30 13:22:12 +00:00
Rafael Espindola ab3e10a7a0 Mark test as requiring x86-registered-target.
llvm-svn: 271163
2016-05-29 02:36:16 +00:00
Rafael Espindola f8f01c3d59 Handle -Wa,--mrelax-relocations=[no|yes].
llvm-svn: 271162
2016-05-29 02:01:14 +00:00
Saleem Abdulrasool 442b88b9ec CodeGen: support blocks on COFF targets in DLLs
This extends the blocks support to support blocks with a dynamically linked
blocks runtime.  The previous code generation would work only for static builds
of the blocks runtime.  Mark the block "isa" pointers and functions as dllimport
if no explicit declaration marked with __declspec(dllexport) is found.  This
additional check allows for the use of the functionality in the runtime library
if desired.

llvm-svn: 271138
2016-05-28 19:41:35 +00:00
Craig Topper cbdbbac875 [AVX512] Add masked v16i32 and v8i64 unaligned store tests.
llvm-svn: 271134
2016-05-28 18:59:06 +00:00
Simon Pilgrim 91b77ceaed [X86][SSE] Replace VPMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (clang)
The VPMOVSX and (V)PMOVZX sign/zero extension intrinsics can be safely represented as generic __builtin_convertvector calls instead of x86 intrinsics.

This patch removes the clang builtins and their use in the sse2/avx headers - a companion patch will remove/auto-upgrade the llvm intrinsics.

Note: We already did this for SSE41 PMOVSX sometime ago.

Differential Revision: http://reviews.llvm.org/D20684

llvm-svn: 271106
2016-05-28 08:12:45 +00:00
David Majnemer e6abf3d29f [CodeGen] Don't crash when sizeof(long) != 4 for some intrins
_InterlockedIncrement and _InterlockedDecrement have 'long' in their
prototypes.  We assumed 'long' was the same size as an i32 which is
incorrect for other targets.

This fixes PR27892.

llvm-svn: 270953
2016-05-27 02:06:19 +00:00
Michael Zuckerman 22c47e606a Adding missing _mm512_castsi512_si256 intrinsic.
llvm-svn: 270851
2016-05-26 14:32:11 +00:00
Simon Pilgrim 1fdfbf6941 [X86][F16C] Improved f16c intrinsics checks
Added checks for upper elements being zero'd in scalar conversions

llvm-svn: 270836
2016-05-26 10:20:25 +00:00
Simon Pilgrim 57446efaa9 [X86][AVX2] Improved checks for float/double mask generation for non-masked gathers
llvm-svn: 270833
2016-05-26 09:56:50 +00:00
Michael Zuckerman eb5f178c4b Fix instrinsics names:
_mm128_cmp_ps_mask-->_mm_cmp_ps_mask
_mm128_mask_cmp_ps_mask-->_mm_mask_cmp_ps_mask
_mm128_cmp_pd_mask-->_mm_cmp_pd_mask
_mm128_mask_cmp_pd_mask-->_mm_mask_cmp_pd_mask

llvm-svn: 270830
2016-05-26 08:10:12 +00:00
Michael Zuckerman 6f08cebf36 [Clang][AVX512][BUILTIN] Adding intrinsics for set1
Differential Revision: http://reviews.llvm.org/D20562

llvm-svn: 270825
2016-05-26 06:54:52 +00:00
Simon Pilgrim f1ad90d509 [X86][AVX2] Full set of AVX2 intrinsics tests
llvm/test/CodeGen/X86/avx2-intrinsics-fast-isel.ll will be synced to this

llvm-svn: 270708
2016-05-25 15:10:49 +00:00
Benjamin Kramer 1f4381f810 [AVX512] Don't rely on value names. They're different in release builds.
llvm-svn: 270704
2016-05-25 14:30:01 +00:00
Michael Zuckerman d5cc6cd262 [Clang][AVX512][BUILTIN] Add missing intrinsics for cast
Differential Revision: http://reviews.llvm.org/D20523

llvm-svn: 270699
2016-05-25 14:04:21 +00:00
Denis Zobnin eebc4af0ed [ms][dll] #26935 Defining a dllimport function should cause it to be exported
If we have some function with dllimport attribute and then we have the function
definition in the same module but without dllimport attribute we should add
dllexport attribute to this function definition.
The same should be done for variables.

Example:
struct __declspec(dllimport) C3 {
  ~C3();
};
C3::~C3() {;} // we should export this definition.

Patch by Andrew V. Tischenko

Differential revision: http://reviews.llvm.org/D18953

llvm-svn: 270686
2016-05-25 11:32:42 +00:00
Simon Pilgrim 7b365bce6f [X86][SSE] Updated _mm_store_ps1 test to match _mm_store1_ps
llvm-svn: 270679
2016-05-25 09:20:08 +00:00
Craig Topper f70a61ff3f [X86] Update test cases to make sure storeu builtins use the storeu instrinsics. We were previously matching on other stores in the IR from this being an -O0 test.
We should probably look into making the storeu builtins just emit a normal store with an alignment of 1.

llvm-svn: 270664
2016-05-25 05:26:23 +00:00
Hans Wennborg 9464491aa7 Rename test/CodeGen/inline-optim.cc to .c and provide a triple
llvm-svn: 270633
2016-05-24 23:37:56 +00:00
Hans Wennborg 7a00888a08 [Driver] Add support for -finline-functions and /Ob2 flags
-finline-functions and /Ob2 are currently ignored by Clang. The only way to
enable inlining is to use the global O flags, which also enable other options,
or to emit LLVM bitcode using Clang, then running opt by hand with the inline
pass.

This patch allows to simply use the -finline-functions flag (same as GCC) or
/Ob2 in clang-cl mode to enable inlining without other optimizations.

This is the first patch of a serie to improve support for the /Ob flags.

Patch by Rudy Pons <rudy.pons@ilod.org>!

Differential Revision: http://reviews.llvm.org/D20576

llvm-svn: 270609
2016-05-24 20:40:51 +00:00
David Majnemer a38c9f1fa5 [MS Volatile] Don't make volatile loads/stores to underaligned objects atomic
Underaligned atomic LValues require libcalls which MSVC doesn't have.
MSVC doesn't seem to consider such operations as requiring a barrier
anyway.

This fixes PR27843.

llvm-svn: 270576
2016-05-24 16:09:25 +00:00
Jacob Baungard Hansen 13a4937404 [Sparc] Add software float option -msoft-float
Summary:
Following patch D19265 which enable software floating point support in the Sparc backend, this patch enables the option to be enabled in the front-end using the -msoft-float option.

The user should ensure a library (such as the builtins from Compiler-RT) that includes the software floating point routines is provided.

Reviewers: jyknight, lero_chris

Subscribers: jyknight, cfe-commits

Differential Revision: http://reviews.llvm.org/D20419

llvm-svn: 270538
2016-05-24 08:30:08 +00:00
Simon Pilgrim 90770c7c76 [X86][SSE] Replace lossless i32/f32 to f64 conversion intrinsics with generic IR
Both the (V)CVTDQ2PD(Y) (i32 to f64) and (V)CVTPS2PD(Y) (f32 to f64) conversion instructions are lossless and can be safely represented as generic __builtin_convertvector calls instead of x86 intrinsics without affecting final codegen.

This patch removes the clang builtins and their use in the sse2/avx headers - a future patch will deal with removing the llvm intrinsics, but that will require a bit more work.

Differential Revision: http://reviews.llvm.org/D20528

llvm-svn: 270499
2016-05-23 22:13:02 +00:00
Michael Zuckerman f86eb71616 [clang][AVX512][Builtin] adding missing intrinsics for vpmultishiftqb{128|256|512} instruction set .
Differential Revision: http://reviews.llvm.org/D20521

llvm-svn: 270441
2016-05-23 15:04:39 +00:00
Michael Zuckerman e6542002fc [Clang][AVX512][BUILTIN]adding missing intrinsics for movdaq instruction set
Differential Revision: http://reviews.llvm.org/D20514

llvm-svn: 270401
2016-05-23 08:01:48 +00:00
Simon Pilgrim 28666ce778 [X86][AVX] Ensure zero-extension of _mm256_extract_epi8 and _mm256_extract_epi16
Ensure _mm256_extract_epi8 and _mm256_extract_epi16 zero extend their i8/i16 result to i32. This matches _mm_extract_epi8 and _mm_extract_epi16.

Fix for PR27594

Differential Revision: http://reviews.llvm.org/D20468

llvm-svn: 270330
2016-05-21 21:14:35 +00:00