3 Commits

Author	SHA1	Message	Date
Kang Zhang	6d88b7d6e7	[PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0 ... Summary: If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen` will set it as true for those instructions which has no match pattern. The instructions `MTLR` and `MFLR` don't set the hasSideEffects flag and don't have match pattern, so their hasSideEffects flag will be set true by `llvm-tblgen`. But in fact, we can use `[LR]` to model the two instructions, so they should not have SideEffects. This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D71390	2019-12-26 02:12:32 +00:00
Jinsong Ji	216be996d6	[NFC][PowerPC] Consolidate testing of common linkage symbols ... Add a new file to test the code gen for common linkage symbol. Remove common linkage in some other testcases to avoid distraction. llvm-svn: 372426	2019-09-20 20:31:37 +00:00
Zi Xuan Wu	e18aa1e0a2	[NFC][Regalloc] Add testcases for D66576 ... llvm-svn: 369877	2019-08-26 05:06:30 +00:00