Commit Graph

61590 Commits

Author SHA1 Message Date
Roman Lebedev 1f63d7fef9 [NFC][ARM] addsubcarry-promotion.ll: whoops - replace '.' with '-' in check-prefix
Does not affect update_llc_test_checks, or the actual output,
but is not accepted by the actual FileCheck.

Sorry, i should have noticed this before committing,
not the very next second after..

llvm-svn: 361398
2019-05-22 15:42:33 +00:00
Roman Lebedev 1b45bdf5ba [NFC][ARM] Autogenerate addsubcarry-promotion.ll test
Being affected by upcoming patch

llvm-svn: 361397
2019-05-22 15:34:51 +00:00
Roman Lebedev 6a53135698 [NFC][X86] Autogenerate negative-offset.ll test
Being affected by upcoming patch

llvm-svn: 361396
2019-05-22 15:34:43 +00:00
Fangrui Song c289d218b9 [llvm-objdump] Dump inline relocations if the relocated section is specified with --section
This fixes PR41886: llvm-objdump -d -r -j .text doesn't show inline relocations of .text

While here, switch to stable_sort() because we don't want to change the order of relocations applied to the same location. gABI says consecutive relocation records are composed together and their order matters. In practise it is difficult to see relocations applied to the same location not consecutive, we just have to keep the relative order of relocations with the same offset.

Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D62253

llvm-svn: 361395
2019-05-22 15:12:51 +00:00
Roman Lebedev 406421b332 [NFC][X86][AArch64] Rewrite sink-addsub-of-const.ll tests to have full permutation coverage
Somehow missed some patterns initially..
While there, add comments.

llvm-svn: 361390
2019-05-22 14:42:41 +00:00
Dmitry Preobrazhensky 7773fc478d [AMDGPU][MC] Corrected parsing of op_sel* and neg_* modifiers
See bug 41361: https://bugs.llvm.org/show_bug.cgi?id=41361

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D61012

llvm-svn: 361386
2019-05-22 13:59:01 +00:00
James Henderson 5316a0d200 [llvm-objcopy] Tidy up error messages
This patch brings various error messages into line with each other, by
removing trailing full stops, and making the first letter lower-case.
This addresses https://bugs.llvm.org/show_bug.cgi?id=40859.

Reviewed by: jhenderson, rupprecht, jakehehrlich

Differential Revision: https://reviews.llvm.org/D62072

Patch by Alex Brachet

llvm-svn: 361384
2019-05-22 13:23:26 +00:00
Roman Lebedev 7c72ca012d UpdateTestChecks: sparc march handling
Summary:
Another target that prefers to use `-march` in tests
```
llvm/test/CodeGen/SPARC$ grep -ri mtriple | wc -l
25
llvm/test/CodeGen/SPARC$ grep -ri march | wc -l
165
```

This test is being affected by a further patch,
so regenerate it to better visualize the changes

Reviewers: RKSimon, dcederman, gberry

Reviewed By: RKSimon

Subscribers: jyknight, fedor.sergeev, jrtc27, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62242

llvm-svn: 361381
2019-05-22 13:04:34 +00:00
Roman Lebedev 4bf35671b5 [NFC][SystemZ] Autogenerate alloca-03.ll test to make test changes more visible
The check lines are being affected by an upcoming patch,
regenerate the checklines to visualize the changes better.

llvm-svn: 361380
2019-05-22 13:04:24 +00:00
Martin Storsjo de6038b265 [llvm-dlltool] Respect NONAME keyword
This adds proper handling of the NONAME-keyword, which makes llvm-dlltool
generate an import using the ordinal instead of the name.

Patch by by Jannik Vogel, test added by Stefan Schmidt.

Differential Revision: https://reviews.llvm.org/D62175

llvm-svn: 361367
2019-05-22 09:49:54 +00:00
Anton Afanasyev df00c6a54f [MIR] Add simple PRE pass to MachineCSE
This is the second part of the commit fixing PR38917 (hoisting
partitially redundant machine instruction). Most of PRE (partitial
redundancy elimination) and CSE work is done on LLVM IR, but some of
redundancy arises during DAG legalization. Machine CSE is not enough
to deal with it. This simple PRE implementation works a little bit
intricately: it passes before CSE, looking for partitial redundancy
and transforming it to fully redundancy, anticipating that the next
CSE step will eliminate this created redundancy. If CSE doesn't
eliminate this, than created instruction will remain dead and eliminated
later by Remove Dead Machine Instructions pass.

The third part of the commit is supposed to refactor MachineCSE,
to make it more clear and to merge MachinePRE with MachineCSE,
so one need no rely on further Remove Dead pass to clear instrs
not eliminated by CSE.

First step: https://reviews.llvm.org/D54839

Fixes llvm.org/PR38917

llvm-svn: 361356
2019-05-22 07:41:34 +00:00
Fangrui Song 1c61471ab1 [PPC64] Parse -elfv1 -elfv2 when specified on target triple
Summary:
For big-endian powerpc64, the default ABI is ELFv1. OpenPower ABI ELFv2 is supported when -mabi=elfv2 is specified. FreeBSD support for PowerPC64 ELFv2 ABI with LLVM is in progress[1]. This patch adds an alternative way to specify ELFv2 ABI on target triple [2].

The following results are expected:

ELFv1 when using:
-target powerpc64-unknown-freebsd12.0
-target powerpc64-unknown-freebsd12.0 -mabi=elfv1
-target powerpc64-unknown-freebsd12.0-elfv1

ELFv2 when using:
-target powerpc64-unknown-freebsd12.0 -mabi=elfv2
-target powerpc64-unknown-freebsd12.0-elfv2

[1] https://wiki.freebsd.org/powerpc/llvm-elfv2
[2] https://clang.llvm.org/docs/CrossCompilation.html

Patch by Alfredo Dal'Ava Júnior!

Differential Revision: https://reviews.llvm.org/D61950

llvm-svn: 361355
2019-05-22 07:29:59 +00:00
Nikita Popov 15df05152d [X86] Don't compare i128 through vector if construction not cheap (PR41971)
Fix for https://bugs.llvm.org/show_bug.cgi?id=41971. Make the
combineVectorSizedSetCCEquality() transform more conservative by
checking that the bitcast to the vector type will be cheap/free
for both operands. I'm considering it cheap if it's a constant,
a load or already a vector. I've dropped the explicit check for
f128 because it should fall out naturally (in the cases where
it'd be detrimental).

Differential Revision: https://reviews.llvm.org/D62220

llvm-svn: 361352
2019-05-22 06:47:06 +00:00
Seiya Nuta 3fcf1f5d29 [NFC] Remove a blank line (test commit)
llvm-svn: 361349
2019-05-22 04:48:26 +00:00
Chen Zheng 9970665f60 [PowerPC] [ISEL] select x-form instruction for unaligned offset
Differential Revision: https://reviews.llvm.org/D62173

llvm-svn: 361346
2019-05-22 02:57:31 +00:00
Pengfei Wang 6a0d432e9e [X86] [CET] Deal with return-twice function such as vfork, setjmp when
CET-IBT enabled

Return-twice functions will indirectly jump after the caller's position.
So when CET-IBT is enable, we should make sure these is endbr*
instructions follow these Return-twice function caller. Like GCC does.

Patch by Xiang Zhang (xiangzhangllvm)

Differential Revision: https://reviews.llvm.org/D61881

llvm-svn: 361342
2019-05-22 00:50:21 +00:00
Sanjay Patel 6a554188aa [InstCombine] fold shuffles of insert_subvectors
This should be a valid exception to the general rule of not creating new shuffle masks in IR...
because we already do it. :)
Also, DAG combining/legalization will undo this by widening the shuffle back out if needed.

Explanation for how we already do this: SLP or vector source can create chains of insert/extract
as shown in 1 of the examples from PR16739:
https://godbolt.org/z/NlK7rA
https://bugs.llvm.org/show_bug.cgi?id=16739

And we expect instcombine or DAGCombine to clean that up by creating relatively simple shuffles.

Differential Revision: https://reviews.llvm.org/D62024

llvm-svn: 361338
2019-05-22 00:32:25 +00:00
Matt Arsenault 2cba91b8db AMDGPU: Assume calls read exec
llvm-svn: 361333
2019-05-21 23:23:16 +00:00
Matt Arsenault eea81c20fe AMDGPU: Add some tests for inlineasm behavior
llvm-svn: 361332
2019-05-21 23:23:12 +00:00
Matt Arsenault dd1ffa00a5 AMDGPU: Assume call pseudos are convergent
There should probably be nonconvergent versions, but my guess is it
doesn't matter in practice.

llvm-svn: 361331
2019-05-21 23:23:10 +00:00
Matt Arsenault 60ba03e210 AMDGPU: Fix not marking new gfx10 SGPRs as CSRs
llvm-svn: 361330
2019-05-21 23:23:05 +00:00
Dan Gohman a49496fb2a [WebAssembly] Add the signature for the new llround builtin function
r360889 added new llround builtin functions. This patch adds their
signatures for the WebAssembly backend.

It also adds wasm32 support to utils/update_llc_test_checks.py, since
that's the script other targets are using for their testcases for this
feature.

Differential Revision: https://reviews.llvm.org/D62207

llvm-svn: 361327
2019-05-21 23:06:34 +00:00
Roman Lebedev 675307b1f1 [NFC][AMDGPU] Autogenerate llvm.amdgcn.s.barrier.ll test
llvm-svn: 361320
2019-05-21 21:49:14 +00:00
Roman Lebedev 21e8ec8d4f [NFC][X86] Autogenerate ragreedy-hoist-spill.ll test
llvm-svn: 361319
2019-05-21 21:49:10 +00:00
Roman Lebedev 079d8b425f [NFC][Thumb2] Autogenerate thumb2-ldr_pre.ll test
llvm-svn: 361318
2019-05-21 21:49:05 +00:00
Sanjay Patel 3590bae8d6 [InstCombine] add more tests for shuffle folding; NFC
As discussed in D62024, we want to limit any potential IR
transforms of shuffles to cases where we know the SDAG
conversion would result in equivalent patterns for these
IR variants.

llvm-svn: 361317
2019-05-21 21:45:24 +00:00
Nikita Popov d34d96770e [X86] Add large integer comparison tests for PR41971; NFC
In these cases we would prefer a direct comparison over going through
a vector type.

llvm-svn: 361315
2019-05-21 21:27:08 +00:00
Cameron McInally 17fdf1d383 [NFC][InstCombine] Add unary fneg tests to operand-complexity.ll.
llvm-svn: 361311
2019-05-21 21:07:46 +00:00
Cameron McInally 872dc79f20 [NFC][InstCombine] Add unary FNeg tests to X86/x86-avx512.ll
llvm-svn: 361308
2019-05-21 20:31:09 +00:00
Yi-Hong Lyu 00e85f7535 Move csr-save-restore-order.ll to the right place
llvm-svn: 361306
2019-05-21 20:28:31 +00:00
Roman Lebedev a7e88f8570 [NFC][X86][AArch64] Add tests for sinking of add/sub by constant through add/sub
Looks we can transform all 8 variants of the pattern:
https://rise4fun.com/Alive/auH

This comes up as an issue on the path towards
https://bugs.llvm.org/show_bug.cgi?id=41952

llvm-svn: 361303
2019-05-21 20:14:54 +00:00
Stanislav Mekhanoshin 44d17ca02e Fix register coalescer failure to prune value
Register coalescer fails for the test in the patch with the assertion in
JoinVals::ConflictResolution `DefMI != nullptr'. It attempts to join
live intervals for two adjacent instructions and erase the copy:

    %2:vreg_256 = COPY %1
    %3:vreg_256 = COPY killed %1

The LI needs to be adjusted to kill subrange for the erased instruction
and extend the subrange of the original def. That was done for the main
interval only but not for the subrange. As a result subrange had a VNI
pointing to the erased slot resulting in the above failure.

Differential Revision: https://reviews.llvm.org/D62162

llvm-svn: 361293
2019-05-21 19:32:41 +00:00
Leonard Chan 0bada7ce6c [Intrinsic] Signed Fixed Point Saturation Multiplication Intrinsic
Add an intrinsic that takes 2 signed integers with the scale of them provided
as the third argument and performs fixed point multiplication on them. The
result is saturated and clamped between the largest and smallest representable
values of the first 2 operands.

This is a part of implementing fixed point arithmetic in clang where some of
the more complex operations will be implemented as intrinsics.

Differential Revision: https://reviews.llvm.org/D55720

llvm-svn: 361289
2019-05-21 19:17:19 +00:00
Simon Pilgrim 4b82e50315 [X86][SSE] computeKnownBitsForTargetNode - add X86ISD::ANDNP support
Fixes PACKSS-PSHUFB shuffle regressions mentioned on D61692

llvm-svn: 361270
2019-05-21 15:20:24 +00:00
Paul Robinson 35a2196bd1 Fix typo in r361251.
llvm-svn: 361256
2019-05-21 13:23:32 +00:00
Roman Lebedev d8db224ecb [NFC][X86][AArch64] Shift amount masking: tests that show that 'neg' doesn't last
Meaning if we were to produce 'neg' in dagcombine, we will get an
endless cycle; some inverse transform would need to be guarded somehow.

Also, the 'and (sub 0, x), 31' variant is sticky,
doesn't get optimized in any way.

https://bugs.llvm.org/show_bug.cgi?id=41952

llvm-svn: 361254
2019-05-21 13:04:56 +00:00
Paul Robinson 0a16ba856b [DebugInfo] Fix tests missed by r362148
llvm-svn: 361251
2019-05-21 12:48:46 +00:00
Paul Robinson 9d5351cab6 De-Window-ize a test
llvm-svn: 361250
2019-05-21 12:08:42 +00:00
Paul Robinson 9c56326934 [DebugInfo] Handle '# line "file"' correctly for asm source.
This provides the correct file path for the original source, rather
than the preprocessed source.

Part of the fix for PR41839.

Differential Revision: https://reviews.llvm.org/D62074

llvm-svn: 361248
2019-05-21 11:59:03 +00:00
Bob Haarman 032f87bbb3 Revert r360902 "Resubmit: [Salvage] Change salvage debug info ..."
This reverts commit rr360902. It caused an assertion failure in
lib/IR/DebugInfoMetadata.cpp: Assertion `(OffsetInBits + SizeInBits <=
FragmentSizeInBits) && "new fragment outside of original fragment"'
failed.

PR41931.

llvm-svn: 361246
2019-05-21 11:53:41 +00:00
Paul Robinson 116e8d4876 [DebugInfo] Handle -main-file-name correctly for asm source.
This option provides only the base filename, not a full relative path.

Part of the fix for PR41839.

Differential Revision: https://reviews.llvm.org/D62071

llvm-svn: 361245
2019-05-21 11:52:27 +00:00
Simon Pilgrim bc03bee66b [X86][SSE] Add shuffle tests for 'splat3' patterns.
Test codegen from shuffles for { dst[0] = dst[1] = dst[2] = *src++; dst += 3 } 'splatting' memcpy patterns generated by loop-vectorizer.

llvm-svn: 361243
2019-05-21 11:42:28 +00:00
Roman Lebedev 2aee73f591 [NFC][X86][AArch64] Add some more tests for shift amount masking
The negation creation should be more eager:
https://bugs.llvm.org/show_bug.cgi?id=41952

llvm-svn: 361241
2019-05-21 11:14:01 +00:00
George Rimar f44eb922c0 [llvm-objdump] Make --disassemble-functions imply -d
Fixes https://bugs.llvm.org/show_bug.cgi?id=41903

Patch by Mike Pozulp!

Differential revision: https://reviews.llvm.org/D62054

llvm-svn: 361240
2019-05-21 11:05:46 +00:00
Clement Courbet a95d95d392 [MergeICmps] Preserve the dominator tree.
Summary: In preparation for D60318 .

Reviewers: gchatelet, efriedma

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62068

llvm-svn: 361239
2019-05-21 11:02:23 +00:00
Fangrui Song cd36a2857e [PPC64] Update LocalEntry from assigned symbols
On PowerPC64 ELFv2 ABI, functions may have 2 entry points: global and local.
The local entry point location of a function is stored in the st_other field of the symbol, as an offset relative to the global entry point.

In order to make symbol assignments (e.g. .equ/.set) work properly with this, PPCTargetELFStreamer already copies the local entry bits from the source symbol to the destination one, on emitAssignment(). The problem is that this copy is performed only at the assignment location, where the source symbol may not yet have processed the .localentry directive, that sets the local entry. This may cause the destination symbol to end up with wrong local entry information. Other symbol info is not affected by this because, in this case, the destination symbol value is actually a symbol reference.

This change keeps track of these assignments, and update all needed st_other fields when finish() is called.

Patch by Leandro Lupori!

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D56586

llvm-svn: 361237
2019-05-21 10:41:25 +00:00
Florian Hahn 4a8835c655 [AArch64] Skip mask checks for masks with an odd number of elements.
Some checks in isShuffleMaskLegal expect an even number of elements,
e.g. isTRN_v_undef_Mask or isUZP_v_undef_Mask, otherwise they access
invalid elements and crash. This patch adds checks to the impacted
functions.

Fixes PR41951

Reviewers: t.p.northover, dmgreen, samparker

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D60690

llvm-svn: 361235
2019-05-21 10:05:26 +00:00
Eugene Leviant ec767b0b4a [llvm-objcopy] Strip file symbols with --strip-unneeded
Differential revision: https://reviews.llvm.org/D61641

llvm-svn: 361231
2019-05-21 09:09:33 +00:00
Cullen Rhodes 7f47b75d18 [AArch64][SVE2] Asm: add integer unary instructions (predicated)
Summary:
Patch adds support for the following instructions:

    * URECPE, URSQRTE, SQABS, SQNEG

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D62129

llvm-svn: 361230
2019-05-21 09:06:51 +00:00
Cullen Rhodes e798e8d9d2 [AArch64][SVE2] Asm: add integer pairwise arithmetic instructions
Summary:
Patch adds support for the following instructions:

    ADDP, SMAXP, UMAXP, SMINP, UMINP

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D62128

llvm-svn: 361229
2019-05-21 08:59:00 +00:00