llvm-project

Commit Graph

Author	SHA1	Message	Date
Francis Visoiu Mistrih	c71cced0aa	[CodeGen] Always use `printReg` to print registers in both MIR and debug output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445	2017-11-30 16:12:24 +00:00
Pete Cooper	46361a1ea1	Change x86 CMOVE_F to read it source, not write it. This was breaking sqlite with the machine verifier because operand 0 was a def according to tablegen, but didn't have the 'isDef' flag set. Looking at the ISA, its clear that this operand is a source as writing to st(0) is implicit. So move the operand to the correct place in the td file. rdar://problem/20751584 llvm-svn: 236183	2015-04-29 23:51:33 +00:00

Author

SHA1

Message

Date

Francis Visoiu Mistrih

c71cced0aa

[CodeGen] Always use `printReg` to print registers in both MIR and debug

output

As part of the unification of the debug format and the MIR format,
always use `printReg` to print all kinds of registers.

Updated the tests using '_' instead of '%noreg' until we decide which
one we want to be the default one.

Differential Revision: https://reviews.llvm.org/D40421

llvm-svn: 319445

2017-11-30 16:12:24 +00:00

Pete Cooper

46361a1ea1

Change x86 CMOVE_F to read it source, not write it.

This was breaking sqlite with the machine verifier because operand 0 was a def according to tablegen, but didn't have the 'isDef' flag set.

Looking at the ISA, its clear that this operand is a source as writing to st(0) is implicit.  So move the operand to the correct place in the td file.

rdar://problem/20751584

llvm-svn: 236183

2015-04-29 23:51:33 +00:00

2 Commits