3eb7691858
Thumb2 RSBS instructions were being printed without the 'S' suffix.
...
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
llvm-svn: 104531
2010-05-24 18:44:06 +00:00
91fdf68516
Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
...
copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.
llvm-svn: 104415
2010-05-22 00:23:12 +00:00
daeca2d156
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
...
llvm-svn: 104115
2010-05-19 07:28:01 +00:00
2a41cad900
Clean up the conditional for handling of sign_extend_inreg based on
...
whether the extract instructions are available.
rdar://7956878
llvm-svn: 103277
2010-05-07 18:34:55 +00:00
151cd8f159
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
...
instructions to subtarget features and update tests to reflect.
PR5717.
llvm-svn: 103136
2010-05-05 23:44:43 +00:00
245b169212
fix copy/paste oops.
...
llvm-svn: 103122
2010-05-05 21:07:46 +00:00
44d7f49887
Add tests for ARMV7M divide instruction use
...
llvm-svn: 103120
2010-05-05 20:47:15 +00:00
2ad68de4aa
Fix a bug which prevented tail merging of return instructions in
...
beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and
test/CodeGen/ARM/ifcvt2.ll for details.
The fix is to change HashEndOfMBB to hash at most one instruction,
instead of trying to apply heuristics about when it will be profitable to
consider more than one instruction. The regular tail-merging heuristics
are already prepared to handle the same cases, and they're more precise.
Also, make test/CodeGen/ARM/ifcvt5.ll and
test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they
continue to test what they're intended to test.
And, this eliminates the problem in
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from
PR5204. Update it accordingly.
llvm-svn: 102907
2010-05-03 14:35:47 +00:00
25f85947a3
Handle register-to-register copies within the tGPR class.
...
Radar 7896289
llvm-svn: 102396
2010-04-26 23:20:08 +00:00
825cb299cd
Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield
...
extraction. This fixes PR5998.
llvm-svn: 102144
2010-04-22 23:24:18 +00:00
2034d9f2da
- Clean up some crappy code which deals with coalescing of copies which look at
...
extract_subreg / insert_subreg, etc.
- Add support for more aggressive insert_subreg coalescing.
llvm-svn: 101971
2010-04-21 00:44:22 +00:00
4fee6f3bdd
Start function numbering at 0.
...
llvm-svn: 101638
2010-04-17 16:29:15 +00:00
f7f97b4bbd
Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.
...
llvm-svn: 101410
2010-04-15 22:20:34 +00:00
1ba1428577
ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908
...
llvm is generating poor code for dynamic alloca, I'll fix that later.
llvm-svn: 101383
2010-04-15 18:42:28 +00:00
71fcb4fedd
switch the flag for using NEON for SP floating point to a subtarget 'feature'.
...
Re-commit. This time complete with testsuite updates.
llvm-svn: 99570
2010-03-25 23:47:34 +00:00
8f3004cff2
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
...
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28 ]
llvm-svn: 98745
2010-03-17 17:52:21 +00:00
1b4e8cc69c
--- Reverse-merging r98637 into '.':
...
U test/CodeGen/ARM/tls2.ll
U test/CodeGen/ARM/arm-negative-stride.ll
U test/CodeGen/ARM/2009-10-30.ll
U test/CodeGen/ARM/globals.ll
U test/CodeGen/ARM/str_pre-2.ll
U test/CodeGen/ARM/ldrd.ll
U test/CodeGen/ARM/2009-10-27-double-align.ll
U test/CodeGen/Thumb2/thumb2-strb.ll
U test/CodeGen/Thumb2/ldr-str-imm12.ll
U test/CodeGen/Thumb2/thumb2-strh.ll
U test/CodeGen/Thumb2/thumb2-ldr.ll
U test/CodeGen/Thumb2/thumb2-str_pre.ll
U test/CodeGen/Thumb2/thumb2-str.ll
U test/CodeGen/Thumb2/thumb2-ldrh.ll
U utils/TableGen/TableGen.cpp
U utils/TableGen/DisassemblerEmitter.cpp
D utils/TableGen/RISCDisassemblerEmitter.h
D utils/TableGen/RISCDisassemblerEmitter.cpp
U Makefile.rules
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/Makefile
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D lib/Target/ARM/Disassembler
U lib/Target/ARM/ARMInstrFormats.td
U lib/Target/ARM/ARMAddressingModes.h
U lib/Target/ARM/Thumb2ITBlockPass.cpp
llvm-svn: 98640
2010-03-16 16:59:47 +00:00
3d9327bd06
Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend
...
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.
Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.
We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60.
And modified test cases to not expect '+' in +reg or #+num. For example,
; CHECK: ldr.w r9, [r7, #28 ]
llvm-svn: 98637
2010-03-16 16:36:54 +00:00
298a83ecfe
Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.
...
This does not move entirely to UAL syntax, since the default "increment after"
suffix is empty but we still use "IA" for that.
llvm-svn: 98635
2010-03-16 16:19:07 +00:00
5125770346
Add a testcase for the change in r98586.
...
llvm-svn: 98610
2010-03-16 05:33:29 +00:00
80ad113731
Enable machine cse pass.
...
llvm-svn: 98132
2010-03-10 03:07:41 +00:00
0bfbd9b68c
Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit
...
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand. We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.
llvm-svn: 98001
2010-03-08 22:56:15 +00:00
ece1797542
Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version
...
of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".
llvm-svn: 97760
2010-03-04 22:24:41 +00:00
63af51c1c8
Create a stack frame on ARM when
...
- Function uses all scratch registers AND
- Function does not use any callee saved registers AND
- Stack size is too big to address with immediate offsets.
In this case a register must be scavenged to calculate the address of a stack
object, and the scavenger needs a spare register or emergency spill slot.
llvm-svn: 97071
2010-02-24 22:43:17 +00:00
6ad4bcb0da
LowerCall() should always do getCopyFromReg() to reference the stack pointer.
...
Machine instruction selection is much happier when operands are in virtual
registers.
llvm-svn: 97012
2010-02-24 01:43:03 +00:00
9be7200b08
Last week we were generating code with duplicate induction variables in this
...
test, but the problem seems to have gone away today. Add a check to make sure
it doesn't come back.
llvm-svn: 96277
2010-02-15 21:56:40 +00:00
01abf8fc2f
Besides removing phi cycles that reduce to a single value, also remove dead
...
phi cycles. Adjust a few tests to keep dead instructions from being optimized
away. This (together with my previous change for phi cycles) fixes Apple
radar 7627077.
llvm-svn: 96057
2010-02-13 00:31:44 +00:00
45774ce0ad
Reapply the new LoopStrengthReduction code, with compile time and
...
bug fixes, and with improved heuristics for analyzing foreign-loop
addrecs.
This change also flattens IVUsers, eliminating the stride-oriented
groupings, which makes it easier to work with.
llvm-svn: 95975
2010-02-12 10:34:29 +00:00
0827e040e0
Add a new pass on machine instructions to optimize away PHI cycles that
...
reduce down to a single value. InstCombine already does this transformation
but DAG legalization may introduce new opportunities. This has turned out to
be important for ARM where 64-bit values are split up during type legalization:
InstCombine is not able to remove the PHI cycles on the 64-bit values but
the separate 32-bit values can be optimized. I measured the compile time
impact of this (running llc on 176.gcc) and it was not significant.
llvm-svn: 95951
2010-02-12 01:30:21 +00:00
93c92225af
Reapply coalescer fix for better cross-class coalescing.
...
This time with fixed test cases.
llvm-svn: 95938
2010-02-11 23:55:29 +00:00
5638c36efd
Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex.
...
Radar 7614112.
llvm-svn: 95456
2010-02-06 00:24:38 +00:00
045f81981a
Revert LoopStrengthReduce.cpp to pre-r94061 for now.
...
llvm-svn: 94123
2010-01-22 00:46:49 +00:00
51ad99d2c5
Re-implement the main strength-reduction portion of LoopStrengthReduction.
...
This new version is much more aggressive about doing "full" reduction in
cases where it reduces register pressure, and also more aggressive about
rewriting induction variables to count down (or up) to zero when doing so
reduces register pressure.
It currently uses fairly simplistic algorithms for finding reuse
opportunities, but it introduces a new framework allows it to combine
multiple strategies at once to form hybrid solutions, instead of doing
all full-reduction or all base+index.
llvm-svn: 94061
2010-01-21 02:09:26 +00:00
bdc17f6840
Remove predicates when changing an add into an unpredicable mov.
...
Since the mov is executed unconditionally, make sure that the add didn't have
any predicate.
llvm-svn: 93909
2010-01-19 21:08:28 +00:00
298cdac99c
Run the pre-register allocation tail duplication pass by default. Remove
...
the -pre-regalloc-taildup command-line option, and add a new
-disable-early-taildup option.
llvm-svn: 93597
2010-01-16 00:29:50 +00:00
f1522d612f
Add comments.
...
llvm-svn: 92883
2010-01-07 00:51:04 +00:00
29a64c9575
Add Target hook to duplicate machine instructions.
...
Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.
llvm-svn: 92873
2010-01-06 23:47:07 +00:00
fb4193625a
Delete useless trailing semicolons.
...
llvm-svn: 92740
2010-01-05 17:55:26 +00:00
23fbd54cfe
Make this test pass on Linux.
...
llvm-svn: 91521
2009-12-16 07:35:25 +00:00
75dfed4fa5
Dynamic stack realignment use of sp register as source/dest register
...
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4
llvm-svn: 90724
2009-12-06 22:39:50 +00:00
8a8ba87ac8
test case for IV-Users simplification loop improvement
...
llvm-svn: 90260
2009-12-01 21:53:51 +00:00
184ec26fcd
Enable predication of NEON instructions in Thumb2 mode.
...
llvm-svn: 89748
2009-11-24 08:06:15 +00:00
dbb4140f37
move fconst[sd] to UAL. <rdar://7414913>
...
llvm-svn: 89700
2009-11-23 21:08:25 +00:00
50b293d65e
update test for 89694
...
llvm-svn: 89695
2009-11-23 20:39:53 +00:00
f161e97a9e
Miss two, PR5307.
...
llvm-svn: 89596
2009-11-22 15:35:28 +00:00
cc856372b0
Convert Thumb2 tests to FileCheck for PR5307.
...
llvm-svn: 89595
2009-11-22 15:18:27 +00:00
e09e95b35c
Revert 89562. We're being sneakier than I was giving us credit for, and this
...
isn't necessary.
llvm-svn: 89568
2009-11-21 23:34:09 +00:00
43fd822249
Darwin requires a frame pointer for all non-leaf functions to support correct
...
backtraces.
llvm-svn: 89562
2009-11-21 21:40:08 +00:00
73f9a9e2c8
Enable hoisting load from constant memories.
...
llvm-svn: 89510
2009-11-20 23:31:34 +00:00
bdb43a9d99
Remat VLDRD from constpool. Clean up some instruction property specifications.
...
llvm-svn: 89478
2009-11-20 19:57:15 +00:00
bbd50b0f78
Also CSE non-pic load from constant pools.
...
llvm-svn: 89440
2009-11-20 02:10:27 +00:00
b18525937c
More consistent thumb1 asm printing.
...
llvm-svn: 89328
2009-11-19 06:57:41 +00:00
2a6c92fcb6
Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.
...
llvm-svn: 89326
2009-11-19 06:32:27 +00:00
cdde77c6a3
Enable arm jumpt table adjustment.
...
llvm-svn: 89143
2009-11-17 21:24:11 +00:00
a2873f4d59
Forgot to commit test fixes
...
llvm-svn: 89138
2009-11-17 20:38:36 +00:00
0ad7efbace
Convert to FileCheck
...
llvm-svn: 89007
2009-11-17 00:20:26 +00:00
4781c3caf8
Convert to FileCheck
...
llvm-svn: 89002
2009-11-17 00:03:38 +00:00
805d195649
Cleanup. Missed removing these when converting. Oops.
...
llvm-svn: 89001
2009-11-17 00:00:33 +00:00
1deb0b9f53
Convert to FileCheck
...
llvm-svn: 88991
2009-11-16 23:19:29 +00:00
9b32e22ad1
Convert to FileCheck
...
llvm-svn: 88947
2009-11-16 20:04:15 +00:00
980d94164d
Convert to FileCheck
...
llvm-svn: 88942
2009-11-16 19:46:46 +00:00
c670bdc311
tbb opt off by default
...
llvm-svn: 88921
2009-11-16 17:24:45 +00:00
01c1cae34d
Detect need for autoalignment of the stack earlier to catch spills more
...
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling
llvm-svn: 88874
2009-11-15 21:45:34 +00:00
f16a3b7a9f
remove xfail
...
llvm-svn: 88817
2009-11-14 21:57:35 +00:00
66401c90da
When expanding t2STRDi8 r, r to two stores, add kill markers correctly.
...
llvm-svn: 88734
2009-11-14 01:50:00 +00:00
1025a4998b
Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input.
...
llvm-svn: 86997
2009-11-12 17:19:09 +00:00
5218176bc6
Fix typo in run line.
...
llvm-svn: 86984
2009-11-12 12:35:27 +00:00
5d85a46f76
RegScavenger::enterBasicBlock should always reset register state.
...
llvm-svn: 86972
2009-11-12 07:49:10 +00:00
85a9f430e9
- Teach LSR to avoid changing cmp iv stride if it will create an immediate that
...
cannot be folded into target cmp instruction.
- Avoid a phase ordering issue where early cmp optimization would prevent the
later count-to-zero optimization.
- Add missing checks which could cause LSR to reuse stride that does not have
users.
- Fix a bug in count-to-zero optimization code which failed to find the pre-inc
iv's phi node.
- Remove, tighten, loosen some incorrect checks disable valid transformations.
- Quite a bit of code clean up.
llvm-svn: 86969
2009-11-12 07:35:05 +00:00
64b5d0f468
Add support for tail duplication to BranchFolding, and extend
...
tail merging support to handle more cases.
- Recognize several cases where tail merging is beneficial even when
the tail size is smaller than the generic threshold.
- Make use of MachineInstrDesc::isBarrier to help detect
non-fallthrough blocks.
- Check for and avoid disrupting fall-through edges in more cases.
llvm-svn: 86871
2009-11-11 19:48:59 +00:00
47e3bcf180
Update test
...
llvm-svn: 86614
2009-11-09 22:59:01 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
...
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
a8e8a7c976
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
...
llvm-svn: 86330
2009-11-07 04:04:34 +00:00
7ff831962a
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
...
except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
llvm-svn: 86328
2009-11-07 03:52:02 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
...
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
db42ca663b
Fix a broken test.
...
llvm-svn: 86298
2009-11-06 23:06:42 +00:00
8f4e3d99c9
Fix test.
...
llvm-svn: 85986
2009-11-04 00:42:33 +00:00
8d681f0471
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
...
llvm-svn: 85871
2009-11-03 05:52:54 +00:00
2c2dc9f64f
Temporary xfail until PR5367 will be resolved
...
llvm-svn: 85848
2009-11-03 00:37:36 +00:00
1708b06c0e
Unbreak ARMBaseRegisterInfo::copyRegToReg.
...
llvm-svn: 85787
2009-11-02 04:44:55 +00:00
43219997b6
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
...
llvm-svn: 85743
2009-11-01 21:12:51 +00:00
50bc004b67
Fix tests.
...
llvm-svn: 85723
2009-11-01 18:13:29 +00:00
6f29ad9170
Use cbz and cbnz instructions.
...
llvm-svn: 85698
2009-10-31 23:46:45 +00:00
5cba8de2c8
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
...
them for scalar floating point operations for now.
llvm-svn: 85697
2009-10-31 22:57:36 +00:00
403202aef1
Consolidate test files
...
llvm-svn: 85696
2009-10-31 22:20:56 +00:00
c79fb530d4
Change to use FileCheck
...
llvm-svn: 85695
2009-10-31 22:16:14 +00:00
69f364babc
Make tests more explicit about which instructions are expected.
...
llvm-svn: 85694
2009-10-31 22:14:17 +00:00
259c37cc55
Grammar tweak to comments
...
llvm-svn: 85693
2009-10-31 22:12:44 +00:00
2c3e618a06
Update test to be more explicit about what instruction sequences are expected for each operation.
...
llvm-svn: 85691
2009-10-31 22:10:38 +00:00
6ef6fe1c31
Force triple; darwin's ASM syntax differs from linux's.
...
llvm-svn: 85676
2009-10-31 19:54:06 +00:00
7e06083a3a
Add missing colons for FileCheck.
...
llvm-svn: 85674
2009-10-31 19:22:24 +00:00
cdbb70c065
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
...
llvm-svn: 85643
2009-10-31 03:39:36 +00:00
3d43b38f0f
Fix Thumb2 failures by converting them to FileCheck.
...
llvm-svn: 85210
2009-10-27 06:31:02 +00:00
69140ec4fa
Add a couple of ARM cross-rc coalescing tests.
...
llvm-svn: 85051
2009-10-25 08:01:41 +00:00
b9f3520660
Update tests.
...
llvm-svn: 85050
2009-10-25 07:53:48 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
...
immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
786b15fe12
Match more patterns to movt.
...
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
682a2d154a
Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail.
...
llvm-svn: 84727
2009-10-21 01:44:44 +00:00
baf6dd26ea
Checkpoint more aggressive anti-dependency breaking for post-ra scheduler.
...
llvm-svn: 84658
2009-10-20 19:54:44 +00:00
3f23601b00
Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng.
...
llvm-svn: 84212
2009-10-15 22:25:32 +00:00
4ad726b4be
Fix tests.
...
llvm-svn: 83241
2009-10-02 06:53:57 +00:00
1cc6dd97da
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
...
llvm-svn: 83218
2009-10-01 22:19:57 +00:00
3ea1ba7739
Forgot this test earlier.
...
llvm-svn: 83143
2009-09-30 08:41:27 +00:00
83e0d481ae
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
...
instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
llvm-svn: 82982
2009-09-28 09:14:39 +00:00
a6b9cab822
Enable pre-regalloc load / store multiple pass for Thumb2.
...
llvm-svn: 82893
2009-09-27 09:46:04 +00:00
ccde96e96b
"Update" tests for -disable-if-conversion removal. I think branch.ll should just
...
be removed, but I XFAIL'd it for now.
llvm-svn: 82847
2009-09-26 05:29:36 +00:00
a080159a7c
Convert more tests to avoid llvm-as.
...
llvm-svn: 81545
2009-09-11 18:36:27 +00:00
cf61d68eaf
Cast MO.getImm() to unsigned before comparing with an unsigned limit.
...
llvm-svn: 81318
2009-09-09 06:05:16 +00:00
c8054d90fb
Eliminate more uses of llvm-as and llvm-dis.
...
llvm-svn: 81293
2009-09-09 00:09:15 +00:00
f87421f088
update various tests for signedness changes in .s file.
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llvm-svn: 81289
2009-09-08 23:51:06 +00:00
9ef94277f1
adjust for signedness change. I'd appreciate it if an ARM flavored person
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could look at this: the top undefined bits of an immediate shouldn't affect
isel (cmp vs cmp.w)
llvm-svn: 81288
2009-09-08 23:44:53 +00:00
6837964819
merge thumb2-bic2.ll into thumb2-bic.ll and update for signedness changes.
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llvm-svn: 81285
2009-09-08 23:41:06 +00:00
3d2fce01aa
Run branch folding if if-converter make some transformations.
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llvm-svn: 80994
2009-09-04 07:47:40 +00:00
4f835f1d7d
Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed.
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llvm-svn: 80615
2009-08-31 20:14:07 +00:00
43b9ca6f42
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
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llvm-svn: 80404
2009-08-28 23:18:09 +00:00
7a37b1a2ca
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
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llvm-svn: 80191
2009-08-27 01:23:50 +00:00
9054d25808
Fix a typo. Somehow I thought this had passed before, but I guess not.
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llvm-svn: 79937
2009-08-24 21:17:17 +00:00
5fe1d38607
Convert slow test to use FileCheck.
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llvm-svn: 79935
2009-08-24 20:33:47 +00:00
a41fa35992
Make tail merging handle blocks with repeated predecessors correctly, and
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remove RemoveDuplicateSuccessor, as it is no longer necessary, and because
it breaks assumptions made in
MachineBasicBlock::isOnlyReachableByFallthrough.
Convert test/CodeGen/X86/omit-label.ll to FileCheck and add a testcase
for PR4732.
test/CodeGen/Thumb2/thumb2-ifcvt2.ll sees a diff with this commit due to
it being bugpoint-reduced to the point where it doesn't matter what the
condition for the branch is.
Add some more interesting code to
test/CodeGen/X86/2009-08-06-branchfolder-crash.ll, which is the testcase
that originally motivated the RemoveDuplicateSuccessor code, to help
verify that the original problem isn't being re-broken.
llvm-svn: 79338
2009-08-18 15:18:18 +00:00
dd406177de
Fix revsh pattern.
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llvm-svn: 79318
2009-08-18 05:43:23 +00:00
d7e1a79eea
Fix tests.
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llvm-svn: 79086
2009-08-15 08:23:11 +00:00
6ddd7bcdd1
Turn on if-conversion for thumb2.
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llvm-svn: 79084
2009-08-15 07:59:10 +00:00
7dae88d2c9
Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim.
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llvm-svn: 79039
2009-08-14 20:48:13 +00:00
e41903b10d
Also shrink immediate branches; also more assembler workarounds.
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llvm-svn: 79014
2009-08-14 18:31:44 +00:00
db73d68cbe
Shrink ADR and LDR from constantpool late during constantpool island pass.
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llvm-svn: 78970
2009-08-14 00:32:16 +00:00
608d92c943
Remove an Darwin assembler workaround.
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llvm-svn: 78777
2009-08-12 01:56:42 +00:00
1e6c2a1c17
Shrink ADDS, ADC, RSB, and SUBS.
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llvm-svn: 78776
2009-08-12 01:49:45 +00:00
f6a9d06241
Shrinkify Thumb2 r = add sp, imm.
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llvm-svn: 78745
2009-08-11 23:00:31 +00:00
cc9ca3500d
Shrinkify Thumb2 load / store multiple instructions.
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llvm-svn: 78717
2009-08-11 21:11:32 +00:00
806845daec
Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
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llvm-svn: 78659
2009-08-11 09:37:40 +00:00
475f8a4fa2
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
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llvm-svn: 78622
2009-08-10 23:56:04 +00:00
f72c13bdf5
Handle the constantfp created during post-legalization dag combiner phase.
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llvm-svn: 78594
2009-08-10 20:25:59 +00:00
ac51533b8a
Simplify RegScavenger::forward a bit more.
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Verify that early clobber registers and their aliases are not used.
All changes to RegsAvailable are now done as a transaction so the order of
operands makes no difference.
The included test case is from PR4686. It has behaviour that was dependent on the order of operands.
llvm-svn: 78465
2009-08-08 13:18:47 +00:00
6e130db3b7
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
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llvm-svn: 78410
2009-08-07 21:19:10 +00:00
4c3b1ca5a0
Fix support to use NEON for single precision fp math.
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llvm-svn: 78397
2009-08-07 19:30:41 +00:00
b1aeeed03e
Another coalescer bug. When a dead copy is eliminated, transfer the kill to a def of the exact register rather than a super-register.
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llvm-svn: 78376
2009-08-07 07:14:14 +00:00
b972e5633f
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
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This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
ea2b82b8fc
Disable stack coloring with register for now. It's not able to set kill markers.
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llvm-svn: 78179
2009-08-05 07:26:17 +00:00
a2ce665f60
Another nasty coalescer bug (is there another kind):
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After coalescing reg1027's def and kill are both at the same point:
%reg1027,0.000000e+00 = [56,814:0) 0@70-(814)
bb5:
60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>
Do not remove the kill marker on t2LDRi12.
llvm-svn: 78178
2009-08-05 07:05:41 +00:00
1f7b549c79
One more. Transfer kill of the larger register when lowering an EXTRACT_SUBREG.
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llvm-svn: 78145
2009-08-05 02:25:11 +00:00
6376367356
One more place where subreg lowering forgot to transfer undefness.
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llvm-svn: 78144
2009-08-05 01:57:22 +00:00
cdb125ce66
If the insert_subreg source is <undef>, insert an implicit_def instead of a copy.
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llvm-svn: 78141
2009-08-05 01:29:24 +00:00
7cc6aca1e6
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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llvm-svn: 78126
2009-08-04 23:47:55 +00:00
28c2d9809d
Fix test.
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llvm-svn: 78113
2009-08-04 22:22:58 +00:00
783b65b546
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
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llvm-svn: 78104
2009-08-04 21:12:13 +00:00
a3abe2a7ce
In thumb mode, r7 is used as frame register. This fixes pr4681.
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llvm-svn: 78086
2009-08-04 18:46:17 +00:00
03eb0e3c33
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
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llvm-svn: 78030
2009-08-04 01:41:15 +00:00
093e124256
Fix a coaelescer bug. If a copy val# is extended to eliminate a non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy.
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llvm-svn: 77967
2009-08-03 08:41:59 +00:00
8b9deebba3
Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.
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llvm-svn: 77939
2009-08-03 02:38:06 +00:00
8e3889f12e
Test both darwin and linux.
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llvm-svn: 77852
2009-08-02 02:54:34 +00:00
f165160724
Hack to make this test work on platforms which aren't Macs. Fixing this
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myself because I'm getting tired of seeing the red buildbots, which have
been red since 5:30PM PDT last night.
Proposed supplement to developer policy: committers should make sure to
be around to watch for buildbot failures after committing.
llvm-svn: 77785
2009-08-01 16:37:18 +00:00
e64f48ba8b
Workaround a couple of Darwin assembler bugs.
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llvm-svn: 77781
2009-08-01 06:13:52 +00:00
e6e8289d72
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
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llvm-svn: 77764
2009-08-01 01:43:45 +00:00
6ab54fdb0a
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
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instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
llvm-svn: 77756
2009-08-01 00:16:10 +00:00
be8422e8e0
Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align
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to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.
llvm-svn: 77705
2009-07-31 18:35:56 +00:00
5811ab5cf3
When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.
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llvm-svn: 77642
2009-07-30 23:29:25 +00:00
0bfc8312c2
Darwin assembler now recognizes "orn", so remove workaround.
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llvm-svn: 77627
2009-07-30 21:51:41 +00:00
ce774e2383
Darwin assembler now supports "rrx", so remove workaround.
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llvm-svn: 77625
2009-07-30 21:38:40 +00:00
79c079b478
Cleanup and include code selection for some frame index cases.
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llvm-svn: 77622
2009-07-30 18:56:48 +00:00
e3493a91cc
tbb / tbh instructions only branch forward, not backwards.
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llvm-svn: 77522
2009-07-29 23:20:20 +00:00
c6d70ae063
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
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llvm-svn: 77422
2009-07-29 02:18:14 +00:00
c8bed03349
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
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llvm-svn: 77364
2009-07-28 20:53:24 +00:00
68bb69d6e3
Remove support for ORN to workaround <rdar://problem/7096522>.
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llvm-svn: 77363
2009-07-28 20:51:25 +00:00
865c6298d7
Add workaround for <rdar://problem/7098328>.
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llvm-svn: 77340
2009-07-28 18:15:38 +00:00
e82862e24e
Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
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llvm-svn: 77329
2009-07-28 17:06:49 +00:00
780748d565
- More refactoring. This gets rid of all of the getOpcode calls.
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- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
57b51d9f82
ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM.
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llvm-svn: 77275
2009-07-27 23:34:12 +00:00
782f242fd7
Add ".w" suffix for wide thumb-2 instructions.
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llvm-svn: 77199
2009-07-27 16:31:55 +00:00
f3a1fce8ae
Change Thumb2 jumptable codegen to one that uses two level jumps:
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Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2 ]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
llvm-svn: 77024
2009-07-25 00:33:29 +00:00
8c8e88bd39
Remove a duplicated test.
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llvm-svn: 77020
2009-07-25 00:24:40 +00:00
aee0e1f48c
Fix these tests.
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llvm-svn: 77006
2009-07-24 22:42:22 +00:00
3990850a7d
Convert a test to FileCheck.
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llvm-svn: 76954
2009-07-24 06:01:46 +00:00
dc99f07113
Thumb2 does not allow the use of "pc" register as part of the load / store address.
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llvm-svn: 76909
2009-07-23 23:09:51 +00:00
d2919a1773
Fix up ARM constant island pass for Thumb2.
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Also fixed up code to fully use the SoImm field for ADR on ARM mode.
llvm-svn: 76890
2009-07-23 18:27:47 +00:00
38e88cb53f
Do not select tSXTB / tSXTH in thumb2 mode.
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llvm-svn: 76600
2009-07-21 18:15:26 +00:00
0d8b0cf3b8
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.
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llvm-svn: 76520
2009-07-21 00:31:12 +00:00
c5df7e2dc1
Emit cross regclass register moves for thumb2.
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Minor code duplication cleanup.
llvm-svn: 76124
2009-07-16 23:26:06 +00:00
72b80ac9b1
Fix detection of valid BFC immediates.
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llvm-svn: 75576
2009-07-14 00:57:56 +00:00
017288a4fc
Don't put IT instruction before conditional branches.
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llvm-svn: 75361
2009-07-11 07:26:20 +00:00
e3c4765bac
convert test to use FileCheck, which is much more precise and faster than
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the previous RUN lines. Hopefully this will be an inspiration for future
tests :)
llvm-svn: 75261
2009-07-10 18:34:47 +00:00
0f9cce7951
Add a thumb2 pass to insert IT blocks.
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llvm-svn: 75218
2009-07-10 01:54:42 +00:00
22c2fba978
Use common code for both ARM and Thumb-2 instruction and register info.
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llvm-svn: 75067
2009-07-08 23:10:31 +00:00
121563c615
Add rev16 test... xfail for now
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llvm-svn: 75012
2009-07-08 16:15:06 +00:00
af7451b674
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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llvm-svn: 75010
2009-07-08 16:09:28 +00:00
d0611f9a37
Add Thumb2 movcc instructions.
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llvm-svn: 74946
2009-07-07 20:39:03 +00:00
d0f6324cdc
Add Thumb2 pkhbt / pkhtb.
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llvm-svn: 74895
2009-07-07 05:35:52 +00:00
b24e51e2d9
Add some more Thumb2 multiplication instructions.
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llvm-svn: 74889
2009-07-07 01:17:28 +00:00
0e8bde5910
Add thumb2 sign / zero extend with rotate instructions.
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llvm-svn: 74755
2009-07-03 01:43:10 +00:00
53cdf022b6
Added indexed stores.
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llvm-svn: 74740
2009-07-03 00:06:39 +00:00
8ecd7eb3f7
Sign extending pre/post indexed loads.
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llvm-svn: 74736
2009-07-02 23:16:11 +00:00
84c6cda2ef
Thumb2 pre/post indexed loads.
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llvm-svn: 74696
2009-07-02 07:28:31 +00:00
86c7e20ca6
Add PIC load and store patterns for Thumb-2.
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llvm-svn: 74577
2009-07-01 00:01:13 +00:00
d0890a2bad
Add thumb-2 store word, halfword, and byte.
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llvm-svn: 74555
2009-06-30 22:11:34 +00:00
28d6d87244
Improve Thumb-2 jump table support.
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llvm-svn: 74549
2009-06-30 19:50:22 +00:00
57726817aa
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
17512663f5
Enhance tests to include shifted-register operand testing.
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llvm-svn: 74490
2009-06-30 01:02:20 +00:00
76b37950ca
Add Thumb-2 support for TEQ amd TST.
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llvm-svn: 74468
2009-06-29 22:49:42 +00:00
911edef65b
Thumb-2 tests
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llvm-svn: 74464
2009-06-29 22:25:22 +00:00
dbf11ba800
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
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llvm-svn: 74423
2009-06-29 15:33:01 +00:00
b23b50d54d
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
5285817490
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
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llvm-svn: 74355
2009-06-26 23:13:13 +00:00
3aaa751712
Thumb-2 tests
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llvm-svn: 74345
2009-06-26 22:37:07 +00:00
aa294c5593
Thumb-2 has CLZ.
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llvm-svn: 74322
2009-06-26 20:47:43 +00:00
35ee722d42
Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
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llvm-svn: 74321
2009-06-26 20:45:56 +00:00
a720af1370
More spelling Count as count.
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llvm-svn: 74306
2009-06-26 18:35:07 +00:00
6b1678d5d8
Spell Count as count.
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llvm-svn: 74298
2009-06-26 18:21:54 +00:00
3bd42afebe
Add Thumb-2 tests.
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llvm-svn: 74295
2009-06-26 18:10:30 +00:00
5960e6d974
ADC used to implement adde should use "adcs" opcode instead of "adc".
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llvm-svn: 74293
2009-06-26 18:07:25 +00:00
34f7ede9e7
ORN and BIC tests.
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llvm-svn: 74289
2009-06-26 16:20:06 +00:00
0377f737ff
Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
...
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.
llvm-svn: 74288
2009-06-26 16:10:07 +00:00
7779156b39
Fix tests: Count -> count.
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llvm-svn: 74282
2009-06-26 07:05:57 +00:00
34c8c7414f
Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates.
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llvm-svn: 74276
2009-06-26 05:59:16 +00:00
07025e2c02
Fix spelling of 'count'
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llvm-svn: 74249
2009-06-26 01:33:02 +00:00
97727a61f9
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
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llvm-svn: 74228
2009-06-25 23:34:10 +00:00
16f357cccf
Use MVN for ~t2_so_imm immediates.
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llvm-svn: 74223
2009-06-25 23:11:21 +00:00
c7ea8df67e
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
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llvm-svn: 74200
2009-06-25 20:59:23 +00:00
83f979a48b
Add Thumb2 pc relative add.
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llvm-svn: 74141
2009-06-24 23:47:58 +00:00
ff1a4a7271
We should run these tests as well.
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llvm-svn: 74121
2009-06-24 21:36:26 +00:00
d76d0aa68a
Move thumb and thumb2 tests into separate directories.
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llvm-svn: 74068
2009-06-24 06:36:07 +00:00
Bob Wilson