Commit Graph

321900 Commits

Author SHA1 Message Date
Owen Reynolds 629273ec09 [llvm-ar][test] Add tests failing on Darwin
These tests that failed on Darwin but passed on other machines due to the default archive format differing
on a Darwin machine, and what looks to be bugs in the output of this format.
I can not investigate these issue further so the tests are considered expected failures on Darwin.

Differential Revision: https://reviews.llvm.org/D64802

llvm-svn: 366334
2019-07-17 15:10:02 +00:00
Chris Jackson 87886299b4 [lld] Add Visual Studio compatible diagnostics
Summary:
Add a --vs-diagnostics flag that alters the format of diagnostic output
to enable source hyperlinks in Visual Studio.

Differential Revision: https://reviews.llvm.org/D58484

Reviewed by: ruiu

llvm-svn: 366333
2019-07-17 14:54:02 +00:00
Gabor Marton ae512b83d5 [ASTImporter] Fix structural eq of lambdas
Summary:
The structural equivalence check reported false eq between lambda classes
with different parameters in their call signature.
The solution is to check the methods for equality too in case of lambda
classes.

Reviewers: a_sidorin, a.sidorin

Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64075

llvm-svn: 366332
2019-07-17 14:40:09 +00:00
Alex Bradbury 80de11ed02 [RISCV] Add RISCV to LLVM_ALL_TARGETS so it s built by default
This follows the RFC <http://lists.llvm.org/pipermail/llvm-dev/2019-July/133724.html>.

Follow-on commits will add appropriate release notes changes etc.

Pushing this now and in a minimal form so there is reasonable time before 9.0
branches to resolve any issues arising from e.g. the backend being exposed on
different sanitizer setups.

The current builder for RISC-V is on the staging build-bot
<http://lab.llvm.org:8014/builders/llvm-riscv-linux>, however with the RISCV
backend being built by default it won't provide any real additional coverage.
We will shortly set up a builder that runs the test-suite in qemu-user.

llvm-svn: 366331
2019-07-17 14:32:25 +00:00
Alex Bradbury c74fded05f [RISCV][NFC] Remove outdated TODO from test/CodeGen/RISCV/dwarf-eh.ll
llvm-svn: 366330
2019-07-17 14:04:48 +00:00
Alex Bradbury ab009a602e [AsmPrinter] Make the encoding of call sites in .gcc_except_table configurable and use for RISC-V
The original behavior was to always emit the offsets to each call site in the
call site table as uleb128 values, however on some architectures (eg RISCV)
these uleb128 offsets into the code cannot always be resolved until link time
(because relaxation will invalidate any calculated offsets), and there are no
appropriate relocations for uleb128 values. As a consequence it needs to be
possible to specify an alternative.

This also switches RISCV to use DW_EH_PE_udata4 for call side encodings in
.gcc_except_table

Differential Revision: https://reviews.llvm.org/D63415
Patch by Edward Jones.

llvm-svn: 366329
2019-07-17 14:00:35 +00:00
Matt Arsenault 6584c4842f Mips: Remove immarg from copy and insert intrinsics
These intrinsics do in fact work with non-constant index arguments.

These are lowered to either the generic
ISD::INSERT_VECTOR_ELT/ISD::EXTRACT_VECTOR_ELT, or to
VEXTRACT_SEXT_ELT. The handling of these all accept variable
indexes. Turning these into generic instructions which do allow
variables introduces complications in a future change to immarg
handling.

Since these just turn into generic instructions, these are kind of
pointless and should probably just be autoupgraded to
extractelement/insertelement.

llvm-svn: 366328
2019-07-17 13:55:01 +00:00
Alex Bradbury b94c233d06 [RISCV] Set correct encodings for DWARF exception handling
This patch sets correct encodings for DWARF exception handling for RISC-V
(other than call site encoding, which must be udata4 rather than uleb128 and
is handled by D63415).

This has the same intend as D63409, except this version matches GCC/binutils
behaviour which uses the same encodings regardless of PIC/non-PIC and
medlow/medany code model.

llvm-svn: 366327
2019-07-17 13:54:38 +00:00
Alex Bradbury aa55124eca [RISCV][NFC] Add tests that capture current encodings for DWARF EH
Items which are known to be wrong/different vs GCC are marked as TODO and will
be address in follow-up patches.

llvm-svn: 366326
2019-07-17 13:48:49 +00:00
Gabor Marton aefcf5100a [ASTImporter] Fix LLDB lookup in transparent ctx and with ext src
Summary:
With LLDB we use localUncachedLookup(), however, that fails to find
Decls when a transparent context is involved and the given DC has
external lexical storage.  The solution is to use noload_lookup, which
works well with transparent contexts.  But, we cannot use only the
noload_lookup since the slow case of localUncachedLookup is still needed
in some other cases.

These other cases are handled in ASTImporterLookupTable, but we cannot
use that with LLDB since that traverses through the AST which initiates
the load of external decls again via DC::decls().

We must avoid loading external decls during the import becuase
ExternalASTSource is implemented with ASTImporter, so external loads
during import results in uncontrolled and faulty import.

Reviewers: shafik, teemperor, jingham, clayborg, a_sidorin, a.sidorin

Subscribers: rnkovacs, dkrupp, Szelethus, gamesh411, cfe-commits, lldb-commits

Tags: #clang, #lldb

Differential Revision: https://reviews.llvm.org/D61333

llvm-svn: 366325
2019-07-17 13:47:46 +00:00
Fangrui Song 62069ac310 [llvm-ar][test] \r\n -> \n
Also simplify some empty output tests with 'count 0'

llvm-svn: 366324
2019-07-17 13:40:42 +00:00
Jay Foad 70235c642e [AMDGPU] Optimize atomic AND/OR/XOR
Summary: Extend the atomic optimizer to handle AND, OR and XOR.

Reviewers: arsenm, sheredom

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64809

llvm-svn: 366323
2019-07-17 13:40:03 +00:00
Momchil Velikov 4b8da3a503 [AArch64] Add support for Transactional Memory Extension (TME)
TME is a future architecture technology, documented in

https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools
https://developer.arm.com/docs/ddi0601/a

More about the future architectures:

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture

This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and
TCANCEL and the target feature/arch extension "tme".

It also implements TME builtin functions, defined in ACLE Q2 2019
(https://developer.arm.com/docs/101028/latest)

Patch by Javed Absar and Momchil Velikov

Differential Revision: https://reviews.llvm.org/D64416

llvm-svn: 366322
2019-07-17 13:23:27 +00:00
Sam McCall 2889fe6769 [clangd] Force the required interpretation of #import on windows tests.
Summary: NFC but should fix a bunch of tests.

Reviewers: kadircet

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64857

llvm-svn: 366321
2019-07-17 13:21:25 +00:00
Kadir Cetinkaya 6011a285ed [clangd] Handle windows line endings in QueryDriver
Summary: fixes second case of https://github.com/clangd/clangd/issues/93

Reviewers: sammccall

Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64789

llvm-svn: 366320
2019-07-17 13:14:02 +00:00
Justin Hibbits 0257c6b659 PowerPC: Fix register spilling for SPE registers
Summary:
Missed in the original commit, use the correct callee-saved register
list for spilling, instead of the standard SVR432 list.  This avoids
needlessly spilling the SPE non-volatile registers when they're not used.

As part of this, also add where missing, and sort, the spill opcode
checks for SPE and SPE4 register classes.

Reviewers: nemanjai, hfinkel, joerg

Subscribers: kbarton, jsji, llvm-commits

Differential Revision: https://reviews.llvm.org/D56703

llvm-svn: 366319
2019-07-17 12:30:48 +00:00
Justin Hibbits 5214956eaa PowerPC/SPE: Fix load/store handling for SPE
Summary:
Pointed out in a comment for D49754, register spilling will currently
spill SPE registers at almost any offset.  However, the instructions
`evstdd` and `evldd` require a) 8-byte alignment, and b) a limit of 256
(unsigned) bytes from the base register, as the offset must fix into a
5-bit offset, which ranges from 0-31 (indexed in double-words).

The update to the register spill test is taken partially from the test
case shown in D49754.

Additionally, pointed out by Kei Thomsen, globals will currently use
evldd/evstdd, though the offset isn't known at compile time, so may
exceed the 8-bit (unsigned) offset permitted.  This fixes that as well,
by forcing it to always use evlddx/evstddx when accessing globals.

Part of the patch contributed by Kei Thomsen.

Reviewers: nemanjai, hfinkel, joerg

Subscribers: kbarton, jsji, llvm-commits

Differential Revision: https://reviews.llvm.org/D54409

llvm-svn: 366318
2019-07-17 12:30:04 +00:00
Petar Avramovic 1e62635d05 [MIPS GlobalISel] ClampScalar and select pointer G_ICMP
Add narrowScalar to half of original size for G_ICMP.
ClampScalar G_ICMP's operands 2 and 3 to to s32.
Select G_ICMP for pointers for MIPS32. Pointer compare is same
as for integers, it is enough to declare them as legal type.

Differential Revision: https://reviews.llvm.org/D64856

llvm-svn: 366317
2019-07-17 12:08:01 +00:00
Raphael Isemann 60bd7a9c13 [lldb][NFC] Tablegenify watchpoint commands
Part of the project that migrates these struct initializers to our
new lldb-tablegen.

llvm-svn: 366316
2019-07-17 11:48:29 +00:00
Momchil Velikov e14cfe2d2e [AArch64] Consistent types and naming for AArch64 target features (NFC)
Differential Revision: https://reviews.llvm.org/D64415

Committed as obvious.

llvm-svn: 366315
2019-07-17 11:24:37 +00:00
Nicolai Haehnle 8b7041a5c6 AMDGPU/GFX10: Apply the VMEM-to-scalar-write hazard also to writes to EXEC
Summary: Change-Id: I854fbf7d48e937bef9f8f3f5d0c8aeb970652630

Reviewers: rampitec, mareko

Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64807

Change-Id: I4405b3a7f84186acea5a78d291bff71056e745fc
llvm-svn: 366314
2019-07-17 11:22:57 +00:00
Nicolai Haehnle a256b8b7d7 AMDGPU: Improve alias analysis for GDS
Summary: GDS cannot alias anything else.

Original patch by: Marek Olšák

Reviewers: arsenm, mareko

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64114

Change-Id: I07bfbd96f5d5c37a6dfba7997df12f291dd794b0
llvm-svn: 366313
2019-07-17 11:22:19 +00:00
Momchil Velikov 52c3939615 [TableGen] Do not set ReadNone attribute on intrinsics with side effects
If an intrinsic is defined without outputs, but having side effects,
it still can be removed completely from the program. This patch makes
TableGen not set Attribute::ReadNone for intrinsics which
are declared with IntrHasSideEffects.

Differential Revision: https://reviews.llvm.org/D64414

llvm-svn: 366312
2019-07-17 10:53:13 +00:00
Sam McCall 11b06242a7 [clangd] Fix error message in tweaktests to be useful. NFC
llvm-svn: 366311
2019-07-17 10:17:47 +00:00
Owen Reynolds 247add6f3a [llvm-ar][test] Add coverage for replace and update key letters
Some more tests to increase llvm-ar test coverage, this time for replace 'r' and update 'u'.

Differential Revision: https://reviews.llvm.org/D64803

llvm-svn: 366309
2019-07-17 10:16:44 +00:00
Diana Picus 37e403d18c [ARM GlobalISel] Cleanup CallLowering. NFC
Migrate CallLowering::lowerReturnVal to use the same infrastructure as
lowerCall/FormalArguments and remove the now obsolete code path from
splitToValueTypes.

Forgot to push this earlier.

llvm-svn: 366308
2019-07-17 10:01:27 +00:00
Fangrui Song 2be0ebb0d8 [ELF] Delete redundant pageAlign at PT_GNU_RELRO boundaries after D58892
Summary:
After D58892 split the RW PT_LOAD on the PT_GNU_RELRO boundary, the new
layout is:

PT_LOAD(PT_GNU_RELRO(.data.rel.ro .bss.rel.ro)) PT_LOAD(.data. .bss)

The two pageAlign() calls at PT_GNU_RELRO boundaries are redundant due
to the existence of PT_LOAD.

Reviewers: grimar, peter.smith, ruiu, espindola

Reviewed By: ruiu

Subscribers: sfertile, atanasyan, emaste, arichardson, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64854

llvm-svn: 366307
2019-07-17 09:23:04 +00:00
Marco Antognini 9eb95903da [OpenCL][Sema] Minor refactoring and constraint checking
Summary:
Simplify code a bit and add assertion to address post-landing comments
from D64083.

Subscribers: yaxunl, Anastasia, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64804

llvm-svn: 366306
2019-07-17 08:52:09 +00:00
Rainer Orth 9662721572 [Driver] Enable __cxa_atexit on Solaris
Starting with Solaris 11.4 (which is now the required minimal version), Solaris does
support __cxa_atexit.  This patch reflects that.

One might consider removing the affected tests altogether instead of inverting them,
as is done on other targets.

Besides, this lets two ASan tests PASS:

  AddressSanitizer-i386-sunos :: TestCases/init-order-atexit.cc
  AddressSanitizer-i386-sunos-dynamic :: TestCases/init-order-atexit.cc

Tested on x86_64-pc-solaris2.11 and sparcv9-sun-solaris2.11.

Differential Revision: https://reviews.llvm.org/D64491

llvm-svn: 366305
2019-07-17 08:37:00 +00:00
Rui Ueyama 42cfbafc1f Replace CRLF with LF.
llvm-svn: 366304
2019-07-17 08:31:51 +00:00
Simon Atanasyan 1292464125 [mips] Remove redundant test case. NFC
The `inlineasm-constraint-reg64.ll` test checks the same functionality.

llvm-svn: 366303
2019-07-17 08:12:03 +00:00
Simon Atanasyan 6d4b1c046b [mips] Name inline asm constraint test cases in a uniform manner. NFC
llvm-svn: 366302
2019-07-17 08:11:57 +00:00
Simon Atanasyan 4c1e440892 [mips] Use mult/mflo pattern on 64-bit targets prior to MIPS64
The `MUL` instruction is available starting from the MIPS32/MIPS64 targets.

llvm-svn: 366301
2019-07-17 08:11:40 +00:00
Simon Atanasyan a884afb6f8 [mips] Implement .cplocal directive
This directive forces to use the alternate register for context pointer.
For example, this code:
  .cplocal $4
  jal foo
expands to:
  ld    $25, %call16(foo)($4)
  jalr  $25

Differential Revision: https://reviews.llvm.org/D64743

llvm-svn: 366300
2019-07-17 08:11:31 +00:00
Simon Atanasyan 7f308af5ee [mips] Support the "o" inline asm constraint
As well as other LLVM targets we do not handle "offsettable"
memory addresses in any special way. In other words, the "o" constraint
is an exact equivalent of the "m" one. But some existing code require
the "o" constraint support.

This fixes PR42589.

Differential Revision: https://reviews.llvm.org/D64792

llvm-svn: 366299
2019-07-17 08:11:15 +00:00
Alex Langford fc1c8f5d7d [Target][NFCI] Remove commented out code
llvm-svn: 366295
2019-07-17 07:13:42 +00:00
Serguei Katkov 587d13d4c2 [LoopInfo] Fix getUniqueNonLatchExitBlocks
It is possible that exit block has two predecessors and one of them is a latch
block while another is not.

Current algorithm is based on the assumption that all exits are dedicated
and therefore we can check only first predecessor of loop exit to find all unique
exits.

However if we do not consider latch block and it is first predecessor of some
exit then this exit will be found.

Regression test is added.

As a side effect of algorithm re-writing, the restriction that all exits are dedicated
is eliminated.

Reviewers: reames, fhahn, efriedma
Reviewed By: efriedma
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D64787

llvm-svn: 366294
2019-07-17 07:09:20 +00:00
Nathan Lanza 06bf5d8538 [NativePDB] Make GetTranslationUnitDecl return an lldb CompilerDeclCtx
Summary:
We intend to make PdbAstBuilder abstract and implement
PdbAstBuilderClang along with any other languages that wish to use
PDBs. This is the first step.

Differential Revision: https://reviews.llvm.org/D64852

llvm-svn: 366293
2019-07-17 07:05:49 +00:00
Alex Langford e574f8b3d8 [Target][NFCI] Rename variable
This variable doesn't have anything to do with clang.

llvm-svn: 366292
2019-07-17 07:03:17 +00:00
Qiu Chaofan 4c77a696ae Update email address.
llvm-svn: 366291
2019-07-17 07:02:02 +00:00
Nico Weber 67cf3d61ee gn build: Merge r366265
llvm-svn: 366289
2019-07-17 01:21:14 +00:00
Nico Weber 420f3f6444 gn build: Merge r366216
llvm-svn: 366288
2019-07-17 01:19:30 +00:00
Matt Arsenault e56865d40c AMDGPU: Add some missing builtins
llvm-svn: 366286
2019-07-17 00:01:03 +00:00
Nathan Lanza 98a48794ec Don't require python exe and lib versions to match while crosscompiling
Summary:
While cross compiling, the python executable is used to run a handful
of scripts while the libraries are linked and headers are included.
Theoretically it's possible for the versions to match completely, but
requiring the build to match 2.7.10 to 2.7.15 is unnecessary.

Subscribers: mgorny

Differential Revision: https://reviews.llvm.org/D64822

llvm-svn: 366285
2019-07-16 23:54:17 +00:00
Reid Kleckner 9304e59c01 Fix OpenCLCXX test on 32-bit Windows where thiscall is present
llvm-svn: 366284
2019-07-16 23:44:33 +00:00
Stanislav Mekhanoshin e5012ab308 [AMDGPU] Autogenerate register asm names
Differential Revision: https://reviews.llvm.org/D64839

llvm-svn: 366283
2019-07-16 23:44:21 +00:00
Reid Kleckner 2ecca781a1 Fix darwin-ld.c if dsymutil.exe exists on PATH
llvm-svn: 366282
2019-07-16 23:38:05 +00:00
Nathan Lanza e71679082c add a workaround in GetLine to account for ReadFile not reporintg error
Summary:
ReadFile on Windows is supposed to set ERROR_OPERATION_ABORTED according
to the docs on MSDN. However, this has evidently been a known bug since
Windows 8. Therefore, we can't detect if a signal interrupted in the
fgets. So pressing ctrl-c causes the repl to end and the process to
exit. A temporary workaround is just to attempt to fgets twice until
this bug is fixed.

A possible alternative would be to set a flag in the `sigint_handler`
and simply check that flag in the true part of the if statement.
However, signal handlers on Windows are asynchronous and this would
require sleeping on the repl loop thread while still not necessarily
guarnateeing that you caught the sigint.

Reviewers: jfb

Differential Revision: https://reviews.llvm.org/D64660

llvm-svn: 366281
2019-07-16 23:01:59 +00:00
Matt Arsenault 1bd9c6547f ARM: Fix missing immarg for space intrinsic
llvm-svn: 366280
2019-07-16 22:41:38 +00:00
Matt Arsenault 1c3f4ec7fc GlobalISel: Add overload of handleAssignments with CCState
AMDGPU needs to allocate special argument registers separately from
the user function argument list, so needs direct control over the
CCState.

The ArgLocs argument is only really necessary because CCState doesn't
allow access to it.

llvm-svn: 366279
2019-07-16 22:41:34 +00:00