Commit Graph

8 Commits

Author SHA1 Message Date
Zakk Chen 821547cabb [RISCV][Clang] Update new overloading rules for RVV intrinsics.
RVV intrinsics has new overloading rule, please see
82aac7dad4

Changed:
1. Rename `generic` to `overloaded` because the new rule is not using C11 generic.
2. Change HasGeneric to HasNoMaskedOverloaded because all masked operations
   support overloading api.
3. Add more overloaded tests due to overloading rule changed.

Differential Revision: https://reviews.llvm.org/D99189
2021-03-28 09:04:35 -07:00
Zakk Chen 88c2d4c8eb [RISCV][Clang] Add RVV Vector Indexed Load intrinsic functions.
Support Complex type transformer to define more complexity legal type.

Overall our downstream implementation there are only four instructions need to
use complex type transformer, it's not a common case.
I still feel using a string for prototypes is simple and clear.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D98848
2021-03-23 19:18:50 -07:00
Zakk Chen be947aded0 [RISCV][Clang] Add RVV vle/vse intrinsic functions.
Add new field PermuteOperands to mapping different operand order between
C/C++ API and clang builtin.

Reviewed By: craig.topper, rogfer01

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Differential Revision: https://reviews.llvm.org/D98388
2021-03-17 20:31:25 -07:00
Zakk Chen 95c0125f2b [Clang][RISCV] Add rvv vsetvl and vsetvlmax intrinsic functions.
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D96843
2021-03-17 20:26:06 -07:00
Jim Lin 678241795c [RISCV] Don't emit #undef BUILTIN from RISCVVEmitter.cpp
In BuiltinsRISCV.def, other extension 's intrinsics need to be defined by using macro BUILTIN.
So, it shouldn't undefine macro BUILTIN in the end of declaration for V intrinsics.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D98682
2021-03-16 14:57:45 +08:00
Simon Pilgrim d53866ff47 Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warnings. NFCI. 2021-03-11 10:29:14 +00:00
Craig Topper 9773cad519 [RISCV] Add additional checking to tablgen RISCVVEmitter requested in D95016.
This errors, but doesn't give source location. We'd need to pass
the Record through several layers to get to the location.

Reviewed By: jrtc27

Differential Revision: https://reviews.llvm.org/D98379
2021-03-10 19:46:25 -08:00
Zakk Chen d6a0560bf2 [Clang][RISCV] Add custom TableGen backend for riscv-vector intrinsics.
Demonstrate how to generate vadd/vfadd intrinsic functions

1. add -gen-riscv-vector-builtins for clang builtins.
2. add -gen-riscv-vector-builtin-codegen for clang codegen.
3. add -gen-riscv-vector-header for riscv_vector.h. It also generates
ifdef directives with extension checking, base on D94403.
4. add -gen-riscv-vector-generic-header for riscv_vector_generic.h.
Generate overloading version Header for generic api.
https://github.com/riscv/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#c11-generic-interface
5. update tblgen doc for riscv related options.

riscv_vector.td also defines some unused type transformers for vadd,
because I think it could demonstrate how tranfer type work and we need
them for the whole intrinsic functions implementation in the future.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Reviewed By: jrtc27, craig.topper, HsiangKai, Jim, Paul-C-Anagnostopoulos

Differential Revision: https://reviews.llvm.org/D95016
2021-03-10 18:43:43 -08:00