Commit Graph

1441 Commits

Author SHA1 Message Date
Petr Hosek 68a3a3b281 [Clang] Enable RISC-V support for Fuchsia
We don't have a full sysroot yet, so for now we only include compiler
support and compiler-rt builtins, the rest of the runtimes will get
enabled later.

Differential Revision: https://reviews.llvm.org/D70477
2019-11-21 16:02:26 -08:00
Tim Northover 44e5879f0f AArch64: add arm64_32 support to Clang. 2019-11-12 12:45:18 +00:00
Sam Elliott f46d413fa0 [RISCV] Add FreeBSD targets
Reviewers: asb

Reviewed By: asb

Subscribers: simoncook, s.egerton, lenary, psnobl, benna, mhorne, emaste, kito-cheng, shiva0217, rogfer01, rkruppe, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D57795

Patch by James Clarke (jrtc27)

llvm-svn: 367557
2019-08-01 13:14:30 +00:00
Reid Kleckner 8777df5270 De-templatize non-dependent VS macro logic, NFC
These macro definitions don't depend on the template parameter, so they
don't need to be part of the template. Move them to a .cpp file.

llvm-svn: 365556
2019-07-09 20:57:28 +00:00
Alon Zakai b4f9991f38 [WebAssembly] Add Emscripten OS definition + small_printf
The Emscripten OS provides a definition of __EMSCRIPTEN__, and also that it
supports iprintf optimizations.

Also define small_printf optimizations, which is a printf with float support
but not long double (which in wasm can be useful since long doubles are 128
bit and force linking of float128 emulation code). This part is based on
sunfish's https://reviews.llvm.org/D57620 (which can't land yet since
the WASI integration isn't ready yet).

Differential Revision: https://reviews.llvm.org/D60167

llvm-svn: 357552
2019-04-03 01:08:35 +00:00
Jason Liu 7f7867b05a Reland the rest of "Add AIX Target Info"
llvm-svn 356197 relanded previously failing test case max_align.c.
This commit will reland the rest of llvm-svn 356060 commit.

Differential Revision: https://reviews.llvm.org/D59048

llvm-svn: 356208
2019-03-14 21:54:30 +00:00
Jason Liu e62ccefe44 Revert "Add AIX Target Info"
This reverts commit 4e192d0e1e.
The newly added test case max_align.c do not work on all platforms.

original llvm-svn: 356060

llvm-svn: 356070
2019-03-13 17:57:23 +00:00
Jason Liu 4e192d0e1e Add AIX Target Info
Summary:
A first pass over platform-specific properties of the C API/ABI
on AIX for both 32-bit and 64-bit modes.
This is a continuation of D18360 by Andrew Paprocki and further work by Wu Zhao.

Patch by Andus Yu

Reviewers: apaprocki, chandlerc, hubert.reinterpretcast, jasonliu,
xingxue, sfertile

Reviewed by: hubert.reinterpretcast, apaprocki, sfertile

Differential Revision: https://reviews.llvm.org/D59048

llvm-svn: 356060
2019-03-13 16:02:26 +00:00
Dan Gohman c1eee1d659 [WebAssembly] Add a __wasi__ target macro
This adds a `__wasi__` macro for the wasi OS, similar to `__linux__` etc. for
other OS's.

Differential Revision: https://reviews.llvm.org/D57155

llvm-svn: 352105
2019-01-24 21:05:11 +00:00
Chandler Carruth 2946cd7010 Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636
2019-01-19 08:50:56 +00:00
Dan Gohman 788ce374c4 [WebAssembly] COWS has been renamed to WASI.
llvm-svn: 351298
2019-01-16 05:23:57 +00:00
Craig Topper 5589738979 [Nios2] Remove Nios2 backend
As mentioned here http://lists.llvm.org/pipermail/llvm-dev/2019-January/129121.html This backend is incomplete and has not been maintained in several months.

Differential Revision: https://reviews.llvm.org/D56690

llvm-svn: 351230
2019-01-15 19:58:36 +00:00
Dan Gohman 055a6f0462 [WebAssembly] Support multilibs for wasm32 and add a wasm OS that uses it
This adds support for multilib paths for wasm32 targets, following
[Debian's Multiarch conventions], and also adds an experimental OS name in
order to test it. 

[Debian's Multiarch conventions]: https://wiki.debian.org/Multiarch/

Differential Revision: https://reviews.llvm.org/D56553

llvm-svn: 351164
2019-01-15 06:58:16 +00:00
Kristina Brooks 77a4adc4f9 Add Hurd target to Clang driver (2/2)
This adds Hurd toolchain support to Clang's driver in addition
to handling translating the triple from Hurd-compatible form to
the actual triple registered in LLVM.

(Phabricator was stripping the empty files from the patch so I 
manually created them)

Patch by sthibaul (Samuel Thibault)

Differential Revision: https://reviews.llvm.org/D54379

llvm-svn: 347833
2018-11-29 03:49:14 +00:00
Tatyana Krasnukha f8c264e02e [clang][ARC] Add ARCTargetInfo
Based-on-patch-by: Pete Couperus <petecoup@synopsys.com>

Differential Revision: https://reviews.llvm.org/D53100

llvm-svn: 347699
2018-11-27 19:52:10 +00:00
Fangrui Song 1d38c13f6e Use the container form llvm::sort(C, ...)
There are a few leftovers of rC343147 that are not (\w+)\.begin but in
the form of ([-[:alnum:]>.]+)\.begin or spanning two lines. Change them
to use the container form in this commit. The 12 occurrences have been
inspected manually for safety.

llvm-svn: 343425
2018-09-30 21:41:11 +00:00
Leonard Chan db01c3adc6 [Fixed Point Arithmetic] Fixed Point Precision Bits and Fixed Point Literals
This diff includes the logic for setting the precision bits for each primary fixed point type in the target info and logic for initializing a fixed point literal.

Fixed point literals are declared using the suffixes

```
hr: short _Fract
uhr: unsigned short _Fract
r: _Fract
ur: unsigned _Fract
lr: long _Fract
ulr: unsigned long _Fract
hk: short _Accum
uhk: unsigned short _Accum
k: _Accum
uk: unsigned _Accum
```
Errors are also thrown for illegal literal values

```
unsigned short _Accum u_short_accum = 256.0uhk;   // expected-error{{the integral part of this literal is too large for this unsigned _Accum type}}
```

Differential Revision: https://reviews.llvm.org/D46915

llvm-svn: 335148
2018-06-20 17:19:40 +00:00
Eli Friedman e54d0ff400 [TargetInfo] Sort target features before passing them to the backend
Passing the features in random order will lead to unpredictable results
when some of the features are related (like the architecture-version
features on ARM).

It might be possible to fix this particular case in the ARM target code,
to avoid adding overlapping target features. But we should probably be
sorting in any case: the behavior shouldn't depend on StringMap's
hashing algorithm.

Differential Revision: https://reviews.llvm.org/D46030

llvm-svn: 330861
2018-04-25 19:14:05 +00:00
Yaxun Liu bec8a66454 [CUDA] Revert defining __CUDA_ARCH__ for amdgcn targets
amdgcn targets only support HIP, which does not define __CUDA_ARCH__.

this is a partial unroll of r329232 / D45277.

Differential Revision: https://reviews.llvm.org/D45387

llvm-svn: 329584
2018-04-09 15:43:01 +00:00
Yaxun Liu 8391387f7b [HIP] define __CUDA_ARCH_=1 for amdgcn targets
Differential Revision: https://reviews.llvm.org/D45277

llvm-svn: 329420
2018-04-06 16:43:42 +00:00
Yaxun Liu 8a5fc15aa4 [CUDA] Add amdgpu sub archs
Patch by Greg Rodgers.
Revised and lit tests added by Yaxun Liu.

Differential Revision: https://reviews.llvm.org/D45277

llvm-svn: 329232
2018-04-04 21:19:27 +00:00
Erich Keane 3ec1743d0d Make march/target-cpu print a note with the list of valid values for ARM
When rejecting a march= or target-cpu command line parameter,
the message is quite lacking. This patch adds a note that prints
all possible values for the current target, if the target supports it.

This adds support for the ARM/AArch64 targets (more to come!). 

Differential Revision: https://reviews.llvm.org/D42978 

llvm-svn: 324673
2018-02-08 23:14:15 +00:00
Alex Bradbury 3e1478f866 [RISCV] Create a LinuxTargetInfo when targeting Linux
Previously, RISCV32TargetInfo or RISCV64TargetInfo were created 
unconditionally. Use LinuxTargetInfo<RISCV??TargetInfo> to ensure that the 
proper OS-specific defines are present.

This patch only adds logic to instantiate LinuxTargetInfo and leaves a TODO, 
as I'm reluctant to add logic for other targets (e.g. FreeBSD, RTEMS) until 
I've produced and tested at least one binary for that OS+target combo.

Thanks to @mgrang to reporting the issue.

llvm-svn: 324170
2018-02-03 11:56:11 +00:00
Alex Bradbury 71f45455e1 [RISCV] Add the RISCV target and compiler driver
As RV64 codegen has not yet been upstreamed into LLVM, we focus on RV32 driver 
support (RV64 to follow).

Differential Revision: https://reviews.llvm.org/D39963

llvm-svn: 322276
2018-01-11 13:36:56 +00:00
Martell Malone 051e966e49 [MINGW] normalize WIN32 macros
move _WIN64 and _WIN32 defines to lib/Basic/Targets/OSTargets.h
move WIN32, WIN64 and __MINGW64__ to addMinGWDefines

fixes __MINGW64__ not being defined for aarch64
adds WIN32 definition for x64

Reviewers: mstorsjo

Differential Revision: https://reviews.llvm.org/D40285

llvm-svn: 318755
2017-11-21 11:28:29 +00:00
Wei Mi b086289787 [Atomic][X8664] set max atomic inline width according to the target
This is to fix PR31620. MaxAtomicInlineWidth is set to 128 for x86_64. However
for target without cx16 support, 128 atomic operation will generate __sync_*
libcalls. The patch set MaxAtomicInlineWidth to 64 if the target doesn't support
cx16.

Differential Revision: https://reviews.llvm.org/D38046

llvm-svn: 313992
2017-09-22 16:30:00 +00:00
Martin Storsjo 31cac7a67c [AArch64] Add support for a MinGW AArch64 target
Differential Revision: https://reviews.llvm.org/D36364

llvm-svn: 310798
2017-08-13 19:42:17 +00:00
Martin Storsjo e2a247ccb0 [Targets] Move addCygMingDefines into the arch-independent Targets.cpp (NFC)
This fixes a dependency inconsistency, where addMinGWDefines in Targets.cpp
(used from other architectures than X86) called the addCygMingDefines function
in X86.h.

This was inconsistently split in SVN r308791 (D35701).

Differential Revision: https://reviews.llvm.org/D36072

llvm-svn: 309598
2017-07-31 18:17:38 +00:00
Erich Keane 2b9657b570 Remove Bitrig: Clang Changes
Bitrig code has been merged back to OpenBSD, thus the OS has been abandoned.

Differential Revision: https://reviews.llvm.org/D35708

llvm-svn: 308797
2017-07-21 22:46:31 +00:00
Erich Keane ebba592682 Break up Targets.cpp into a header/impl pair per target type[NFCI]
Targets.cpp is getting unwieldy, and even minor changes cause the entire thing 
to cause recompilation for everyone. This patch bites the bullet and breaks 
it up into a number of files.

I tended to keep function definitions in the class declaration unless it 
caused additional includes to be necessary. In those cases, I pulled it 
over into the .cpp file. Content is copy/paste for the most part, 
besides includes/format/etc.


Differential Revision: https://reviews.llvm.org/D35701

llvm-svn: 308791
2017-07-21 22:37:03 +00:00
Krzysztof Parzyszek 33e67ad098 [Hexagon] Add inline-asm constraint 'a' for modifier register class
For example
  asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory")

llvm-svn: 308763
2017-07-21 18:07:15 +00:00
Artem Belevich d7a73824e4 [NVPTX] Add lowering of i128 params.
The patch adds support of i128 params lowering. The changes are quite trivial to
support i128 as a "special case" of integer type. With this patch, we lower i128
params the same way as aggregates of size 16 bytes: .param .b8 _ [16].

Currently, NVPTX can't deal with the 128 bit integers:
* in some cases because of failed assertions like
  ValVTs.size() == OutVals.size() && "Bad return value decomposition"
* in other cases emitting PTX with .i128 or .u128 types (which are not valid [1])
  [1] http://docs.nvidia.com/cuda/parallel-thread-execution/index.html#fundamental-types

Differential Revision: https://reviews.llvm.org/D34555
Patch by: Denys Zariaiev (denys.zariaiev@gmail.com)

llvm-svn: 308675
2017-07-20 21:16:03 +00:00
Craig Topper 9377b9fa69 [X86] Put avx512vpopcntdq in the right spot in the validateCpuSupports string switch.
The validateCpuSupports switch is in the order of the enum defined in CGBuiltin.cpp and libgcc/compiler-rt.

llvm-svn: 308546
2017-07-19 22:58:58 +00:00
Erich Keane 2c748cc756 Add isValidCPUName and isValidFeature to TargetInfo
These two functions are really useful for implementations of attributes 
(including attribute-target), so add the functionality.

llvm-svn: 308530
2017-07-19 21:50:08 +00:00
Mandeep Singh Grang daa40b98ef [COFF, ARM64] Set the data type widths and the data layout string
Summary: COFF ARM64 is LLP64 platform. So int is 4 bytes, long is 4 bytes and long long is 8 bytes.

Reviewers: compnerd, ruiu, rnk, efriedma

Reviewed By: compnerd, efriedma

Subscribers: efriedma, javed.absar, cfe-commits, aemerson, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D34859

llvm-svn: 308222
2017-07-17 21:10:45 +00:00
Martin Storsjo 022e782e75 [AArch64] Add support for __builtin_ms_va_list on aarch64
Move builtins from the x86 specific scope into the global
scope. Their use is still limited to x86_64 and aarch64 though.

This allows wine on aarch64 to properly handle variadic functions.

Differential Revision: https://reviews.llvm.org/D34475

llvm-svn: 308218
2017-07-17 20:49:45 +00:00
Ulrich Weigand 76976a7920 [SystemZ] Add support for IBM z14 processor (2/3)
This patch extends the -fzvector language feature to enable the new
"vector float" data type when compiling at -march=z14.  This matches
the updated extension definition implemented by other compilers for
the platform, which is indicated to applications by pre-defining
__VEC__ to 10302 (instead of 10301).

llvm-svn: 308198
2017-07-17 17:46:47 +00:00
Ulrich Weigand cac24ab04c [SystemZ] Add support for IBM z14 processor (1/3)
This patch series adds support for the IBM z14 processor.  This part includes:
- Basic support for the new processor and its features.
- Support for low-level builtins mapped to new LLVM intrinsics.

Support for the -fzvector extension to vector float and the new
high-level vector intrinsics is provided by separate patches.

llvm-svn: 308197
2017-07-17 17:45:57 +00:00
Brad Smith 733fe193d3 Enable TLS support on OpenBSD, but default to the emulatated TLS model.
llvm-svn: 308155
2017-07-17 00:49:31 +00:00
Craig Topper 3544b3e501 [X86] Add 'movbe' to btver2 CPU.
This probably doesn't change anything because the frotend doesn't do anything with this feature and the backend will infer from the cpu string. So this is just for consistency with other cpus that support movbe.

llvm-svn: 308002
2017-07-14 06:36:17 +00:00
Amara Emerson ebe02904d4 [AArch64] Add support for handling the +sve target feature.
This also adds the appropriate predefine for SVE if enabled.

Differential Revision: https://reviews.llvm.org/D35118

llvm-svn: 307919
2017-07-13 15:36:01 +00:00
Simon Atanasyan 3606ebf6d6 [mips] Create the correct profiling symbol on Linux MIPS
llvm-svn: 307627
2017-07-11 06:19:01 +00:00
Yaxun Liu cbf647cc3a CodeGen: Fix address space of global variable
Certain targets (e.g. amdgcn) require global variable to stay in global or constant address
space. In C or C++ global variables are emitted in the default (generic) address space.
This patch introduces virtual functions TargetCodeGenInfo::getGlobalVarAddressSpace
and TargetInfo::getConstantAddressSpace to handle this in a general approach.

It only affects IR generated for amdgcn target.

Differential Revision: https://reviews.llvm.org/D33842

llvm-svn: 307470
2017-07-08 13:24:52 +00:00
Craig Topper 61395176f9 [X86] Replace 'fallthrough' comments with LLVM_FALLTHROUGH.
llvm-svn: 307420
2017-07-07 18:41:09 +00:00
Sjoerd Meijer 98ee78578b This reverts r305820 (ARMv.2-A FP16 vector intrinsics) because it shows
problems in testing, see comments in D34161 for some more details.
A fix is in progres in D35011, but a revert seems better now as the fix will
probably take some more time to land.

llvm-svn: 307277
2017-07-06 16:37:31 +00:00
Ulrich Weigand 6d6c4808ef [SystemZ] Simplify handling of ISA revisions
This moves determination of the ISA revision from the CPU name to
one single place, removing a bunch of duplicated code.  It also
makes the supported ISA revisions available as feature strings.

No functional change.

llvm-svn: 307156
2017-07-05 13:19:47 +00:00
Yaxun Liu 25d1b4341f [AMDGPU] Fix size and alignment of size_t and pointer types
Differential Revision: https://reviews.llvm.org/D34995

llvm-svn: 307121
2017-07-05 04:58:24 +00:00
Yaxun Liu 3ba4a720ad [AMDGPU] Fix regressions on mesa/clover with libclc due to address space
Currently AMDGPUTargetInfo does not initialize AddrSpaceMap in constructor, which causes regressions in mesa/clover with libclc.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D34987

llvm-svn: 307105
2017-07-04 19:57:18 +00:00
Hiroshi Inoue 3170de0eb8 fix trivial typos; NFC
llvm-svn: 306954
2017-07-01 08:46:43 +00:00
Yuka Takahashi dc771509a4 Changed Opts.EABIVersion type string to llvm::EABI enum class
Summary:
Changed EABIVersion type from string to llvm::EABI.
It seems it was just a typo and this is intended implementation.

Differential Revision: https://reviews.llvm.org/D34595

llvm-svn: 306953
2017-07-01 07:57:23 +00:00