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92 Commits

Author SHA1 Message Date
Evan Cheng 6222cf2a36 Silly bug 
llvm-svn: 27719
 2006-04-15 05:37:34 +00:00
Evan Cheng 00a5b3d9d3 Some clean up 
llvm-svn: 27715
 2006-04-14 23:32:40 +00:00
Evan Cheng 5d247f81c1 Last few SSE3 intrinsics. 
llvm-svn: 27711
 2006-04-14 21:59:03 +00:00
Evan Cheng 3bd605397b Misc. SSE2 intrinsics: clflush, lfench, mfence 
llvm-svn: 27699
 2006-04-14 07:43:12 +00:00
Evan Cheng eb0063a34f pcmpeq* and pcmpgt* intrinsics. 
llvm-svn: 27685
 2006-04-14 01:39:53 +00:00
Evan Cheng 16287444ff psll*, psrl*, and psra* intrinsics. 
llvm-svn: 27684
 2006-04-14 00:14:05 +00:00
Evan Cheng a84319719c Doh. PANDrm, etc. are not commutable. 
llvm-svn: 27668
 2006-04-13 18:11:28 +00:00
Evan Cheng ed3996743f psad, pmax, pmin intrinsics. 
llvm-svn: 27647
 2006-04-13 06:11:45 +00:00
Evan Cheng 58dad55959 Various SSE2 packed integer intrinsics: pmulhuw, pavgw, etc. 
llvm-svn: 27645
 2006-04-13 05:24:54 +00:00
Evan Cheng b3fe00bdc6 padds{b|w}, paddus{b|w}, psubs{b|w}, psubus{b|w} intrinsics. 
llvm-svn: 27639
 2006-04-13 00:43:35 +00:00
Evan Cheng 0aab735a1a Naming inconsistency. 
llvm-svn: 27638
 2006-04-13 00:00:23 +00:00
Evan Cheng c88afc36a9 SSE / SSE2 conversion intrinsics. 
llvm-svn: 27637
 2006-04-12 23:42:44 +00:00
Evan Cheng 92232307d0 All "integer" logical ops (pand, por, pxor) are now promoted to v2i64. 
Clean up and fix various logical ops issues.

llvm-svn: 27633
 2006-04-12 21:21:57 +00:00
Evan Cheng e2157c6e41 Promote v4i32, v8i16, v16i8 load to v2i64 load. 
llvm-svn: 27612
 2006-04-12 17:12:36 +00:00
Evan Cheng 29be057d92 Various SSE2 conversion intrinsics 
llvm-svn: 27603
 2006-04-12 05:20:24 +00:00
Evan Cheng 70c74a3ced Added __builtin_ia32_storelv4si, __builtin_ia32_movqv4si, 
__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.

llvm-svn: 27599
 2006-04-11 22:28:25 +00:00
Evan Cheng 6b60357f4a gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support 
later.

llvm-svn: 27591
 2006-04-11 18:04:57 +00:00
Evan Cheng 6ea715af28 Misc. intrinsics. 
llvm-svn: 27590
 2006-04-11 17:35:57 +00:00
Evan Cheng 09a956271a movnt* and maskmovdqu intrinsics 
llvm-svn: 27587
 2006-04-11 06:57:30 +00:00
Evan Cheng 12ba3e23d0 Added support for _mm_move_ss and _mm_move_sd. 
llvm-svn: 27575
 2006-04-11 00:19:04 +00:00
Evan Cheng f8ac02283c Remove some bogus patterns; clean up. 
llvm-svn: 27569
 2006-04-10 22:35:16 +00:00
Evan Cheng 76112c3cb8 Added some missing shuffle patterns. 
llvm-svn: 27564
 2006-04-10 21:42:19 +00:00
Evan Cheng 395fa3d2a6 movups / movupd 
llvm-svn: 27562
 2006-04-10 21:11:06 +00:00
Evan Cheng 617a6a812e Conditional move of vector types. 
llvm-svn: 27556
 2006-04-10 07:23:14 +00:00
Evan Cheng 0df9c9f57d ldmxcsr and stmxcsr. 
llvm-svn: 27506
 2006-04-08 00:47:44 +00:00
Evan Cheng aa18a52545 Added patterns for MOVHPSmr and MOVLPSmr. 
llvm-svn: 27497
 2006-04-07 21:20:58 +00:00
Evan Cheng d8e1a01be6 A MOVPS2SSmr, i.e. _mm_store_ss, encoding bug. 
Also MOVPDI2DIrr.

llvm-svn: 27476
 2006-04-06 23:53:29 +00:00
Evan Cheng c995b45f67 - movlp{s|d} and movhp{s|d} support. 
- Normalize shuffle nodes so result vector lower half elements come from the
  first vector, the rest come from the second vector. (Except for the
  exceptions :-).
- Other minor fixes.

llvm-svn: 27474
 2006-04-06 23:23:56 +00:00
Evan Cheng 695e45c252 POR encoded as PAND, yikes. 
llvm-svn: 27446
 2006-04-06 01:49:20 +00:00
Evan Cheng 780382946e Support for comi / ucomi intrinsics. 
llvm-svn: 27444
 2006-04-05 23:38:46 +00:00
Evan Cheng f3b52c84ea Handle canonical form of e.g. 
vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>

This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.

It would match a {p}unpckl on x86.

llvm-svn: 27437
 2006-04-05 07:20:06 +00:00
Evan Cheng 011c23d9d3 Added pslldq and psrldq. 
llvm-svn: 27412
 2006-04-04 21:49:39 +00:00
Evan Cheng 8f3b6b8d8a Minor fixes + naming changes. 
llvm-svn: 27410
 2006-04-04 19:12:30 +00:00
Evan Cheng 802b35c339 PSHUF* encoding bugs. 
llvm-svn: 27405
 2006-04-04 18:40:36 +00:00
Evan Cheng e91e3bd874 cmpps / cmppd encoding bug 
llvm-svn: 27393
 2006-04-04 03:04:07 +00:00
Evan Cheng dd2eb27d6d Compact some intrinsic definitions. 
llvm-svn: 27388
 2006-04-04 00:10:53 +00:00
Evan Cheng 0ef83c83e1 Some SSE1 intrinsics: min, max, sqrt, etc. 
llvm-svn: 27384
 2006-04-03 23:49:17 +00:00
Evan Cheng b64827e662 Use movlpd to: store lower f64 extracted from v2f64. 
Use movhpd to: store upper f64 extracted from v2f64.

llvm-svn: 27382
 2006-04-03 22:30:54 +00:00
Evan Cheng ebf1006d16 - More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc. 
- Some bug fixes and naming inconsistency fixes.

llvm-svn: 27377
 2006-04-03 20:53:28 +00:00
Evan Cheng 5fd7c69473 Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed 
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.

llvm-svn: 27314
 2006-03-31 21:55:24 +00:00
Evan Cheng 747e29ef0b Added support for SSE3 horizontal ops: haddp{s|d} and hsub{s|d}. 
llvm-svn: 27310
 2006-03-31 21:29:33 +00:00
Evan Cheng cbffa4656b Add support to use pextrw and pinsrw to extract and insert a word element 
from a 128-bit vector.

llvm-svn: 27304
 2006-03-31 19:22:53 +00:00
Evan Cheng 7e2ff11a42 Make sure all possible shuffles are matched. 
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.

llvm-svn: 27259
 2006-03-30 19:54:57 +00:00
Evan Cheng dd487d865b More logical ops patterns 
llvm-svn: 27257
 2006-03-30 07:33:32 +00:00
Evan Cheng c58ef7deeb Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics 
llvm-svn: 27256
 2006-03-30 06:21:22 +00:00
Evan Cheng 593310016d Add 128-bit pmovmskb intrinsic support. 
llvm-svn: 27255
 2006-03-30 00:33:26 +00:00
Evan Cheng c5cf9bba05 Change SSE pack operation definitions to fit what the intrinsics expected. 
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.

llvm-svn: 27254
 2006-03-29 23:53:14 +00:00
Evan Cheng b7fedffc78 - Added some SSE2 128-bit packed integer ops. 
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252
 2006-03-29 23:07:14 +00:00
Evan Cheng acc336475e Need to special case splat after all. Make the second operand of splat 
vector_shuffle undef.

llvm-svn: 27250
 2006-03-29 19:02:40 +00:00
Evan Cheng 3cf95747c7 Floating point logical operation patterns should match bit_convert. Or else 
integer vector logical operations would match andp{s|d} instead of pand.

llvm-svn: 27248
 2006-03-29 18:47:40 +00:00