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19899 Commits

Author SHA1 Message Date
Evan Cheng aa93ceb164 Add missing avx pattern. 
llvm-svn: 145272
 2011-11-28 20:27:23 +00:00
Duncan Sands 12330650f8 Silence wrong warnings from GCC about variables possibly being used 
uninitialized: GCC doesn't understand that the variables are only used
if !UseImm, in which case they have been initialized.

llvm-svn: 145239
 2011-11-28 10:31:27 +00:00
Craig Topper 818a983e93 Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge VPERMILPS/VPERMILPD detection since they are pretty similar. 
llvm-svn: 145238
 2011-11-28 10:14:51 +00:00
Craig Topper b0456936da Make isCommutedVSHUFP more like the way isCommutedSHUFP is handled. 
llvm-svn: 145218
 2011-11-28 01:14:24 +00:00
Craig Topper 79ee88a511 Merge detecting and handling for VSHUFPSY and VSHUFPDY since a lot of the code was similar for both. 
llvm-svn: 145199
 2011-11-27 21:41:12 +00:00
Wesley Peck 97b3da5433 Add several new instructions supported by the latest MicroBlaze. 
These instructions are not generated by the backend yet, this will come in a later commit.

llvm-svn: 145161
 2011-11-27 05:16:58 +00:00
Wesley Peck d2e2e1782f Optimize comparison against 0 in conditional instructions. 
Fix a couple of 80-column violations.

llvm-svn: 145159
 2011-11-27 01:36:20 +00:00
Benjamin Kramer 7ba71be392 Move code into anonymous namespaces. 
llvm-svn: 145154
 2011-11-26 23:01:57 +00:00
Craig Topper 51280d565b Merge 128-bit and 256-bit X86ISD node types for VPERMILPS and VPERMILPD. Simplify some shuffle lowering code since V1 can never be UNDEF due to canonalizing that occurs when shuffle nodes are created. 
llvm-svn: 145153
 2011-11-26 22:55:48 +00:00
Wesley Peck 69d5040485 Rename a couple of options and fix some simple typos. 
llvm-svn: 145152
 2011-11-26 21:50:38 +00:00
Craig Topper 7704bd7ac3 Collapse X86ISD node types for PUNPCKH*, PUNPCKL*, UNPCKLP*, and UNPCKHP* to not be type specific. Now we just have integer high and low and floating point high and low. Pattern matching will choose the correct instruction based on the vector type. 
llvm-svn: 145148
 2011-11-26 20:47:44 +00:00
Bruno Cardoso Lopes 0f9a1f5e6c This patch contains support for encoding FMA4 instructions and 
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.

Patch by Jan Sjodin

llvm-svn: 145133
 2011-11-25 19:33:42 +00:00
NAKAMURA Takumi 989eaf6e3f ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build. 
llvm-svn: 145129
 2011-11-25 09:19:57 +00:00
Craig Topper d65a444478 Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64. 
llvm-svn: 145126
 2011-11-24 22:57:10 +00:00
Craig Topper d26466748b Remove AVX2 specific X86ISD node types for PUNPCKH/L and instead just reuse the 128-bit versions and let the vector type distinguish. 
llvm-svn: 145125
 2011-11-24 22:20:08 +00:00
Benjamin Kramer 651db37352 X86: alias cqo to cqto. 
llvm-svn: 145121
 2011-11-24 12:02:46 +00:00
Akira Hatanaka 049e9e4d22 This patch makes the following changes necessary for MIPS' direct code emission. 
- lower unaligned loads/stores.
- encode the size operand of instructions INS and EXT.
- emit relocation information needed for JAL (jump-and-link).  

llvm-svn: 145113
 2011-11-23 22:19:28 +00:00
Akira Hatanaka f5ddf13f79 This patch addresses gp relative fixups/relocations for jump tables. 
llvm-svn: 145112
 2011-11-23 22:18:04 +00:00
Benjamin Kramer ebcb451874 X86: Use btq for bit tests if the immediate can't be encoded in 32 bits. 
Before:
	movabsq	$4294967296, %rax       ## encoding: [0x48,0xb8,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00]
	testq	%rax, %rdi              ## encoding: [0x48,0x85,0xf8]
	jne	LBB0_2                  ## encoding: [0x75,A]

After:
	btq	$32, %rdi               ## encoding: [0x48,0x0f,0xba,0xe7,0x20]
	jb	LBB0_2                  ## encoding: [0x72,A]

btq is usually slower than testq because it doesn't fuse with the jump, but here we're better off
saving one register and a giant movabsq.

llvm-svn: 145103
 2011-11-23 13:54:17 +00:00
Elena Demikhovsky 779ba6d7b7 I added several lines in X86 code generator that allow to choose 
VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask.

The patch was reviewed by Bruno.

llvm-svn: 145099
 2011-11-23 10:23:16 +00:00
Jakob Stoklund Olesen 02845410f9 Fix PR11422. 
This was a bug in keeping track of the available domains when merging
domain values.

The wrong domain mask caused ExecutionDepsFix to try to move VANDPSYrr
to the integer domain which is only available in AVX2.

Also add an assertion to catch future attempts at emitting AVX2
instructions.

llvm-svn: 145096
 2011-11-23 04:03:08 +00:00
Hal Finkel 6f0ae783fe add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern 
llvm-svn: 145065
 2011-11-22 16:21:04 +00:00
Craig Topper 83c4592619 More fixes to the X86InstComments for shuffle instructions. In particular add AVX flavors of many instructions and fix the destination operand for some of the existing AVX entries. 
llvm-svn: 145063
 2011-11-22 14:27:57 +00:00
Craig Topper ccb7097509 Fix shuffle decoding logic to handle UNPCKLPS/UNPCKLPD on 256-bit vectors correctly. Add support for decoding UNPCKHPS/UNPCKHPD for AVX 128-bit and 256-bit forms. 
llvm-svn: 145055
 2011-11-22 01:57:35 +00:00
Craig Topper f563977795 Add methods for querying minimum SSE version along with AVX. Simplifies all the places that had to check a version of SSE and AVX. 
llvm-svn: 145053
 2011-11-22 00:44:41 +00:00
Craig Topper 6270d072c5 Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled. 
llvm-svn: 145028
 2011-11-21 08:26:50 +00:00
Craig Topper 669199ca94 Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if AVX2 is enabled. 
llvm-svn: 145026
 2011-11-21 06:57:39 +00:00
Craig Topper a065238c6e Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and use AVX2 shifts when AVX2 is enabled. 
llvm-svn: 145022
 2011-11-21 01:12:36 +00:00
Craig Topper e79761df73 Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine. 
llvm-svn: 145005
 2011-11-20 00:12:05 +00:00
Craig Topper a3a6583694 Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled. 
llvm-svn: 145004
 2011-11-19 22:34:59 +00:00
Craig Topper bac86038ac Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns. 
llvm-svn: 145003
 2011-11-19 21:01:54 +00:00
Craig Topper 3af6ae089f Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns. 
llvm-svn: 144999
 2011-11-19 17:46:46 +00:00
Craig Topper f984efbfce Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors. 
llvm-svn: 144989
 2011-11-19 09:02:40 +00:00
Craig Topper 81390be00f Collapse X86 PSIGNB/PSIGNW/PSIGND node types. 
llvm-svn: 144988
 2011-11-19 07:33:10 +00:00
Craig Topper de6b73bb4d Extend VPBLENDVB and VPSIGN lowering to work for AVX2. 
llvm-svn: 144987
 2011-11-19 07:07:26 +00:00
Craig Topper 66e2b5a61e Remove unused parameters from the AVX maskmov classes. 
llvm-svn: 144985
 2011-11-19 04:49:22 +00:00
Nadav Rotem 1ec141d0f9 Add AVX2 vpbroadcast support 
llvm-svn: 144967
 2011-11-18 02:49:55 +00:00
Chad Rosier ee93ff736a Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code. 
llvm-svn: 144959
 2011-11-18 01:17:34 +00:00
Chad Rosier 0eff3e5c21 Add TODO comment. 
llvm-svn: 144920
 2011-11-17 21:46:13 +00:00
Craig Topper f41e1d0246 Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments. 
llvm-svn: 144896
 2011-11-17 07:49:38 +00:00
Chad Rosier 15b2498e88 Dead code. 
llvm-svn: 144888
 2011-11-17 07:24:49 +00:00
Craig Topper f17b600577 Remove seemingly unnecessary duplicate VROUND definitions. 
llvm-svn: 144885
 2011-11-17 07:04:00 +00:00
Eli Friedman 489c0ff4a4 Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom 
names for fwrite and fputs.

Fixes <rdar://problem/9815881>.

llvm-svn: 144876
 2011-11-17 01:27:36 +00:00
Chad Rosier ce619ddfc5 Don't unconditionally set the kill flag. 
rdar://10456186

llvm-svn: 144872
 2011-11-17 01:16:53 +00:00
Eli Friedman 20439a42b0 Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing. 
llvm-svn: 144867
 2011-11-17 00:21:52 +00:00
Jim Grosbach d3f02cbce9 Generalize the fixup info for ARM mode. 
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

llvm-svn: 144852
 2011-11-16 22:48:37 +00:00
Akira Hatanaka b31abde0f3 Lower 64-bit constant pool node. 
llvm-svn: 144849
 2011-11-16 22:44:38 +00:00
Akira Hatanaka eb42071721 Lower 64-bit block address. 
llvm-svn: 144847
 2011-11-16 22:42:10 +00:00
Jim Grosbach 7ccdb7c0ae Fix encoding of NOP used for padding in ARM mode .align. 
llvm-svn: 144842
 2011-11-16 22:40:25 +00:00
Akira Hatanaka 7b8547c4d0 Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool 
nodes.

llvm-svn: 144841
 2011-11-16 22:39:56 +00:00