Commit Graph

52554 Commits

Author SHA1 Message Date
Chris Lattner 33633a90a0 fix a bug I introduced in r148929, this is not a splat!
Thanks to Eli for noticing.

llvm-svn: 148947
2012-01-25 09:56:22 +00:00
Nick Lewycky 3c3feaf40c Gracefully degrade precision in branch probability numbers.
llvm-svn: 148946
2012-01-25 09:43:14 +00:00
Nick Lewycky 70d50ee8fb Support pointer comparisons against constants, when looking at the inline-cost
savings from a pointer argument becoming an alloca. Sometimes callees will even
compare a pointer to null and then branch to an otherwise unreachable block!
Detect these cases and compute the number of saved instructions, instead of
bailing out and reporting no savings.

llvm-svn: 148941
2012-01-25 08:27:40 +00:00
Chris Lattner 6705883ad8 use Constant::getAggregateElement to simplify a bunch of code.
llvm-svn: 148934
2012-01-25 06:48:06 +00:00
Craig Topper 7834900950 Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.
llvm-svn: 148933
2012-01-25 06:43:11 +00:00
Chris Lattner 7e683d10a8 constify some methods and add a new Constant::getAggregateElement
helper method for the common operation of extracting an element
out of a constant aggregate.

llvm-svn: 148931
2012-01-25 06:16:32 +00:00
Chris Lattner 47a86bdbe2 use ConstantVector::getSplat in a few places.
llvm-svn: 148929
2012-01-25 06:02:56 +00:00
Craig Topper ce4f9c5668 Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary.
llvm-svn: 148927
2012-01-25 05:37:32 +00:00
Chris Lattner e9eed29b5b reapply r148901 with a crucial fix.
"Introduce a new ConstantVector::getSplat constructor function to 
simplify a really common case."

llvm-svn: 148924
2012-01-25 05:19:54 +00:00
Craig Topper 5bcf070e68 Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago.
llvm-svn: 148922
2012-01-25 04:42:03 +00:00
Akira Hatanaka 012f041bce Mark 64-bit register RA_64 unused too.
llvm-svn: 148918
2012-01-25 04:19:22 +00:00
Akira Hatanaka 01d3c42f90 Modify MipsFrameLowering::emitPrologue and emitEpilogue.
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit.
- Change the types of variables so that they are sufficiently large to handle
  64-bit pointers.
- Emit instructions to set register $28 in a function prologue after
  instructions which store callee-saved registers have been emitted. 
 

llvm-svn: 148917
2012-01-25 04:12:04 +00:00
Akira Hatanaka d1d4b3efcf Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate to
expand offsets that do not fit in the 16-bit immediate field of load and store
instructions. Also change the types of variables so that they are sufficiently
large to handle 64-bit pointers.

llvm-svn: 148916
2012-01-25 03:55:10 +00:00
Craig Topper 3ad5bc019a Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions.
llvm-svn: 148914
2012-01-25 03:52:09 +00:00
NAKAMURA Takumi 6c421ea484 MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc.
inttypes.h is not supplied in msvc.

llvm-svn: 148912
2012-01-25 03:34:41 +00:00
Nick Lewycky ff50962534 Fix assert("msg"). Fix unused-variable warnings complaining about VT used only
in asserts.

llvm-svn: 148910
2012-01-25 03:20:12 +00:00
NAKAMURA Takumi 96a21dcea3 Target/Mips: Unbreak CMake build.
llvm-svn: 148909
2012-01-25 03:15:46 +00:00
Akira Hatanaka 86d5fadd57 Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added.
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.

llvm-svn: 148908
2012-01-25 03:01:35 +00:00
Argyrios Kyrtzidis 939b7a0b7c Revert r148901 because it crashes llvm tests.
Original log:
    Introduce a new ConstantVector::getSplat constructor function to
    simplify a really common case.

llvm-svn: 148906
2012-01-25 02:42:41 +00:00
Chris Lattner 9fe7dd872b Introduce a new ConstantVector::getSplat constructor function to
simplify a really common case.

llvm-svn: 148901
2012-01-25 01:53:58 +00:00
Akira Hatanaka ff36fd3de3 Add class MipsAnalyzeImmediate which comes up with an instruction sequence to
load an immediate. 

llvm-svn: 148900
2012-01-25 01:43:36 +00:00
Chris Lattner 8a3df5495a Remove the Type::getNumElements() method, which is only called in 4 places,
did something extremely surprising, and shadowed actually useful 
implementations that had completely different behavior.

llvm-svn: 148898
2012-01-25 01:32:59 +00:00
Chris Lattner 9be59599b3 Use the right method to get the # elements in a CDS.
llvm-svn: 148897
2012-01-25 01:27:20 +00:00
Jim Grosbach 086cbfac7d NEON VLD4(all lanes) assembly parsing and encoding.
llvm-svn: 148884
2012-01-25 00:01:08 +00:00
Jim Grosbach ccb6d55dae Tidy up. Rename VLD4DUP patterns for consistency.
llvm-svn: 148883
2012-01-24 23:47:07 +00:00
Jim Grosbach b78403ce48 NEON VLD3(all lanes) assembly parsing and encoding.
llvm-svn: 148882
2012-01-24 23:47:04 +00:00
Jakob Stoklund Olesen 1b8e437ab6 Set correct <def,undef> flags when lowering REG_SEQUENCE.
A REG_SEQUENCE instruction is lowered into a sequence of partial defs:

  %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0
  %vreg7:ssub_1<def> = COPY %vreg2
  %vreg7:ssub_2<def> = COPY %vreg2
  %vreg7:ssub_3<def> = COPY %vreg2

The first def needs an <undef> flag to indicate it is the beginning of
the live range, while the other defs are read-modify-write.  Previously,
we depended on LiveIntervalAnalysis to notice and fix the missing
<def,undef>, but that solution was never robust, it was causing problems
with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE
instructions.

This fixes PR11841.

llvm-svn: 148879
2012-01-24 23:28:42 +00:00
Jakob Stoklund Olesen 66ef9ad33f Use the standard MachineFunction::print() after SlotIndexes.
llvm-svn: 148878
2012-01-24 23:28:38 +00:00
Akira Hatanaka d7970f9e4b Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,
which is what N32/64 does.

llvm-svn: 148875
2012-01-24 23:18:43 +00:00
Akira Hatanaka 7e6c195c11 Pass CCState by reference.
llvm-svn: 148871
2012-01-24 22:07:36 +00:00
Akira Hatanaka 77dbd786c8 Pattern for f32 to i64 conversion.
llvm-svn: 148869
2012-01-24 22:05:25 +00:00
Jim Grosbach 35bc8f9159 ARM Darwin symbol ref differences w/o subsection-via-symbols.
When not using subsections via symbols, the assembler can resolve
symbol differences (including pcrel references) to non-local
labels at assembly time, not just those in the same atom.

llvm-svn: 148865
2012-01-24 21:45:25 +00:00
Devang Patel a410ed3ced Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
llvm-svn: 148864
2012-01-24 21:43:36 +00:00
Akira Hatanaka 9f7ec1538f 64-bit sign extension in register instructions.
llvm-svn: 148862
2012-01-24 21:41:09 +00:00
Matt Beaumont-Gay 88297ef665 Sink assert-only variables into the asserts
llvm-svn: 148849
2012-01-24 19:43:30 +00:00
Kostya Serebryany c11d1dd133 [asan] enable asan only for the functions that have Attribute::AddressSafety
llvm-svn: 148846
2012-01-24 19:34:43 +00:00
Jim Grosbach 8e2722cdb0 NEON VST4(one lane) assembly parsing and encoding.
llvm-svn: 148836
2012-01-24 18:53:13 +00:00
Owen Anderson d845d9d9e9 Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand.
llvm-svn: 148833
2012-01-24 18:37:29 +00:00
Jim Grosbach 14952a0e32 NEON VLD4(one lane) assembly parsing and encoding.
llvm-svn: 148832
2012-01-24 18:37:25 +00:00
Jakob Stoklund Olesen 5b9deabae8 Fix old doxygen comment.
llvm-svn: 148825
2012-01-24 18:09:18 +00:00
Jim Grosbach 3cfef8d467 NEON Two-operand assembly aliases for VSRA.
llvm-svn: 148821
2012-01-24 17:55:36 +00:00
Jim Grosbach 7ae12cc546 NEON Two-operand assembly aliases for VSLI.
llvm-svn: 148819
2012-01-24 17:49:15 +00:00
Jim Grosbach 7b6f0f67aa NEON Two-operand assembly aliases for VSRI.
llvm-svn: 148818
2012-01-24 17:46:58 +00:00
Jim Grosbach 681db34eae NEON add correct predicates for some asm aliases.
llvm-svn: 148815
2012-01-24 17:23:29 +00:00
Chris Lattner a0d01ff567 basic instcombine support for CDS.
llvm-svn: 148806
2012-01-24 14:31:22 +00:00
Chris Lattner 139822fc83 C++, CBE, and TLOF support for ConstantDataSequential
llvm-svn: 148805
2012-01-24 14:17:05 +00:00
Chris Lattner 2068393140 Rearrange argument order of ::get methods so that LLVMContext comes first,
add a ConstantDataArray::getString method that corresponds to the (to be
removed) StringRef version of ConstantArray::get, but is dramatically more 
efficient.

llvm-svn: 148804
2012-01-24 14:04:40 +00:00
Elena Demikhovsky 0b0c5d8c4c ZERO_EXTEND operation is optimized for AVX.
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.

llvm-svn: 148803
2012-01-24 13:54:13 +00:00
Chris Lattner 00245f420a add more support for ConstantDataSequential
llvm-svn: 148802
2012-01-24 13:41:11 +00:00
Evgeniy Stepanov 33a7e2f2a1 An option to selectively enable part of ARM EHABI support.
This change adds an new option --arm-enable-ehabi-descriptors that
enables emitting unwinding descriptors. This provides a mode with a
working backtrace() without the (currently broken) exception support.

llvm-svn: 148800
2012-01-24 13:05:33 +00:00
Benjamin Kramer 8aefffca4c Bit pack DIE structures better.
16 bits are sufficient to store attributes, tags and forms.

llvm-svn: 148799
2012-01-24 12:08:28 +00:00
Eric Christopher 3e8ccc2000 Remove generation of DW_AT_sibling. Nothing as far as I can tell uses it.
Saves about 1.5% on debug info size.

rdar://10278198

llvm-svn: 148794
2012-01-24 09:43:28 +00:00
Chris Lattner 5d4497bf4a Add AsmPrinter (aka MCLowering) support for ConstantDataSequential,
and clean up some other misc stuff.  Unlike ConstantArray, we will
prefer to emit .fill directives for "String" arrays that all have
the same value, since they are denser than emitting a .ascii

llvm-svn: 148793
2012-01-24 09:31:43 +00:00
Chris Lattner 5dd4d87ce0 Add various "string" methods to ConstantDataSequential, which have the
same semantics as ConstantArray's but much more efficient because they
don't have to return std::string's.  The ConstantArray methods will
eventually be removed.

llvm-svn: 148792
2012-01-24 09:01:07 +00:00
Chris Lattner f7eb543380 teach valuetracking about ConstantDataSequential
llvm-svn: 148790
2012-01-24 07:54:10 +00:00
Chris Lattner e166a8548f switch SCEV to use the new ConstantFoldLoadThroughGEPIndices function
instead of its own hard coded thing, allowing it to handle 
ConstantDataSequential and fixing some obscure bugs (e.g. it would
previously crash on a CAZ of vector type).

llvm-svn: 148788
2012-01-24 05:49:24 +00:00
Chris Lattner f488b35826 Split the interesting bits of ConstantFoldLoadThroughGEPConstantExpr
out into a new ConstantFoldLoadThroughGEPIndices (more useful) function
and rewrite it to be simpler, more efficient, and to handle the new
ConstantDataSequential type.

Enhance ConstantFoldLoadFromConstPtr to handle ConstantDataSequential.

llvm-svn: 148786
2012-01-24 05:43:50 +00:00
Chris Lattner 030af79b14 Add some accessor methods to CAZ and UndefValue that help simplify clients.
Make some CDS methods public.

llvm-svn: 148785
2012-01-24 05:42:11 +00:00
Anton Korobeynikov 3cad0c21ed Use correct register class for am2offset register operands.
This pacifies machine verifier

llvm-svn: 148782
2012-01-24 04:58:56 +00:00
Jakob Stoklund Olesen c46534a0cd Preserve <def,undef> flags in CoalesceExtSubRegs.
This won't have an effect until EliminateRegSequences() starts setting
the undef flags.

llvm-svn: 148779
2012-01-24 04:44:01 +00:00
Chris Lattner e4f3f102c2 implement the ConstantDataSequential accessor methods.
No need for 'getOperand' :)

llvm-svn: 148778
2012-01-24 04:43:41 +00:00
Craig Topper 0d8e67aebd Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types.
llvm-svn: 148771
2012-01-24 03:03:17 +00:00
Jim Grosbach da70eac268 NEON VST4(multiple 4 element structures) assembly parsing.
llvm-svn: 148764
2012-01-24 00:58:13 +00:00
Jim Grosbach ed561fc850 NEON VLD4(multiple 4 element structures) assembly parsing.
llvm-svn: 148762
2012-01-24 00:43:17 +00:00
Jim Grosbach 1e946a4f91 Tidy up. Remove some vertical space for readability.
llvm-svn: 148761
2012-01-24 00:43:12 +00:00
Chandler Carruth ed975232bc Revert r148686 (and r148694, a fix to it) due to a serious layering
violation -- MC cannot depend on CodeGen.

Specifically, the MCTargetDesc component of each target is actually
a subcomponent of the MC library. As such, it cannot depend on the
target-independent code generator, because MC itself cannot depend on
the target-independent code generator. This change moved a flag from the
ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in
ARMException.cpp, leaving behind an 'extern' to refer back to it. That
layering order isn't viable givin the constraints outlined above.
Commandline flags are designed to be static specifically to avoid these
types of bugs.

Fixing this is likely going to require some non-trivial refactoring.

llvm-svn: 148759
2012-01-24 00:30:17 +00:00
Jim Grosbach 17bacab475 Fix typo.
llvm-svn: 148757
2012-01-24 00:12:39 +00:00
Jim Grosbach d3d36d9315 NEON VST3(single element from one lane) assembly parsing.
llvm-svn: 148755
2012-01-24 00:07:41 +00:00
Devang Patel eba7d3dba9 Fix typo.
llvm-svn: 148751
2012-01-23 23:56:33 +00:00
Jim Grosbach 1a74724fc9 NEON VST3(multiple 3-element structures) assembly parsing.
llvm-svn: 148748
2012-01-23 23:45:44 +00:00
Jim Grosbach ac2af3ffab NEON VLD3(multiple 3-element structures) assembly parsing.
llvm-svn: 148745
2012-01-23 23:20:46 +00:00
Anton Korobeynikov 820417af07 Add missed mayStore flag to STREXD / t2STREXD
llvm-svn: 148742
2012-01-23 22:57:52 +00:00
Chris Lattner 3756b91313 start the implementation of a new ConstantDataVector and ConstantDataArray
classes, per PR1324.  Not all of their helper functions are implemented,
nothing creates them, and the rest of the compiler doesn't handle them yet.

llvm-svn: 148741
2012-01-23 22:57:10 +00:00
Bill Wendling 11eeeff24f Remove extraneous ';'s.
llvm-svn: 148740
2012-01-23 22:55:02 +00:00
David Blaikie d3303ded75 Remove dead default.
llvm-svn: 148738
2012-01-23 22:37:11 +00:00
Devang Patel cf893a437e Intel syntax: Robustify parsing of memory operand's displacement experssion.
llvm-svn: 148737
2012-01-23 22:35:25 +00:00
Jim Grosbach a8b444b08b NEON VLD3 lane-indexed assembly parsing and encoding.
llvm-svn: 148734
2012-01-23 21:53:26 +00:00
Rafael Espindola 3c47e37387 Add support for .cfi_signal_frame. Fixes pr11762.
llvm-svn: 148733
2012-01-23 21:51:52 +00:00
Lang Hames 2f6377cafe copyImplicitOps is redundant here - the loop above already copies these ops.
llvm-svn: 148725
2012-01-23 21:15:01 +00:00
Jakob Stoklund Olesen 20948fab69 Fix PR11829. PostRA LICM was too aggressive.
This fixes a typo in r148589.

llvm-svn: 148724
2012-01-23 21:01:15 +00:00
Jakob Stoklund Olesen 9082353e3b Simplify debug output.
llvm-svn: 148723
2012-01-23 21:01:11 +00:00
Devang Patel e660fdd953 Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
llvm-svn: 148721
2012-01-23 20:20:06 +00:00
Jim Grosbach d28ef9ac46 Simplify some NEON assembly pseudo definitions.
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.

llvm-svn: 148718
2012-01-23 19:39:08 +00:00
Matt Beaumont-Gay 54db64e2e4 Silence warnings in -asserts build
llvm-svn: 148715
2012-01-23 18:46:04 +00:00
Devang Patel 880bc1644b Intel syntax: Parse segment registers.
llvm-svn: 148712
2012-01-23 18:31:58 +00:00
Chris Lattner c7f9fd4da8 convert CAZ, UndefValue, and CPN to use DenseMap's again, this time without
using OwningPtr.  OwningPtr would barf when the densemap had to reallocate,
which doesn't appear to happen on the regression test suite, but obviously
happens in real life :)

llvm-svn: 148700
2012-01-23 15:20:12 +00:00
Chris Lattner 962c272f95 revert r148691 and 148693
llvm-svn: 148698
2012-01-23 15:09:44 +00:00
Alexander Potapenko c94cf8faf6 Implemented AddressSanitizer::getPassName()
llvm-svn: 148697
2012-01-23 11:22:43 +00:00
NAKAMURA Takumi 28ea8f523b ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.
llvm-svn: 148694
2012-01-23 09:14:42 +00:00
Chris Lattner 4494e1ae25 switch UndefValue and ConstantPointerNull over to DenseMap's for uniquing.
llvm-svn: 148693
2012-01-23 08:52:32 +00:00
Chris Lattner 1910c9c3a0 Replace a use of ConstantUniqueMap for CAZ constants with a simple DenseMap.
Now that the type system rewrite has landed, there is no need for its
complexity and std::map'ness.

llvm-svn: 148691
2012-01-23 08:42:38 +00:00
Craig Topper edd1d0acfc Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns.
llvm-svn: 148687
2012-01-23 08:18:28 +00:00
Evgeniy Stepanov 482cdc4ebd An option to selectively enable parts of ARM EHABI support.
This change adds an new value to the --arm-enable-ehabi option that
disables emitting unwinding descriptors. This mode gives a working
backtrace() without the (currently broken) exception support.

llvm-svn: 148686
2012-01-23 07:57:39 +00:00
Craig Topper 6b90c5d03e Update more places to use target specific nodes for vector shifts instead of intrinsics.
llvm-svn: 148685
2012-01-23 06:46:22 +00:00
Craig Topper 5e80db4e4f Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed.
llvm-svn: 148684
2012-01-23 06:16:53 +00:00
Rafael Espindola 624e30894a Avoid using an invalidated iterator.
llvm-svn: 148681
2012-01-23 05:07:16 +00:00
Rafael Espindola abf456e320 The iteration order over a std::set<Module*> depends on the addresses of the
modules. Avoid that to make the order the linker sees the modules deterministic.

llvm-svn: 148676
2012-01-23 03:41:53 +00:00
Craig Topper 20c98df340 Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments.
llvm-svn: 148672
2012-01-23 00:06:44 +00:00
Nick Lewycky c31ceda7d9 Make Value::isDereferenceablePointer() handle unreachable code blocks. (This
returns false in the event the computation feeding into the pointer is
unreachable, which maybe ought to be true -- but this is at least consistent
with undef->isDereferenceablePointer().) Fixes PR11825!

llvm-svn: 148671
2012-01-23 00:05:17 +00:00
Craig Topper 0b7ad76bd0 Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching.
llvm-svn: 148670
2012-01-22 23:36:02 +00:00
Craig Topper bd4884371b Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.
llvm-svn: 148667
2012-01-22 22:42:16 +00:00
Nicolas Geoffray e197d943f3 Use Attributes::None instead of 0 after r148553 change on Attributes from unsigned to their own class.
llvm-svn: 148665
2012-01-22 20:05:26 +00:00
Craig Topper 094626414d Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead.
llvm-svn: 148664
2012-01-22 19:15:14 +00:00
Anton Korobeynikov 0251f20ad1 Add an option to disable buggy copy propagation pass
llvm-svn: 148662
2012-01-22 14:08:34 +00:00
Anton Korobeynikov 5482b9f535 Add fused multiple+add instructions from VFPv4.
Patch by Ana Pazos!

llvm-svn: 148658
2012-01-22 12:07:33 +00:00
Eli Bendersky bff72ba77e Remove trailing spaces
llvm-svn: 148654
2012-01-22 09:02:48 +00:00
Eli Bendersky c3c80f0986 Basic runtime dynamic loading capabilities added to ELFObjectFile, implemented
in a subclass named DyldELFObject. This class supports rebasing the object file
it represents by re-mapping section addresses to the actual memory addresses
the object was placed in. This is required for MC-JIT implementation on ELF with
debugging support.

Patch reviewed on llvm-commits.

Developed together with Ashok Thirumurthi and Andrew Kaylor.

llvm-svn: 148653
2012-01-22 09:01:03 +00:00
Eli Bendersky 058d647adf Split the lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h header to smaller logical headers.
ELF and MachO implementations of RuntimeDyldImpl go into their own header files now.

Reviewed on llvm-commits

llvm-svn: 148652
2012-01-22 07:05:02 +00:00
Craig Topper a4ed5246d8 Make code a little less verbose.
llvm-svn: 148651
2012-01-22 03:07:48 +00:00
Craig Topper cb3433cd58 Remove unused X86 ISD node type defines.
llvm-svn: 148644
2012-01-22 01:15:56 +00:00
Craig Topper 123adfa0f3 Move some vector shift patterns into their instruction definitions.
llvm-svn: 148643
2012-01-22 00:41:20 +00:00
Craig Topper dcaa5fbd08 Add memory patterns for some of the fp<->integer conversion instructions. Fold some patterns into instruction definitions.
llvm-svn: 148641
2012-01-21 18:37:15 +00:00
Benjamin Kramer 5cff13a3fb Remove unused variables.
llvm-svn: 148635
2012-01-21 10:42:44 +00:00
Craig Topper 39bc1e4d25 Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that.
llvm-svn: 148632
2012-01-21 08:49:33 +00:00
Evan Cheng 64a2beca52 Fix an obvious typo.
llvm-svn: 148622
2012-01-21 03:31:03 +00:00
Jakob Stoklund Olesen 8e3bb315d8 Handle register masks in LiveVariables.
A register mask operand kills any live physreg that isn't preserved.
Unlike an implicit-def operand, the clobbered physregs are never live
afterwards.

This means LiveVariables has to track a much smaller number of live
physregs, and it should spend much less time in addRegisterDead().

llvm-svn: 148609
2012-01-21 00:58:53 +00:00
Jim Grosbach 8c592f13e3 RuntimeDyld alignment adjustment from MachO file.
The MachO file stores section alignment as log2(alignment-in-bytes). The
allocation routines want the raw alignment-in-bytes value, so adjust
for that.

llvm-svn: 148604
2012-01-21 00:21:53 +00:00
Jim Grosbach 78dcaed8ca Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.
llvm-svn: 148601
2012-01-21 00:07:56 +00:00
Jakob Stoklund Olesen 52ee45d64a Delete an unused member variable.
llvm-svn: 148594
2012-01-20 22:48:59 +00:00
Jim Grosbach 1dc4a77a23 Fix inverted condition.
llvm-svn: 148593
2012-01-20 22:44:03 +00:00
Devang Patel ce6a2ca8c8 Intel syntax: Robustify register parsing.
llvm-svn: 148591
2012-01-20 22:32:05 +00:00
Jakob Stoklund Olesen 6b17ef58a1 Support register masks in MachineLICM.
Only PostRA LICM is affected.

llvm-svn: 148589
2012-01-20 22:27:12 +00:00
Jakob Stoklund Olesen 58614f2f5a Handle register masks in DeadMachineInstructionElim.
Don't track live physregs that are clobbered by a register mask operand.

llvm-svn: 148588
2012-01-20 22:27:09 +00:00
David Blaikie 46a9f016c5 More dead code removal (using -Wunreachable-code)
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
Andrew Trick b9c822ab0b Handle a corner case with IV chain collection with bailout instead of assert.
Fixes PR11783: bad cast to AddRecExpr.

llvm-svn: 148572
2012-01-20 21:23:40 +00:00
Devang Patel d0930fff85 Intel syntax: Parse ... PTR [-8]
llvm-svn: 148570
2012-01-20 21:21:01 +00:00
Devang Patel f36613cb45 Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
llvm-svn: 148569
2012-01-20 21:14:06 +00:00
Bob Wilson 6c7aaec077 ARM vector any_extends need to be selected to vmovl. <rdar://problem/10723651>
We have patterns for vector sext and zext operations but were missing
anyext.  Without those patterns, codegen will fail when the selection DAG
has any_extend nodes.

llvm-svn: 148568
2012-01-20 20:59:56 +00:00
Jim Grosbach 91f5a3f253 TblGen diagnostic for mismatched template instantiation.
Providing a template argment to a non-templatized class was crashing
tblgen. Add a diagnostic.

For example,
$ cat bug.td
class A;

def B : A<0> {
}
$ llvm-tblgen bug.td
bug.td:3:11: error: template argument provided to non-template class
def B : A<0> {
          ^

llvm-svn: 148565
2012-01-20 20:02:39 +00:00
Jim Grosbach 90f5780fc1 VST2 four-register w/ update pseudos for fixed/register update.
rdar://10724489

llvm-svn: 148560
2012-01-20 19:16:00 +00:00
Jim Grosbach a9d36fbca7 NEON use vmov.i32 to splat some f32 values into vectors.
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.

rdar://10616677

llvm-svn: 148556
2012-01-20 18:09:51 +00:00
Kostya Serebryany a5054ad2f3 Extend Attributes to 64 bits
Problem: LLVM needs more function attributes than currently available (32 bits).
One such proposed attribute is "address_safety", which shows that a function is being checked for address safety (by AddressSanitizer, SAFECode, etc).

Solution:
- extend the Attributes from 32 bits to 64-bits
- wrap the object into a class so that unsigned is never erroneously used instead
- change "unsigned" to "Attributes" throughout the code, including one place in clang.
- the class has no "operator uint64 ()", but it has "uint64_t Raw() " to support packing/unpacking.
- the class has "safe operator bool()" to support the common idiom:  if (Attributes attr = getAttrs()) useAttrs(attr);
- The CTOR from uint64_t is marked explicit, so I had to add a few explicit CTOR calls
- Add the new attribute "address_safety". Doing it in the same commit to check that attributes beyond first 32 bits actually work.
- Some of the functions from the Attribute namespace are worth moving inside the class, but I'd prefer to have it as a separate commit.

Tested:
"make check" on Linux (32-bit and 64-bit) and Mac (10.6)
built/run spec CPU 2006 on Linux with clang -O2.


This change will break clang build in lib/CodeGen/CGCall.cpp.
The following patch will fix it.

llvm-svn: 148553
2012-01-20 17:56:17 +00:00
Benjamin Kramer d3309a3434 Add missing breaks to switch.
Found by the clang static analyzer.

llvm-svn: 148543
2012-01-20 14:42:37 +00:00
Benjamin Kramer 084b9f4134 Remove a bunch of unused variable assignments.
Found by the clang static analyzer.

llvm-svn: 148541
2012-01-20 14:42:32 +00:00
Benjamin Kramer fe4848b55d Remove obviously invalid early exit that prevented analyzing ConstantAggregateZeros.
Found by the clang static analyzer.

llvm-svn: 148540
2012-01-20 14:42:25 +00:00
Craig Topper a409479023 Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed.
llvm-svn: 148537
2012-01-20 09:29:03 +00:00
Nick Lewycky e8415fea4b Fix CountCodeReductionForAlloca to more accurately represent what SROA can and
can't handle. Also don't produce non-zero results for things which won't be
transformed by SROA at all just because we saw the loads/stores before we saw
the use of the address.

llvm-svn: 148536
2012-01-20 08:35:20 +00:00
Andrew Trick c908b43d9f SCEVExpander fixes. Affects LSR and indvars.
LSR has gradually been improved to more aggressively reuse existing code, particularly existing phi cycles. This exposed problems with the SCEVExpander's sloppy treatment of its insertion point. I applied some rigor to the insertion point problem that will hopefully avoid an endless bug cycle in this area. Changes:

- Always used properlyDominates to check safe code hoisting.

- The insertion point provided to SCEV is now considered a lower bound. This is usually a block terminator or the use itself. Under no cirumstance may SCEVExpander insert below this point.

- LSR is reponsible for finding a "canonical" insertion point across expansion of different expressions.

- Robust logic to determine whether IV increments are in "expanded" form and/or can be safely hoisted above some insertion point.

Fixes PR11783: SCEVExpander assert.

llvm-svn: 148535
2012-01-20 07:41:13 +00:00
Craig Topper 3469212c82 Add support for selecting 256-bit PALIGNR.
llvm-svn: 148532
2012-01-20 05:53:00 +00:00
Bill Wendling 9249261858 When lowering the 'resume' instruction, look to see if we can eliminate the
'insertvalue' instructions that recreate the structure returned by the
'landingpad' instruction. Because the 'insertvalue' instruction isn't supported
by FastISel, this can save a bit of time during -O0 compilation.

llvm-svn: 148520
2012-01-20 00:53:28 +00:00
Eli Friedman 32c7c25dcb Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.
llvm-svn: 148513
2012-01-20 00:05:46 +00:00
Benjamin Kramer 116e99a469 Silence warnings about mixing enums.
llvm-svn: 148495
2012-01-19 21:11:13 +00:00
Owen Anderson 4b53e188c1 Add a dump() implementation for sub-instruction MCOperands.
llvm-svn: 148493
2012-01-19 19:32:20 +00:00
Dan Gohman 8ee108bf98 Set the "tail" flag on pattern-matched objc_storeStrong calls.
rdar://10531041.

llvm-svn: 148490
2012-01-19 19:14:36 +00:00
Devang Patel f83dcfd052 Post process 'and', 'sub' instructions and select better encoding, if available.
llvm-svn: 148489
2012-01-19 18:40:55 +00:00
Nick Lewycky 219e6bcb71 Actually, this code handles wrapped sets just fine. Noticed by inspection.
llvm-svn: 148487
2012-01-19 18:19:42 +00:00
Devang Patel 2529dd9e00 Intel syntax: There is no need to create unary expr for simple negative displacement.
llvm-svn: 148486
2012-01-19 18:15:51 +00:00
Devang Patel 4a62ff9bcb Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
llvm-svn: 148485
2012-01-19 17:53:25 +00:00
Evgeniy Stepanov 4c7eb477b5 Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.
llvm-svn: 148473
2012-01-19 12:53:06 +00:00
Craig Topper a875b7ccc7 Folding table additions and fixes for AVX.
llvm-svn: 148467
2012-01-19 08:50:38 +00:00