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387 Commits

Author SHA1 Message Date
Evan Cheng 45e19098a6 DAG based isel call support. 
llvm-svn: 25103
 2006-01-05 00:27:02 +00:00
Evan Cheng 14c53b45f5 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
 2005-12-26 09:11:45 +00:00
Evan Cheng 9ae486047e * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. 
* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997
 2005-12-23 22:14:32 +00:00
Evan Cheng 5c59d49630 More X86 floating point patterns. 
llvm-svn: 24990
 2005-12-23 07:31:11 +00:00
Evan Cheng dfad8ed54e Bye bye HACKTROCITY. 
llvm-svn: 24935
 2005-12-22 02:26:21 +00:00
Evan Cheng 9cdc16c6d3 * Fix a GlobalAddress lowering bug. 
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.

llvm-svn: 24921
 2005-12-21 23:05:39 +00:00
Evan Cheng 02767195bb Oops. Accidentally deleted RET pattern. It's still needed for return void; 
llvm-svn: 24920
 2005-12-21 22:22:16 +00:00
Evan Cheng c1583dbd63 * Added support for X86 RET with an additional operand to specify number of 
bytes to pop off stack.
* Added support for X86 SETCC.

llvm-svn: 24917
 2005-12-21 20:21:51 +00:00
Chris Lattner 0dcdd83c0e This was meant to go in 
llvm-svn: 24900
 2005-12-21 07:50:26 +00:00
Chris Lattner f431ad4477 Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns 
that were overloaded to work before and after the stackifier runs.  With the
new clean world, it is possible to write patterns for these instructions: woo!

This also adds a few simple patterns here and there, though there are a lot
still missing.  These should be easy to add though. :)

See the comments under "Floating Point Stack Support" for more details on
the new world order.

This patch as absolutely no effect on the generated code, woo!

llvm-svn: 24899
 2005-12-21 07:47:04 +00:00
Chris Lattner 988827a482 Wrap some long lines: no functionality change 
llvm-svn: 24898
 2005-12-21 05:34:58 +00:00
Evan Cheng a74ce62746 * Added lowering hook for external weak global address. It inserts a load 
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
  value (or store / fld / copy to ST(0) for floating point value). This
  eliminate the need to write C++ code to handle RET with variable number
  of operands.

llvm-svn: 24888
 2005-12-21 02:39:21 +00:00
Evan Cheng 5c0b4df483 SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns. 
llvm-svn: 24886
 2005-12-20 22:59:51 +00:00
Evan Cheng 5815a6e455 Added X86 readport patterns. 
llvm-svn: 24879
 2005-12-20 07:38:38 +00:00
Evan Cheng 6fc31046aa X86 conditional branch support. 
llvm-svn: 24870
 2005-12-19 23:12:38 +00:00
Chris Lattner db8e888fb5 eliminate some redundancy 
llvm-svn: 24781
 2005-12-17 19:47:05 +00:00
Evan Cheng b06925d1dd Added anyext, modelled as zext on X86. 
llvm-svn: 24759
 2005-12-17 01:47:57 +00:00
Evan Cheng cb19390ead Added support for cmp, test, and conditional move instructions. 
llvm-svn: 24756
 2005-12-17 01:24:02 +00:00
Evan Cheng 74151ba279 * Promote all 1 bit entities to 8 bit. 
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726
 2005-12-15 19:49:23 +00:00
Evan Cheng 305c6a73b5 Added frameindex, constpool, globaladdr, and externalsym as root nodes of 
leaaddr.

llvm-svn: 24724
 2005-12-15 08:31:04 +00:00
Evan Cheng bc9344477e Use MOV8rm to load 1 bit value. 
llvm-svn: 24721
 2005-12-15 00:59:17 +00:00
Evan Cheng c273900dd8 Added sext and zext patterns. 
llvm-svn: 24705
 2005-12-14 02:22:27 +00:00
Evan Cheng 229f0ee6d7 Add load + store folding srl and sra patterns. 
llvm-svn: 24696
 2005-12-13 07:24:22 +00:00
Evan Cheng acec857b1a Beautify a few patterns. 
llvm-svn: 24690
 2005-12-13 02:40:18 +00:00
Evan Cheng 89c6db4baf Some shl patterns which do load + store folding. 
llvm-svn: 24689
 2005-12-13 02:34:51 +00:00
Evan Cheng 108beceb0f A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility. 
llvm-svn: 24688
 2005-12-13 01:57:51 +00:00
Evan Cheng ddd5ae5a22 Add and, or, and xor patterns which fold load + stores. 
llvm-svn: 24687
 2005-12-13 01:41:36 +00:00
Evan Cheng e5a94a03e2 Add inc + dec patterns which fold load + stores. 
llvm-svn: 24686
 2005-12-13 01:02:47 +00:00
Evan Cheng bde9e6fca6 Add neg and not patterns which fold load + stores. 
llvm-svn: 24685
 2005-12-13 00:54:44 +00:00
Evan Cheng c414d563f0 Missed a couple redundant explicit type casts. 
llvm-svn: 24684
 2005-12-13 00:25:07 +00:00
Evan Cheng 62e6808aa5 Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc. 
llvm-svn: 24683
 2005-12-13 00:14:11 +00:00
Evan Cheng 86b2cf22d2 * Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands. 
This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.

llvm-svn: 24682
 2005-12-13 00:01:09 +00:00
Evan Cheng 3e52756928 Add some integer mul patterns. 
llvm-svn: 24681
 2005-12-12 23:47:46 +00:00
Evan Cheng af3fe8217a Add some sub patterns. 
llvm-svn: 24675
 2005-12-12 21:54:05 +00:00
Evan Cheng e80248b378 Add a few more add / store patterns. e.g. ADD32mi8. 
llvm-svn: 24670
 2005-12-12 19:45:23 +00:00
Evan Cheng 0d6cfee704 * Added X86 store patterns. 
* Added X86 dec patterns.

llvm-svn: 24654
 2005-12-10 00:48:20 +00:00
Evan Cheng 275a3ed80c Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al 
llvm-svn: 24648
 2005-12-09 22:48:48 +00:00
Evan Cheng f039648614 Added explicit type field to ComplexPattern. 
llvm-svn: 24637
 2005-12-08 02:15:07 +00:00
Evan Cheng c9fab31098 * Added intelligence to X86 LEA addressing mode matching routine so it returns 
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.

llvm-svn: 24635
 2005-12-08 02:01:35 +00:00
Evan Cheng c0c190239d Remove unnecessary let hasCtrlDep=1 now it can be inferred. 
llvm-svn: 24611
 2005-12-05 23:09:43 +00:00
Chris Lattner 3c0b8f577d Several things: 
1. Remove redundant type casts now that PR673 is implemented.
2. Implement the OUT*ir instructions correctly.  The port number really
   *is* a 16-bit value, but the patterns should only match if the number
   is 0-255.  Update the patterns so they now match.
3. Fix patterns for shifts to reflect that the shift amount is always an
   i8, not an i16 as they were believed to be before.  This previous fib
   stopped working when we started knowing that CL has type i8.
4. Change use of i16i8imm in SH*ri patterns to all be imm.

llvm-svn: 24599
 2005-12-05 02:40:25 +00:00
Evan Cheng 95cb763818 Added isel patterns for RET, JMP, and WRITEPORT. 
llvm-svn: 24588
 2005-12-04 08:19:43 +00:00
Evan Cheng 4b02426130 Proper support for shifts with register shift value. 
llvm-svn: 24559
 2005-12-01 00:43:55 +00:00
Nate Begeman 6f8c1ace6e No longer track value types for asm printer operands, and remove them as 
an argument to every operand printing function.  Requires some slight
tweaks to x86, the only user.

llvm-svn: 24541
 2005-11-30 18:54:35 +00:00
Chris Lattner 9c7af08bc9 Fix a bug in a recent patch that broke shifts 
llvm-svn: 24526
 2005-11-30 05:11:18 +00:00
Evan Cheng 72ab335858 Add more X86 ISel patterns. 
llvm-svn: 24520
 2005-11-29 19:38:52 +00:00
Chris Lattner d1061ac8d1 encode rdtsc correctly 
llvm-svn: 24435
 2005-11-20 22:13:18 +00:00
Andrew Lenharth 0bf68ae434 The second patch of X86 support for read cycle counter. 
llvm-svn: 24430
 2005-11-20 21:41:10 +00:00
Chris Lattner d7102c4980 Teach the x86 backend about the register constraints of its addressing mode. 
Patch by Evan Cheng

llvm-svn: 24423
 2005-11-19 07:01:30 +00:00
Chris Lattner 57ce97862d add more patterns, patch by Evan Cheng. 
llvm-svn: 24406
 2005-11-18 01:04:42 +00:00
Chris Lattner 2bf458af92 Add patterns for some 16-bit immediate instructions, patch contributed by 
Evan Cheng.

llvm-svn: 24384
 2005-11-17 02:01:55 +00:00
Chris Lattner 5930d3df3d Add patterns for several simple instructions that take i32 immediates. 
Patch contributed by Evan Cheng!

llvm-svn: 24382
 2005-11-16 22:59:19 +00:00
Nate Begeman 9d7008b08d Properly split f32 and f64 into separate register classes for scalar sse fp 
fixing a bunch of nasty hackery

llvm-svn: 23735
 2005-10-14 22:06:00 +00:00
Chris Lattner 2e84be22a8 give all operands names 
llvm-svn: 23356
 2005-09-14 21:10:24 +00:00
Chris Lattner 423d7cbbf8 add a few missing cases 
llvm-svn: 22891
 2005-08-19 00:41:29 +00:00
Chris Lattner e2967ac53d Give ADJCALLSTACKDOWN/UP the correct operands. 
Give a whole bunch of other stuff variable operands, particularly FP.  The
FP stackifier is playing fast and loose with operands here, so we have to
mark them all as variable.  This will have to be fixed before we can dag->dag
the X86 backend.  The solution is for the pre-stackifier and post-stackifier
instructions to all be disjoint.

llvm-svn: 22890
 2005-08-19 00:38:22 +00:00
Nate Begeman 8d394eb703 Scalar SSE: load +0.0 -> xorps/xorpd 
Scalar SSE: a < b ? c : 0.0 -> cmpss, andps
Scalar SSE: float -> i16 needs to be promoted

llvm-svn: 22637
 2005-08-03 23:26:28 +00:00
Nate Begeman a0b5e035ea Get closer to fully working scalar FP in SSE regs. This gets singlesource 
working, and Olden/power.

llvm-svn: 22441
 2005-07-15 00:38:55 +00:00
Nate Begeman 8a0933608a First round of support for doing scalar FP using the SSE2 ISA extension and 
XMM registers.  There are many known deficiencies and fixmes, which will be
addressed ASAP.  The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.

The x86 backend will still default to x87 style FP.  To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.

An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
                        Sum += P[i]; return Sum; }

The inner loop looks like the following:
x87:
.LBB_foo_1:     # no_exit
        fldl (%esp)
        faddl (%eax,%ecx,8)
        fstpl (%esp)
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

SSE2:
        addsd (%eax,%ecx,8), %xmm0
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

llvm-svn: 22340
 2005-07-06 18:59:04 +00:00
Nate Begeman db32921535 Initial set of .td file changes necessary to get scalar fp in xmm registers 
working.  The instruction selector changes will hopefully be coming later
this week once they are debugged.  This is necessary to support the darwin
x86 FP model, and is recommended by intel as the replacement for x87.  As
a bonus, the register allocator knows how to deal with these registers
across basic blocks, unliky the FP stackifier.  This leads to significantly
better codegen in several cases.

llvm-svn: 22300
 2005-06-27 21:20:31 +00:00
Chris Lattner 3f5a98d1f4 Add markers in the asm file for tail calls, add a new ADJSTACKPTRri 
sorta-pseudo-instruction

llvm-svn: 22042
 2005-05-15 03:10:37 +00:00
Chris Lattner 6b5fa91a63 Yes, calltarget is the operand of the day. 
llvm-svn: 22040
 2005-05-15 01:10:30 +00:00
Chris Lattner f0649db870 Add some new instructions 
llvm-svn: 22036
 2005-05-14 23:35:21 +00:00
Chris Lattner 6e4c2302e6 add 'ret imm' instruction 
llvm-svn: 21945
 2005-05-13 17:56:48 +00:00
Chris Lattner 46b5ca4310 Fix the syntax of the i/o instructions, these are obviously unused. 
llvm-svn: 21829
 2005-05-09 20:49:20 +00:00
Chris Lattner 61827484c7 Add some new X86 instrs, patch contributed by Morten Ofstad 
llvm-svn: 21608
 2005-04-28 21:50:05 +00:00
Chris Lattner c21db6b15c add signed versions of the extra precision multiplies 
llvm-svn: 21106
 2005-04-06 04:19:22 +00:00
Chris Lattner 2d451658a6 add an fabs instr 
llvm-svn: 21006
 2005-04-02 04:31:56 +00:00
Chris Lattner 0ce80cd542 Fix spelling, patch contributed by Gabor Greif! 
llvm-svn: 20343
 2005-02-27 06:18:25 +00:00
Chris Lattner 0edf9535b9 Add rotate instructions. 
llvm-svn: 19690
 2005-01-19 07:50:03 +00:00
Chris Lattner d54845f530 Improve coverage of the X86 instruction set by adding 16-bit shift doubles. 
llvm-svn: 19687
 2005-01-19 07:31:24 +00:00
Chris Lattner 2947801735 Teach the code generator that shrd/shld is commutable if it has an immediate. 
This allows us to generate this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        shld %EDX, %EDX, 2
        shl %EAX, 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EDX, %EAX
        shrd %EDX, %ECX, 30
        shl %EAX, 2
        ret

Note the magically transmogrifying immediate.

llvm-svn: 19686
 2005-01-19 07:11:01 +00:00
Chris Lattner 5b589ec0c4 Add conditional moves for the parity flag. 
llvm-svn: 19437
 2005-01-10 22:09:33 +00:00
Chris Lattner d4bb2bbce1 ADC and IMUL are also commutable. 
llvm-svn: 19264
 2005-01-03 01:27:59 +00:00
Chris Lattner 295e45e60e Two changes here: 
1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP.
2. Set the isCommutable and isPromotableTo3Address bits on several
   instructions.

llvm-svn: 19246
 2005-01-02 02:35:46 +00:00
John Criswell 04570265a5 Correct the name of stosd for the AT&T syntax: 
It's stosl (l for long == 32 bit).

llvm-svn: 17658
 2004-11-10 04:48:15 +00:00
Chris Lattner 93867e516a Remove debugging code, fix encoding problem. This fixes the problems 
the JIT had last night.

llvm-svn: 16766
 2004-10-06 14:31:50 +00:00
Chris Lattner e9bfa5a2a4 Add some new instructions. Fix the asm string for sbb32rr 
llvm-svn: 16759
 2004-10-06 04:01:02 +00:00
Chris Lattner 8bbde2fb33 Convert some missed patterns to support AT&T style 
llvm-svn: 16645
 2004-10-04 07:23:07 +00:00
Chris Lattner 2e99778aad Apparently the GNU assembler has a HUGE hack to be compatible with really 
old and broken AT&T syntax assemblers.  The problem with this hack is that
*SOME* forms of the fdiv and fsub instructions have the 'r' bit inverted.
This was a real pain to figure out, but is trivially easy to support: thus
we are now bug compatible with gas and gcc.

llvm-svn: 16644
 2004-10-04 07:08:46 +00:00
Chris Lattner af69503332 Fix incorrect suffix 
llvm-svn: 16642
 2004-10-04 05:20:16 +00:00
Chris Lattner e1a2826d51 Fix some more missed suffixes and swapped operands 
llvm-svn: 16641
 2004-10-04 01:38:10 +00:00
Chris Lattner a488f04f3e Add missing suffixes to FP instructions for AT&T mode 
llvm-svn: 16640
 2004-10-04 00:43:31 +00:00
Chris Lattner 4e59a14909 Add support to the instruction patterns for AT&T style output, which will 
hopefully lead to the death of the 'GasBugWorkaroundEmitter'.  This also
includes changes to wrap the whole file to 80 columns! Woot! :)

Note that the AT&T style output has not been tested at all.

llvm-svn: 16638
 2004-10-03 20:35:00 +00:00
Alkis Evlogimenos 371403193c Use a shorter form to express implicit use/defs in FpGETRESULT and 
FpSETRESULT.

llvm-svn: 16247
 2004-09-08 18:29:31 +00:00
Alkis Evlogimenos 8b700215ed A call instruction should implicitely define ST0 since the return 
value is returned in that register. The pseudo instructions
FpGETRESULT and FpSETRESULT shold also have an implicity use and def
of ST0 repsecitvely.

llvm-svn: 16246
 2004-09-08 16:54:54 +00:00
Chris Lattner eb34c59930 Remove a bunch of ad-hoc target-specific flags that were only used by the 
old asmprinter.

llvm-svn: 15660
 2004-08-11 07:12:04 +00:00
Chris Lattner a0bafce127 Add asmprintergen support for the last X86 instruction that needs it: pcrelative calls. 
llvm-svn: 15657
 2004-08-11 06:59:12 +00:00
Chris Lattner 5f4b65e57d Scrunch memoperands, add a few more for floating point memops 
Eliminate the FPI*m classes, converting them to use FPI instead.

llvm-svn: 15655
 2004-08-11 06:50:10 +00:00
Chris Lattner 6dd0474edd Make FPI take asm string and operand list 
llvm-svn: 15653
 2004-08-11 05:54:16 +00:00
Chris Lattner c52899c3c7 Nuke the Im*i* patterns, by asmprintergenifying all users. 
llvm-svn: 15652
 2004-08-11 05:31:07 +00:00
Chris Lattner f5c767038a X86 instructions that read-modify-write memory are not LLVM two-address instructions. 
llvm-svn: 15651
 2004-08-11 05:07:25 +00:00
Chris Lattner 0d7bc2c5da Get rid of the Im8, Im16, Im32 classes, converting more instructions over to 
asmprintergeneration

llvm-svn: 15650
 2004-08-11 04:31:00 +00:00
Chris Lattner 09ee05bcdf Convert asmprinter to new style of instruction printer 
Start asmprintergen'ifying machine instrs with memory operands.

llvm-svn: 15646
 2004-08-11 02:25:00 +00:00
Chris Lattner ce5fb7db1c This is purely a formatting patch that gets us closer to the mecca of fitting 
X86InstrInfo.td into 80 columns

llvm-svn: 15629
 2004-08-10 21:21:30 +00:00
Chris Lattner 116fc25d79 Drop the first argument of FPI, and asmprinterify fxch 
llvm-svn: 15628
 2004-08-10 21:02:13 +00:00
Chris Lattner ead14c1a07 This purely mechanical patch gives the "I" tblgen class operand list and asm 
string operands, and adjusts all users to pass them in instead of using II.

llvm-svn: 15624
 2004-08-10 20:17:41 +00:00
Chris Lattner c4eb5951d5 Convert Ii32 instructions over to use the asmprinter generator 
llvm-svn: 15621
 2004-08-10 19:06:36 +00:00
Chris Lattner 9f49a91b44 Convert the Ii16 instructions over 
llvm-svn: 15606
 2004-08-10 16:22:02 +00:00
Chris Lattner 4d66b78036 Convert all Ii8 instructions over to the autogenerated asmprinter. 
llvm-svn: 15605
 2004-08-10 16:09:54 +00:00
Chris Lattner 2b47c02b64 Convert all I<> instructions to asmformat. 
Delete the 'name' field of all instructions that have asmformats.

llvm-svn: 15403
 2004-08-01 09:52:59 +00:00
Chris Lattner 27fcf976f2 Eliminate 3 of the X86 printImplicit* flags. 
llvm-svn: 15398
 2004-08-01 08:23:17 +00:00
Chris Lattner f6bd77190e Convert more instructions over to the asmprinter 
llvm-svn: 15396
 2004-08-01 08:13:11 +00:00
Chris Lattner 275d98dcbb Switch more instructions over to using the asmprinter. Fix bugs in the emission 
of in/out instructions (missing %'s on registers).

llvm-svn: 15393
 2004-08-01 07:44:35 +00:00
Chris Lattner 321763358b Specify an asm string and operands lists for a bunch of instructions. 
This only really covers no-operand instructions so far.

llvm-svn: 15387
 2004-08-01 06:01:00 +00:00
Chris Lattner 70d2260eb9 Entirely eliminate all patterns and expanders from this file. We shall go 
with an incremental approach rather than a revolutionary approach.

llvm-svn: 15379
 2004-08-01 03:25:01 +00:00
Chris Lattner 66a13e230d Mark barrier instructions. Execution does not fall through uncond branches 
or return intructions.

llvm-svn: 15356
 2004-07-31 02:10:53 +00:00
Chris Lattner 5ed9113e14 No really, these are dead now 
llvm-svn: 14145
 2004-06-11 04:50:14 +00:00
Chris Lattner b35f47627d Now that compare instructions aren't lumped in with the other twoargfp instructions, 
we can get rid of the FpUCOM/FpUCOMi pseudo instructions, which makes stuff simpler
and faster.

llvm-svn: 14144
 2004-06-11 04:49:02 +00:00
Chris Lattner 0876edf122 Introduce a new FP instruction type to separate the compare cases from the 
twoarg cases.

llvm-svn: 14143
 2004-06-11 04:41:24 +00:00
Chris Lattner a0cfedef3a Add support for the setp instructions 
llvm-svn: 14140
 2004-06-11 04:30:06 +00:00
Chris Lattner a340febe52 Add immediate forms of in/out. Use let to shorten lines 
llvm-svn: 12895
 2004-04-13 17:19:31 +00:00
Chris Lattner a24f986333 Fix issues that the local allocator has dealing with instructions that implicitly use ST(0) 
llvm-svn: 12855
 2004-04-12 03:02:48 +00:00
Chris Lattner 2e2b0ceab9 No really, fix printing for LLC. I gotta get a way for CVS to whine at me if 
I have unsaved emacs buffers, geeze...

llvm-svn: 12854
 2004-04-12 01:52:04 +00:00
Chris Lattner ba1038e0f3 Correct printing for LLC and the encoding for the JIT 
llvm-svn: 12853
 2004-04-12 01:50:04 +00:00
Chris Lattner 6c84d4ca44 Add two new instructions 
llvm-svn: 12850
 2004-04-12 01:38:55 +00:00
Chris Lattner b6e0b58fbc Add some new instructions 
llvm-svn: 12838
 2004-04-11 20:24:15 +00:00
John Criswell c28c3b625f Changes recommended by Chris: 
InstSelectSimple.cpp:
  Change the checks for proper I/O port address size into an exit() instead
  of an assertion.  Assertions aren't used in Release builds, and handling
  this error should be graceful (not that this counts as graceful, but it's
  more graceful).

  Modified the generation of the IN/OUT instructions to have 0 arguments.
X86InstrInfo.td:
  Added the OpSize attribute to the 16 bit IN and OUT instructions.

llvm-svn: 12786
 2004-04-08 22:39:13 +00:00
John Criswell 10db062d41 Added the llvm.readport and llvm.writeport intrinsics for x86. These do 
I/O port instructions on x86.  The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output.  This required adjustment to some
methods so that a leading comma would or would not be printed.

llvm-svn: 12782
 2004-04-08 20:31:47 +00:00
Chris Lattner ba33ae5831 Fix incorrect encoding of some ADC and SBB instuctions 
llvm-svn: 12710
 2004-04-06 19:20:32 +00:00
Chris Lattner 9366f0347d The sbb instructions really ARE sbb's, not adc's 
llvm-svn: 12682
 2004-04-06 02:02:11 +00:00
Alkis Evlogimenos fe66caa9a0 Fix type in comments 
llvm-svn: 12611
 2004-04-02 16:02:50 +00:00
Alkis Evlogimenos d186ed02e4 Add more ADC and SBB variants 
llvm-svn: 12607
 2004-04-02 07:11:10 +00:00
Chris Lattner 9fe1646804 Add FP conditional move instructions, which annoyingly have special properties 
that require the asmwriter to be extended (printing implicit uses before the
explicit operands)

llvm-svn: 12574
 2004-03-31 22:02:13 +00:00
Chris Lattner 1563983d81 Fix some serious bugs in the cmov descriptions, which didn't cause a problem because 
we never generated them

Make indentation a bit more consistent

llvm-svn: 12549
 2004-03-30 20:18:02 +00:00
Alkis Evlogimenos 804dc659b6 Add LAHF instruction 
llvm-svn: 12424
 2004-03-15 17:20:14 +00:00
Alkis Evlogimenos 9884bda541 Add support for a wider range of CMOV instructions. 
llvm-svn: 12336
 2004-03-12 17:59:56 +00:00
Alkis Evlogimenos 8a3f2f3600 Differentiate between extended precision floats (80-bit) and double precision floats (64-bit) 
llvm-svn: 12254
 2004-03-09 03:37:54 +00:00
Alkis Evlogimenos d6f62ba55b Add memory operand version of conditional move. 
llvm-svn: 12190
 2004-03-07 03:19:11 +00:00
Alkis Evlogimenos 0824ffc697 Use correct template for SHLD and SHRD instructions so that the memory 
operand size is correctly specified.

llvm-svn: 11997
 2004-02-29 09:19:40 +00:00
Alkis Evlogimenos ea81b79a97 A big X86 instruction rename. The instructions are renamed to make 
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995
 2004-02-29 08:50:03 +00:00
Alkis Evlogimenos 876f6f96d0 Use correct template for ADC instruction with memory operands. 
llvm-svn: 11974
 2004-02-29 02:18:17 +00:00
Alkis Evlogimenos fa63580517 SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them 
to denote this fact.

llvm-svn: 11972
 2004-02-28 23:46:44 +00:00
Alkis Evlogimenos 4953ae085a Floating point loads/stores act on memory operands. Rename them to 
denote this fact.

llvm-svn: 11971
 2004-02-28 23:42:35 +00:00
Alkis Evlogimenos c6948fa762 Rename instruction templates to be easier to the human eye to 
parse. The name is now I (operand size)*. For example:

Im32 -> instruction with 32-bit memory operands.

Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
          operands.

llvm-svn: 11970
 2004-02-28 23:09:03 +00:00
Alkis Evlogimenos 194939086d Each instruction now has both an ImmType and a MemType. This describes 
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).

llvm-svn: 11967
 2004-02-28 22:02:05 +00:00
Alkis Evlogimenos 2debead504 Do not generate instructions with mismatched memory/immediate sized 
operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944
 2004-02-28 06:01:43 +00:00
Alkis Evlogimenos 24b3d0bdae Further comment updates. 
llvm-svn: 11933
 2004-02-28 03:20:31 +00:00
Alkis Evlogimenos f87966b8c4 Update comments. 
llvm-svn: 11932
 2004-02-28 03:12:31 +00:00
Alkis Evlogimenos 2dbc79df84 My previous commit broke the jit. The shift instructions always take 
an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.

A bug still exists:

def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8

The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.

llvm-svn: 11931
 2004-02-28 02:56:26 +00:00
Alkis Evlogimenos b10b04c5ec Fix argument size for SHL, SHR, SAR, SHLD and SHRD families of 
instructions.

llvm-svn: 11923
 2004-02-27 19:46:30 +00:00
Alkis Evlogimenos 75ed0f67bf Fix encoding of ADD and SUB family of instructions. Also rearrange 
them so that they are consistent with AND, XOR, etc...

llvm-svn: 11922
 2004-02-27 18:57:00 +00:00
Alkis Evlogimenos 58270fcf1f Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}. 
llvm-svn: 11921
 2004-02-27 18:55:12 +00:00
Alkis Evlogimenos 9476b7cbe5 Add memory operand folding support for the SETcc family of 
instructions.

llvm-svn: 11907
 2004-02-27 16:13:37 +00:00
Alkis Evlogimenos 8d99063b38 Add memory operand folding support for SHLD and SHRD instructions. 
llvm-svn: 11905
 2004-02-27 15:03:18 +00:00
Alkis Evlogimenos 3537404299 Add memory operand folding support for SHL, SHR and SAR, SHLD instructions. 
llvm-svn: 11903
 2004-02-27 09:28:43 +00:00
Alkis Evlogimenos f020dfb43c Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them 
consistent with the rest and also pepare for the addition of their
memory operand variants.

llvm-svn: 11902
 2004-02-27 06:57:05 +00:00
Chris Lattner 378157c3d7 Add a new cmove instruction 
llvm-svn: 11722
 2004-02-23 01:16:05 +00:00
Alkis Evlogimenos 6401b22fc2 Fix argument size for MOVSX and MOVZX instructions. 
llvm-svn: 11576
 2004-02-18 16:20:40 +00:00
Alkis Evlogimenos 47ea17a852 These store to memory too. 
llvm-svn: 11558
 2004-02-17 17:53:48 +00:00
Chris Lattner 49794be442 These store to memory, not read from it. 
llvm-svn: 11556
 2004-02-17 17:46:50 +00:00
Alkis Evlogimenos 546513ccfd Add TEST and XCHG memory operand support. 
llvm-svn: 11550
 2004-02-17 15:48:42 +00:00
Alkis Evlogimenos f08064b714 Add OR and XOR memory operand support. 
llvm-svn: 11549
 2004-02-17 15:33:14 +00:00
Alkis Evlogimenos e5585328d8 Add memory operand folding support for MUL, DIV, IDIV, NEG, NOT, 
MOVSX, and MOVZX.

llvm-svn: 11546
 2004-02-17 09:14:23 +00:00
Alkis Evlogimenos 574c7c9ce9 Add CMP{rm,mr,mi}{8,16,32}, INCm{8,16,32} and DECm{8,16,32} instructions. 
llvm-svn: 11544
 2004-02-17 08:49:00 +00:00
Alkis Evlogimenos d5ce14ddd1 Add SUB{rm,mr,mi}{8,16,32} instructions. 
llvm-svn: 11543
 2004-02-17 08:17:40 +00:00
Alkis Evlogimenos b591e5de31 Add support for ADC{rm.mr}32 and SBB{rm,mr}32. 
llvm-svn: 11540
 2004-02-17 08:06:31 +00:00
Chris Lattner 3abcdf3b90 Fix the mneumonics for the mov instructions to have the source and destination 
order in the correct sense!! Arg!

llvm-svn: 11530
 2004-02-17 06:28:19 +00:00
Chris Lattner ebd90733b0 Fix the last crimes against nature that used the 'ir' ordering to use the 
'ri' ordering instead... no it's not possible to store a register into an
immediate!

llvm-svn: 11529
 2004-02-17 06:24:02 +00:00
Chris Lattner 288e043e1b Rename MOVi[mr] instructions to MOV[rm]i 
llvm-svn: 11527
 2004-02-17 06:16:44 +00:00
Chris Lattner c9586411cf Add mem forms of AND instructions 
llvm-svn: 11521
 2004-02-17 05:25:50 +00:00
Chris Lattner 818bcec247 Rename the IMULri* instructions to IMULrri, as they are actually three address 
instructions.  Add forms of these instructions that read from memory

llvm-svn: 11518
 2004-02-17 04:26:43 +00:00
Alkis Evlogimenos f6ce2e313a Add two more variants of add. Update comments. 
llvm-svn: 11510
 2004-02-16 23:48:42 +00:00
Chris Lattner 544c9781db Add some ADD instructions that take memory operands for Alkis 
llvm-svn: 11502
 2004-02-16 18:19:31 +00:00
Chris Lattner 2e4acc0a73 Add support for the 'pop' instruction 
llvm-svn: 11451
 2004-02-14 21:06:02 +00:00
Chris Lattner d6a39eaa70 Urg, right. These need an input value... 
llvm-svn: 11443
 2004-02-14 04:47:23 +00:00
Chris Lattner 8bed37595d add 'rep stos[bwd]' instructions 
llvm-svn: 11441
 2004-02-14 04:45:37 +00:00
Chris Lattner 8dc99feeaf Add support for the rep movs[bwd] instructions, and emit them when code 
generating the llvm.memcpy intrinsic.

llvm-svn: 11351
 2004-02-12 17:53:22 +00:00
Alkis Evlogimenos dbf4b42fde IMULri* instructions do not require their first two registers operands 
to be the same (IOW they are not two address instructions).

llvm-svn: 11117
 2004-02-04 17:21:04 +00:00
Chris Lattner 3c8c72c54f Add the ftst instruction 
llvm-svn: 11095
 2004-02-03 07:27:50 +00:00
Chris Lattner 63b61e8739 No need to declare implicit uses/defs of ST0 
llvm-svn: 11081
 2004-02-02 19:57:45 +00:00
Chris Lattner 30d26ac561 Generate the fchs instruction to negate a floating point number 
llvm-svn: 11078
 2004-02-02 19:31:38 +00:00
Alkis Evlogimenos 68cff6bf4d Remove floating point killer pass. This is now implemented in the 
instruction selector by adding a new pseudo-instruction
FP_REG_KILL. This instruction implicitly defines all x86 fp registers
and is a terminator so that passes which add machine code at the end
of basic blocks (like phi elimination) do not add instructions between
it and the branch or return instruction.

llvm-svn: 10562
 2003-12-20 16:22:59 +00:00
John Criswell 29265fe981 Added LLVM copyright header. 
llvm-svn: 9321
 2003-10-21 15:17:13 +00:00
Chris Lattner 6acb1bedb1 Emit x86 instructions for: A = B op C, where A and B are 16-bit registers, 
C is a constant which can be sign-extended from 8 bits without value loss,
and op is one of: add, sub, imul, and, or, xor.

This allows the JIT to emit the one byte version of the constant instead of
the two or 4 byte version.  Because these instructions are very common, this
can save a LOT of code space.  For example, I sampled two benchmarks, 176.gcc
and 254.gap.

BM        Old     New    Reduction
176.gcc 2673621 2548962  4.89%
254.gap  498261  475104  4.87%

Note that while the percentage is not spectacular, this did eliminate
124.6 _KILOBYTES_ of codespace from gcc.  Not bad.

Note that this doesn't effect the llc version at all, because the assembler
already does this optimization.

llvm-svn: 9284
 2003-10-20 05:53:31 +00:00
Chris Lattner 97e1b55723 * Rename X86::IMULr16 -> X86::IMULrr16 
* Implement R1 = R2 * C where R1 and R2 are 32 or 16 bits. This avoids an
  extra copy into a register, reducing register pressure.

llvm-svn: 9278
 2003-10-20 03:42:58 +00:00
Chris Lattner 55a8ef0cc8 Add some new instructions. Wheee 
llvm-svn: 9266
 2003-10-19 19:25:35 +00:00
Chris Lattner 7235d86507 Add support for unconditional branches and for emitting JE instructions 
llvm-svn: 7872
 2003-08-15 04:50:49 +00:00
Chris Lattner 7606fa0d41 Add basic support for 16 and 32 bit function arguments! 
llvm-svn: 7755
 2003-08-11 21:30:00 +00:00
Chris Lattner 2923637f63 Add (ret int) expander so that we can at least write testcases 
llvm-svn: 7730
 2003-08-11 15:48:00 +00:00
Chris Lattner 7fed97d00a Add patterns for multiply, and, or, and xor 
llvm-svn: 7725
 2003-08-11 15:23:25 +00:00
Chris Lattner 19d25b3c41 add a pattern for RET, immediates no longer need to be explicitly typed 
llvm-svn: 7635
 2003-08-06 15:31:35 +00:00
Chris Lattner 7c257321c7 This is the real fix for the previous register allocator problem. 
Physical registers should not float around.

llvm-svn: 7587
 2003-08-05 00:48:47 +00:00
Chris Lattner 148747e162 Add patterns for (mov R, R) (mov R, I) and subtracts. The moves are to enable 
testing, the subtracts are because I was in the neighborhood.

llvm-svn: 7581
 2003-08-04 21:18:19 +00:00
Chris Lattner 44cdcf013f Change comments into something that TableGen can read! 
llvm-svn: 7580
 2003-08-04 21:08:29 +00:00
Chris Lattner 2551080937 transition to using let instead of set 
llvm-svn: 7564
 2003-08-04 04:59:56 +00:00
Chris Lattner 59a4a91703 Add new TableGen instruction definitions 
llvm-svn: 7537
 2003-08-03 21:54:21 +00:00