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Author SHA1 Message Date
Jessica Clarke 00dfd4f870 Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases" 
The replacement doesn't work for llc, but it is needed by
patchable-function-entry.ll.

This reverts commit aa9a30b83a.
 2021-05-29 15:11:37 +01:00
Jessica Clarke aa9a30b83a [RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases 
Whilst here, also remove a couple of unnecessary -o - instances.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D103201
 2021-05-29 14:58:28 +01:00
Fangrui Song 1a79381bfa [RISCV][test] Migrate llvm-objdump --riscv-no-aliases to -M no-aliases 
--riscv-no-aliases is an internal cl::opt option not intended to be exported.
Use the user-facing -M no-aliases instead.
 2021-05-04 10:38:33 -07:00
Hsiangkai Wang c7189ba785 [RISCV] Add new vector instructions in v0.10. 
* Add new vector instructions in v0.10.
 - load/store for mask value vle1.v vse1.v
 - vsetivli for 0-31 immediate vector length.
* Rename vector instructions in v0.10.
 - vfrsqrte7 -> vfrsqrt7
 - vfrece7 -> vfrec7
* Reserve memory width encodings for EEW>128b.

Differential Revision: https://reviews.llvm.org/D95781
 2021-02-03 13:28:58 +08:00
Hsiangkai Wang 266820be35 [RISCV] Add new V instructions in v1.0-08a0b46. 
Add new V instructions.
vfrsqrte7.v
vfrece7.v
vrgatherei16.vv
vneg.v
vncvt.x.x.w
vfneg.v
 2021-01-22 00:59:58 +08:00
Hsiangkai Wang f03609b5c7 [RISCV] V does not imply F. 
If users want to use vector floating point instructions, they need to
specify 'F' extension additionally.

Differential Revision: https://reviews.llvm.org/D93282
 2020-12-17 10:57:36 +08:00
Hsiangkai Wang 47a4a27f47 Upgrade MC to v0.9. 
Differential revision: https://reviews.llvm.org/D80802
 2020-08-01 07:42:06 +08:00
Hsiangkai Wang 66da87dcba [RISCV] Assemble/Disassemble v-ext instructions. 
Assemble/disassemble RISC-V V extension instructions according to
latest version spec in https://github.com/riscv/riscv-v-spec/.

I have tested this patch using GNU toolchain. The encoding is aligned
to GNU assembler output. In this patch, there is a test case for each
instruction at least.

The V register definition is just for assemble/disassemble. Its type
is not important in this stage. I think it will be reviewed and modified
as we want to do codegen for scalable vector types.

This patch does not include Zvamo, Zvlsseg, and Zvediv.

Differential revision: https://reviews.llvm.org/D69987
 2020-06-28 00:54:07 +08:00