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Author SHA1 Message Date
Lewis Revill aa79a3fe8e [RISCV] Support assembling TLS add and associated modifiers 
This patch adds support in the MC layer for parsing and assembling the
4-operand add instruction needed for TLS addressing. This also involves
parsing the %tprel_hi, %tprel_lo and %tprel_add operand modifiers.

Differential Revision: https://reviews.llvm.org/D55341

llvm-svn: 357698
 2019-04-04 14:13:37 +00:00
Alex Bradbury 7d0e18d0dd [RISCV][MC] Reject bare symbols for the simm12 operand type 
addi a0, a0, foo and lw a0, foo(a0) and similar are now rejected. An explicit 
%lo and %pcrel_lo modifier is required. This matches gas behaviour.

llvm-svn: 342487
 2018-09-18 15:13:29 +00:00
Alex Bradbury a6e6248307 [RISCV] MC layer support for the standard RV64I instructions 
llvm-svn: 320024
 2017-12-07 10:53:48 +00:00