Commit Graph

173413 Commits

Author SHA1 Message Date
Simon Pilgrim f0c533b7db [CostModel][X86] Add truncate cost tests to cover all legal destination types
We were only testing costs for legal source vector element counts

llvm-svn: 350323
2019-01-03 14:49:39 +00:00
Andrea Di Biagio b284054b26 [MCA] Improve code comment and reuse an helper function in ResourceManager. NFCI
llvm-svn: 350322
2019-01-03 14:47:46 +00:00
Alex Bradbury 2ba76be882 [RISCV][MC] Accept %lo and %pcrel_lo on operands to li
This matches GNU assembler behaviour.

llvm-svn: 350321
2019-01-03 14:41:41 +00:00
Serge Guelton b2e5845838 Python compat - decode/encode string
Differential Revision: https://reviews.llvm.org/D56258

llvm-svn: 350320
2019-01-03 14:40:34 +00:00
Serge Guelton bd6769df27 Python compat - test if type is integral
Rely on numbers.Integral instead of int/long

Differential Revision: https://reviews.llvm.org/D56262

llvm-svn: 350316
2019-01-03 14:12:50 +00:00
Serge Guelton 3026e912a3 Python compat - urllib
Differential Revision: https://reviews.llvm.org/D56261

llvm-svn: 350315
2019-01-03 14:12:44 +00:00
Serge Guelton c0606d2716 Python compat - has_key vs. in operator
Use portable `in` operator instead of `has_key(...)` method.

Differential Revision: https://reviews.llvm.org/D56260

llvm-svn: 350314
2019-01-03 14:12:37 +00:00
Serge Guelton 51eabbeeb4 Python compat - map/filter
Differential Revision: https://reviews.llvm.org/D56259

llvm-svn: 350313
2019-01-03 14:12:30 +00:00
Serge Guelton 873cba17b2 Python compat - iteritems() vs. items()
Always use `items()` and introduce extra `list(...)` call when needed.

Differential Revision: https://reviews.llvm.org/D56257

llvm-svn: 350312
2019-01-03 14:12:23 +00:00
Serge Guelton beb6fee542 Python compat - portable way of raising exceptions
Differential Revision: https://reviews.llvm.org/D56256

llvm-svn: 350311
2019-01-03 14:12:13 +00:00
Serge Guelton 7d0174c558 [NFC] Remove unused Python import
Differential Revision: https://reviews.llvm.org/D56254

llvm-svn: 350310
2019-01-03 14:12:07 +00:00
Serge Guelton 07ccb4b81d Pythran compat - range vs. xrange
Use range instead of xrange whenever possible. The extra list creation in Python2
is generally not a performance bottleneck.

Differential Revision: https://reviews.llvm.org/D56253

llvm-svn: 350309
2019-01-03 14:11:58 +00:00
Serge Guelton 707fab58a9 Python compat - assertRaisesRegex
Python3 uses assertRaisesRegex instad of assertRaisesRegexp.

Differential Revision: https://reviews.llvm.org/D56251

llvm-svn: 350308
2019-01-03 14:11:41 +00:00
Serge Guelton 4a27478a5b Python compat - print statement
Make sure all print statements are compatible with Python 2 and Python3 using
the `from __future__ import print_function` statement.

Differential Revision: https://reviews.llvm.org/D56249

llvm-svn: 350307
2019-01-03 14:11:33 +00:00
Philip Pfaffe b39a97c8f6 [NewPM] Port Msan
Summary:
Keeping msan a function pass requires replacing the module level initialization:
That means, don't define a ctor function which calls __msan_init, instead just
declare the init function at the first access, and add that to the global ctors
list.

Changes:
- Pull the actual sanitizer and the wrapper pass apart.
- Add a newpm msan pass. The function pass inserts calls to runtime
  library functions, for which it inserts declarations as necessary.
- Update tests.

Caveats:
- There is one test that I dropped, because it specifically tested the
  definition of the ctor.

Reviewers: chandlerc, fedor.sergeev, leonardchan, vitalybuka

Subscribers: sdardis, nemanjai, javed.absar, hiraditya, kbarton, bollu, atanasyan, jsji

Differential Revision: https://reviews.llvm.org/D55647

llvm-svn: 350305
2019-01-03 13:42:44 +00:00
Diogo N. Sampaio 25ae9a84c3 [NFC] Fix missing testfile change of rL350299
This file was missing on the patch

llvm-svn: 350302
2019-01-03 12:48:06 +00:00
Simon Pilgrim 44d6b25d2c [X86] Cleanup saturated add/sub tests
Use X86/X64 check prefixes
Use nounwind to reduce cfi noise

llvm-svn: 350301
2019-01-03 12:31:13 +00:00
Simon Pilgrim c2aadfaaad [SLPVectorizer] Flag ADD/SUB SSAT/USAT intrinsics trivially vectorizable (PR40123)
Enables SLP vectorization for the SSE2 PADDS/PADDUS/PSUBS/PSUBUS style intrinsics

llvm-svn: 350300
2019-01-03 12:18:23 +00:00
Diogo N. Sampaio 8786a946d8 [ARM] Add command-line option for SB
SB (Speculative Barrier) is only mandatory from 8.5
onwards but is optional from Armv8.0-A. This patch adds a command
line option to enable SB, as it was previously only possible to
enable by selecting -march=armv8.5-a.

This patch also renames FeatureSpecRestrict to FeatureSB.

Reviewed By: olista01, LukeCheeseman

Differential Revision: https://reviews.llvm.org/D55990

llvm-svn: 350299
2019-01-03 12:09:12 +00:00
Simon Pilgrim c5e22b29e4 [SLPVectorizer][X86] Add ADD/SUB SSAT/USAT tests (PR40123)
llvm-svn: 350297
2019-01-03 12:02:14 +00:00
Lama Saba c50a9b4166 [MachinePipeliner] Add missing header file to MachinePipeliner.h
llvm-svn: 350296
2019-01-03 11:56:27 +00:00
Simon Pilgrim d824f99a6c [X86] Add ADD/SUB SSAT/USAT vector costs (PR40123)
Costs for real SSE2 instructions

llvm-svn: 350295
2019-01-03 11:38:42 +00:00
Simon Pilgrim 55ea89305d [X86] Add ADD/SUB SSAT/USAT cost tests (PR40123)
llvm-svn: 350293
2019-01-03 11:29:24 +00:00
Piotr Sobczak 3abef8f9ea [AMDGPU] Change section name with metadata access
Summary:
The commit rL348922 introduced a means to set Metadata
section kind for a global variable, if its explicit section
name was prefixed with ".AMDGPU.metadata.".

This patch changes that prefix to ".AMDGPU.comment.",
as "metadata" in the section name might lead to
ambiguity with metadata used by AMD PAL runtime.

Change-Id: Idd4748800d6fe801441d91595fc21e5a4171e668

Reviewers: kzhuravl

Reviewed By: kzhuravl

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D56197

llvm-svn: 350292
2019-01-03 11:22:58 +00:00
Lama Saba 4d752a88e8 Resubmit rL345008 "Split MachinePipeliner code into header and cpp files"
The commit caused unclear failures in http://green.lab.llvm.org/green//job/lldb-cmake/
will revert if the error reappears

Differential Revision: https://reviews.llvm.org/D56084

llvm-svn: 350290
2019-01-03 10:03:54 +00:00
Markus Lavin 72b9deb21f [CodeGen] Skip over dbg-instr in twoaddr pass
A DBG_VALUE between a two-address instruction and a following COPY
would prevent rescheduleMIBelowKill optimization inside
TwoAddressInstructionPass.

Differential Revision: https://reviews.llvm.org/D55987

llvm-svn: 350289
2019-01-03 08:36:06 +00:00
Martin Storsjo 74e7d26090 [llvm-readobj] [COFF] Print the symbol index for relocations
There can be multiple local symbols with the same name (for e.g.
comdat sections), and thus the symbol name itself isn't enough
to disambiguate symbols.

Differential Revision: https://reviews.llvm.org/D56140

llvm-svn: 350288
2019-01-03 08:08:23 +00:00
Craig Topper 5ef47ad82e [X86] Add test cases for opportunities to use KTEST when check if the result of ANDing two mask registers is zero.
The test cases are constructed to avoid folding the AND into a masked compare operation.

Currently we emit a KAND and a KORTEST for these cases.

llvm-svn: 350287
2019-01-03 07:12:54 +00:00
Kristina Brooks bbbec9daa4 Don't go over 80 chars in MCStreamer.cpp. NFC.
Fixing up style issues around the area to prepare for
a larger differential.

llvm-svn: 350286
2019-01-03 06:06:38 +00:00
QingShan Zhang f24ec7bdd0 [Power9] Enable the Out-of-Order scheduling model for P9 hw
When switched to the MI scheduler for P9, the hardware is modeled as out of order.
However, inside the MI Scheduler algorithm, we still use the in-order scheduling model
as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer
the op. So, only when all the available instructions issued, the pending instruction
could be scheduled. That is not true for our P9 hw in fact.

This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is
picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017.

With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows:

x264_r: +6.95%
cactuBSSN_r: +6.94%
lbm_r: +4.11%
xz_r: -3.85%

And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. 

Reviewer: Nemanjai
Differential Revision: https://reviews.llvm.org/D55810

llvm-svn: 350285
2019-01-03 05:04:18 +00:00
Pete Cooper 697281df42 Teach ObjCARC optimizer about equivalent PHIs when eliminating autoreleaseRV/retainRV pairs
OptimizeAutoreleaseRVCall skips optimizing llvm.objc.autoreleaseReturnValue if it
sees a user which is llvm.objc.retainAutoreleasedReturnValue, and if they have
equivalent arguments (either identical or equivalent PHIs). It then assumes that
ObjCARCOpt::OptimizeRetainRVCall will optimize the pair instead.

Trouble is, ObjCARCOpt::OptimizeRetainRVCall doesn't know about equivalent PHIs
so optimizes in a different way and we are left with an unoptimized llvm.objc.autoreleaseReturnValue.

This teaches ObjCARCOpt::OptimizeRetainRVCall to also understand PHI equivalence.

rdar://problem/47005143

Reviewed By: ahatanak

Differential Revision: https://reviews.llvm.org/D56235

llvm-svn: 350284
2019-01-03 01:38:08 +00:00
Mike Spertus 252b7f3e4f Fix MSVC visualizer for PointerUnion4
Calculate which item is being held and then display it with the appropriate type. We also 
optimize the display of PointerUnion3 to take advantage of our knowing that the IntMask is
always 1 in PointerUnion types

llvm-svn: 350280
2019-01-03 00:52:54 +00:00
Robert Widmann 7882b283cd [LLVM-C] Expand LLVMRelocMode
Summary: Add read[only|write] PIC relocation models to the C API and teach the TargetMachine API about it.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D56187

llvm-svn: 350279
2019-01-03 00:33:44 +00:00
Daniel Sanders 157c43f823 [tblgen][disasm] Emit record names again when decoder conflicts occur.
And add a test for it.

llvm-svn: 350277
2019-01-03 00:14:33 +00:00
Teresa Johnson 0aa09c62cb [gold] emit assembly listing from gold plugin on LTO stage
Summary:
Sometimes it's useful to emit assembly after LTO stage to modify it manually. Emitting precodegen bitcode file (via save-temps plugin option) and then feeding it to llc doesn't always give the same binary as original.
This patch is simpler alternative to https://reviews.llvm.org/D24020.

Patch by Denis Bakhvalov.

Reviewers: mehdi_amini, tejohnson

Reviewed By: tejohnson

Subscribers: MaskRay, inglorion, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D56114

llvm-svn: 350276
2019-01-02 23:48:00 +00:00
Mike Spertus e59da0ba06 MSVC Visualizer for PointerUnion3
llvm-svn: 350275
2019-01-02 23:46:59 +00:00
Craig Topper df5304d8de [X86] Add load folding support to the custom isel we do for X86ISD::UMUL/SMUL.
The peephole pass isn't always able to fold the load because it can't commute the implicit usage of AL/AX/EAX/RAX.

llvm-svn: 350272
2019-01-02 23:24:08 +00:00
Craig Topper ce46bfa848 [X86] Add test cases to show that we fail to fold loads into i8 smulo and i8/i16/i32/i64 umulo lowering without the assistance of the peephole pass. NFC
llvm-svn: 350271
2019-01-02 23:24:03 +00:00
Wouter van Oortmerssen ad72f68501 [WebAssembly] made assembler parse block_type
Summary:
This was previously ignored and an incorrect value generated.

Also fixed Disassembler's handling of block_type.

Reviewers: dschuff, aheejin

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D56092

llvm-svn: 350270
2019-01-02 23:23:51 +00:00
Xin Tong 33e3b4b9b3 [ThinLTO] Scan all variants of vague symbol for reachability.
Summary:
Alias can make one (but not all) live, we still need to scan all others if this symbol is reachable
from somewhere else.

Reviewers: tejohnson, grimar

Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D56117

llvm-svn: 350269
2019-01-02 23:18:20 +00:00
Nikita Popov 41f5710328 [BDCE] Fix typo in test; NFC
shl by 32 is undefined. This was intended to be a shl by 31 as part
of a rotate sequence.

llvm-svn: 350265
2019-01-02 22:34:32 +00:00
Pete Cooper 8d58048024 Fix assert in ObjCARC optimizer when deleting retainBlock of null or undef.
The caller to EraseInstruction had this conditional:

    // ARC calls with null are no-ops. Delete them.
    if (IsNullOrUndef(Arg))

but the assert inside EraseInstruction only allowed ConstantPointerNull and not
undef or bitcasts.

This adds support for both of these cases.

rdar://problem/47003805

llvm-svn: 350261
2019-01-02 21:00:02 +00:00
Thomas Lively 88590e99f2 [WebAssembly][NFC] Elaborate on simd-noopt test comment
llvm-svn: 350260
2019-01-02 20:43:08 +00:00
Nikita Popov cc6ef7f153 [BDCE] Remove instructions without demanded bits
If an instruction has no demanded bits, remove it directly during BDCE,
instead of leaving it for something else to clean up.

Differential Revision: https://reviews.llvm.org/D56185

llvm-svn: 350257
2019-01-02 20:02:14 +00:00
Pawel Bylica cdebad8259 Git ignore CLion project configuration files. NFC
llvm-svn: 350256
2019-01-02 19:58:07 +00:00
Pawel Bylica 119aa8fa5f Format AggresiveInstCombine.cpp. NFC
llvm-svn: 350255
2019-01-02 19:51:46 +00:00
Mike Spertus 8cfefb5087 Fix MSVC PointerUnion visualizer
Differential Revision: https://reviews.llvm.org/D56186

llvm-svn: 350250
2019-01-02 19:26:50 +00:00
Craig Topper 9d4860ec4e [X86] Remove X86ISD::INC/DEC. Just select them from X86ISD::ADD/SUB at isel time
INC/DEC are pretty much the same as ADD/SUB except that they don't update the C flag.

This patch removes the special nodes and just pattern matches from ADD/SUB during isel if the C flag isn't being used.

I had to avoid selecting DEC is the result isn't used. This will become a SUB immediate which will turned into a CMP later by optimizeCompareInstr. This lead to the one test change where we use a CMP instead of a DEC for an overflow intrinsic since we only checked the flag.

This also exposed a hole in our RMW flag matching use of hasNoCarryFlagUses. Our root node for the match is a store and there's no guarantee that all the flag users have been selected yet. So hasNoCarryFlagUses needs to check copyToReg and machine opcodes, but it also needs to check for the pre-match SETCC, SETCC_CARRY, BRCOND, and CMOV opcodes.

Differential Revision: https://reviews.llvm.org/D55975

llvm-svn: 350245
2019-01-02 19:01:05 +00:00
Zachary Turner ba797b6dae [MS Demangler] Add a flag for dumping types without tag specifier.
Sometimes it's useful to be able to output demangled names without
tag specifiers like "struct", "class", etc.  This patch adds a
flag enabling this.

llvm-svn: 350241
2019-01-02 18:33:12 +00:00
Craig Topper 8dd7bd2cd7 [DAGCombiner] After performing the division by constant optimization for a DIV or REM node, replace the users of the corresponding REM or DIV node if it exists.
Currently we expand the two nodes separately. This gives DAG combiner an opportunity to optimize the expanded sequence taking into account only one set of users. When we expand the other node we'll create the expansion again, but might not be able to optimize it the same way. So the nodes won't CSE and we'll have two similarish sequences in the same basic block. By expanding both nodes at the same time we'll avoid prematurely optimizing the expansion until both the division and remainder have been replaced.

Improves the test case from PR38217. There may be additional opportunities after this.

Differential Revision: https://reviews.llvm.org/D56145

llvm-svn: 350239
2019-01-02 18:19:07 +00:00
Nico Weber da997b4aaf [gn build] Add fuzzers in llvm/tools that are needed for check-llvm
Also add a fuzzer() template for defining fuzzers that's similar to
add_llvm_fuzzer in the CMake build, and a build file for dependency
llvm/lib/FuzzMutate.

Also make `assert(defined(...` error strings a bit more self-consistent.

Differential Revision: https://reviews.llvm.org/D56194

llvm-svn: 350238
2019-01-02 18:13:14 +00:00
Craig Topper 44bcc824d3 [X86] Adding full coverage of MC encoding for the XOP and LWP ISAs.
Adding MC regressions tests to cover the XOP isa set.
This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952

Differential Revision: https://reviews.llvm.org/D41392

llvm-svn: 350237
2019-01-02 18:09:41 +00:00
Craig Topper 3109f3a4ab [LegalizeIntegerTypes] When promoting the result of an extract_vector_elt also promote the input type if necessary
By also promoting the input type we get a better idea for what scalar type to use. This can provide better results if the result of the extract is sign extended. What was previously happening is that the extract result would be legalized, sometime later the input of the sign extend would be legalized using the result of the extract. Then later the extract input would be legalized forcing a truncate into the input of the sign extend using a replace all uses. This requires DAG combine to combine out the sext/truncate pair. But sometimes we visited the truncate first and messed things up before the sext could be combined.

By creating the extract with the correct scalar type when we create legalize the result type, the truncate will be added right away. Then when the sign_extend input is legalized it will create an any_extend of the truncate which can be optimized by getNode to maybe remove the truncate. And then a sign_extend_inreg. Now DAG combine doesn't have to worry about getting rid of the extend.

This fixes the regression on X86 in D56156.

Differential Revision: https://reviews.llvm.org/D56176

llvm-svn: 350236
2019-01-02 17:58:30 +00:00
Craig Topper c562fae02b [DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them.
If x has multiple sign bits than it doesn't matter which one we extend from so we can sext from x's msb instead.

The X86 setcc-combine.ll changes are a little weird. It appears we ended up with a (sext_inreg (aext (trunc (extractelt)))) after type legalization. The sext_inreg+aext now gets optimized by this combine to leave (sext (trunc (extractelt))). Then we visit the trunc before we visit the sext. This ends up changing the truncate to an extractvectorelt from a bitcasted vector. I have a follow up patch to fix this.

Differential Revision: https://reviews.llvm.org/D56156

llvm-svn: 350235
2019-01-02 17:58:27 +00:00
Nico Weber a57ffac7c8 [gn build] Add build files for bugpoint-passes and LLVMHello plugins
These two plugins are loaded into a host process that contains all LLVM
symbols, so they don't link against anything. This required minor readjustments
to the tablegen() setup of IR.

Needed for check-llvm.

Differential Revision: https://reviews.llvm.org/D56204

llvm-svn: 350234
2019-01-02 17:38:22 +00:00
Nico Weber a3429b3981 [gn build] Add some llvm/tools: lli, lli-child-target
Also add build files for dependencies llvm/lib/ExecutionEngine/{Interpreter,Orc}

Needed for check-llvm.

Differential Revision: https://reviews.llvm.org/D56193

llvm-svn: 350226
2019-01-02 17:36:41 +00:00
Wei Mi ecc89b76cb [PowerPC] Remove SeenUse check when optimizing conditional branch in
PPCPreEmitPeephole pass.

PPCPreEmitPeephole will convert a BC to B when the conditional branch is
based on a constant CR by CRSET or CRUNSET. This is added in
https://reviews.llvm.org/rL343100.

When the conditional branch is known to be always taken, all branches will
be removed and a new unconditional branch will be inserted. However, when
SeenUse is false the original patch will not remove the branches, but still
insert the new unconditional branch, update the successors and create
inconsistent IR. Compiling the synthetic testcase included can show the
problem we run into.

The patch simply removes the SeenUse condition when adding branches into
InstrsToErase set.

Differential Revision: https://reviews.llvm.org/D56041

llvm-svn: 350223
2019-01-02 17:07:23 +00:00
Simon Pilgrim d8125726d5 [X86] Support SHLD/SHRD masked shift-counts (PR34641)
Peek through shift modulo masks while matching double shift patterns.

I was hoping to delay this until I could remove the X86 code with generic funnel shift matching (PR40081) but this will do for now.

Differential Revision: https://reviews.llvm.org/D56199

llvm-svn: 350222
2019-01-02 17:05:37 +00:00
Sanjay Patel eafd481aad [x86] add more tests for potential horizontal ops; NFC
As discussed in D56011 - add runs for AVX512 and tests with extra uses.

llvm-svn: 350221
2019-01-02 16:36:04 +00:00
Hal Finkel 4f2381440d [BasicAA] Support arbitrary pointer sizes (and fix an overflow bug)
Motivated by the discussion in D38499, this patch updates BasicAA to support
arbitrary pointer sizes by switching most remaining non-APInt calculations to
use APInt. The size of these APInts is set to the maximum pointer size (maximum
over all address spaces described by the data layout string).

Most of this translation is straightforward, but this patch contains a fix for
a bug that revealed itself during this translation process. In order for
test/Analysis/BasicAA/gep-and-alias.ll to pass, which is run with 32-bit
pointers, the intermediate calculations must be performed using 64-bit
integers. This is because, as noted in the patch, when GetLinearExpression
decomposes an expression into C1*V+C2, and we then multiply this by Scale, and
distribute, to get (C1*Scale)*V + C2*Scale, it can be the case that, even
through C1*V+C2 does not overflow for relevant values of V, (C2*Scale) can
overflow. If this happens, later logic will draw invalid conclusions from the
(base) offset value. Thus, when initially applying the APInt conversion,
because the maximum pointer size in this test is 32 bits, it started failing.
Suspicious, I created a 64-bit version of this test (included here), and that
failed (miscompiled) on trunk for a similar reason (the multiplication can
overflow).

After fixing this overflow bug, the first test case (at least) in
Analysis/BasicAA/q.bad.ll started failing. This is also a 32-bit test, and was
relying on having 64-bit intermediate values to have BasicAA return an accurate
result. In order to fix this problem, and because I believe that it is not
uncommon to use i64 indexing expressions in 32-bit code (especially portable
code using int64_t), it seems reasonable to always use at least 64-bit
integers. In this way, we won't regress our analysis capabilities (and there's
a command-line option added, so experimenting with this should be easy).

As pointed out by Eli during the review, there are other potential overflow
conditions that this patch does not address. Fixing those is left to follow-up
work.

Patch by me with contributions from Michael Ferguson (mferguson@cray.com).

Differential Revision: https://reviews.llvm.org/D38662

llvm-svn: 350220
2019-01-02 16:28:09 +00:00
Philip Pfaffe 6bc98ad7e8 Extend Module::getOrInsertGlobal to control the construction of the
GlobalVariable

Summary:
Extend Module::getOrInsertGlobal to accept a callback for creating a new
GlobalVariable if necessary instead of calling the GV constructor
directly using default arguments. Additionally overload
getOrInsertGlobal for the previous default behavior.

Reviewers: chandlerc

Subscribers: hiraditya, llvm-commits, bollu

Differential Revision: https://reviews.llvm.org/D56130

llvm-svn: 350219
2019-01-02 15:41:47 +00:00
Andrea Di Biagio 0682afbaee [MCA] Minor refactoring of method DefaultResourceStrategy::select. NFCI
Common code used by the default resource strategy to select pipeline resources
has been moved to an helper function.

The new selection logic has been slightly rewritten to get rid of a redundant
zero check on the `ReadyMask` value. Before this patch, method select internally
called function `PowerOf2Floor` to compute the next ready pipeline resource.
However, `PowerOf2Floor` forces an implicit (redundant) zero check on the input
value. By construction, `ReadyMask` can never be zero. This patch replaces the
call to `PowerOf2Floor` with an equivalent block of code which avoids the
redundant zero check. This gives a minor 3-3.5% speedup on a release build.

No functional change intended.

llvm-svn: 350218
2019-01-02 15:40:52 +00:00
Nico Weber b1ae8926fe [gn build] Add some llvm/tools: bugpoint, dsymutil, llvm-opt-report
Also add build file for dependency llvm/lib/OptRemarks.

Needed for check-llvm.

Differential Revision: https://reviews.llvm.org/D56192

llvm-svn: 350217
2019-01-02 12:43:56 +00:00
Nico Weber 0ed44da0e1 [gn build] Add some llvm/tools: llvm-c-test, llvm-cfi-verify, llvm-cov, llvm-cvtres
Needed for check-llvm.

Differential Revision: https://reviews.llvm.org/D56191

llvm-svn: 350216
2019-01-02 12:42:39 +00:00
Nico Weber f0ee87b4f3 [gn build] Add some llvm/tools: llvm-cxxdump, llvm-cxxfilt, llvm-cxxmap
Needed for check-llvm.

This is the last target reading llvm_install_binutils_symlinks.

Differential Revision: https://reviews.llvm.org/D56190

llvm-svn: 350215
2019-01-02 12:40:04 +00:00
Nico Weber b2139db1b0 [gn build] Add some llvm/tools: llvm-diff, llvm-dwp
Needed for check-llvm.

Differential Revision: https://reviews.llvm.org/D56189

llvm-svn: 350214
2019-01-02 12:39:05 +00:00
Nico Weber f71ed4ee7d [gn build] Add some llvm/tools: llvm-mca, llvm-mt
Also add build file for dependency llvm/lib/MCA.

Needed for check-llvm.

Differential Revision: https://reviews.llvm.org/D56166

llvm-svn: 350213
2019-01-02 12:37:52 +00:00
Nico Weber 768ae4274a [gn build] Add some llvm/tools: llvm-size, llvm-split, llvm-strings
Needed for check-llvm.

Differential Revision: https://reviews.llvm.org/D56164

llvm-svn: 350212
2019-01-02 12:34:57 +00:00
Nico Weber 7e6c653dbb [gn build] Add some llvm/tools: llvm-xray, sancov, sanstats, verify-uselistorder, yaml-bench
Also add build file for dependency llvm/lib/XRay.

Needed for check-llvm.

(yaml-bench is an llvm/util, not an llvm/tool.)

Differential Revision: https://reviews.llvm.org/D56163

llvm-svn: 350211
2019-01-02 12:32:49 +00:00
Piotr Sobczak 378131bae0 [AMDGPU] Handle OR as operand of raw load/store
Summary:
Use isBaseWithConstantOffset() which handles OR as an operand
to llvm.amdgcn.raw.buffer.load and llvm.amdgcn.raw.buffer.store.

Change-Id: Ifefb9dc5ded8710d333df07ab1900b230e33539a

Reviewers: nhaehnle, mareko, arsenm

Reviewed By: arsenm

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D55999

llvm-svn: 350208
2019-01-02 09:47:41 +00:00
Clement Courbet 176388c973 Revert rL350035 "[llvm-exegesis] Clustering: don't enqueue a point multiple times"
Let's discuss this on the review thread before submitting.

llvm-svn: 350207
2019-01-02 09:21:00 +00:00
Craig Topper f7cc7e3201 [X86] Remove the separate SMUL8/UMUL8 X86ISD opcodes by merging with SMUL/UMUL. Remove the second result from X86ISD::UMUL.
All of these use custom isel so we can pretty easily detect the differences in the custom code in X86ISelDAGToDAG. The ISD opcodes just need to express the desired semantics not the details of how they would be selected by isel. So unifying them lets us remove the special casing from lowering.

llvm-svn: 350206
2019-01-02 06:40:11 +00:00
Craig Topper d4db122483 [X86] Allow LowerSELECT and LowerBRCOND to directly lower i8 UMULO/SMULO.
These require a different X86ISD node to be created than i16/i32/i64. I guess no one wanted to add the special code for that except in LowerXALUO. But now LowerXALUO, LowerSELECT, and LowerBRCOND all use a common helper function so they all share the special code.

Unfortunately, there are no test changes because we seem to correct the miss in a DAG combine later. I did verify it manually using test cases from xmulo.ll

llvm-svn: 350205
2019-01-02 05:46:03 +00:00
Craig Topper 8969720787 [X86] Add i8/i16 smulo/umulo test cases where the overflow indication is used by a mask.
llvm-svn: 350204
2019-01-02 05:46:02 +00:00
Craig Topper 6f2feb8293 [X86] Remove KNL specific check prefix from xmulo.ll test. NFC
This was added at a time when i1 was a legal type with avx512f and there was a bug. i1 is no longer considered a legal type with avx512f so there should be no codegen difference.

llvm-svn: 350203
2019-01-02 05:46:00 +00:00
Sanjay Patel 654e6aabb9 [InstCombine] canonicalize raw IR rotate patterns to funnel shift
The final piece of IR-level analysis to allow this was committed with:
rL350188

Using the intrinsics should improve transforms based on cost models
like vectorization and inlining.

The backend should be prepared too, so we can now canonicalize more
sequences of shift/logic to the intrinsics and know that the end
result should be equal or better to the original code even if the
target does not have an actual rotate instruction.

llvm-svn: 350199
2019-01-01 21:51:39 +00:00
Craig Topper 00b390a000 [X86] Factor the core code out of LowerXALUO into a helper function. Use it in LowerBRCOND and LowerSELECT to avoid some duplicated code.
This makes it easier to keep the LowerBRCOND and LowerSELECT code in sync with LowerXALUO so they always pick the same operation for overflowing instructions.

This is inspired by the helper functions used by ARM and AArch64 for the same purpose.

The test change is because LowerSELECT was not in sync with LowerXALUO with regard to INC/DEC for SADDO/SSUBO.

llvm-svn: 350198
2019-01-01 19:34:11 +00:00
Robert Widmann db5b537f1e [LLVM-C] bool -> LLVMBool
llvm-svn: 350197
2019-01-01 19:03:37 +00:00
Robert Widmann 5d1dfa3eb6 [LLVM-C] Add Accessors for Discarding Value Names in the IR
Summary: Add accessors so the performance improvement from this setting is accessible to third parties.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D56179

llvm-svn: 350196
2019-01-01 18:56:51 +00:00
Craig Topper a728214203 [X86] Remove KNL specific check prefix from xaluo.ll test. NFC
This was added at a time when i1 was a legal type with avx512f and there was a bug. i1 is no longer considered a legal type with avx512f so there should be no codegen difference.

llvm-svn: 350195
2019-01-01 18:44:44 +00:00
Craig Topper 9478492a80 [X86] Add test cases to show where LowerSELECT doesn't select SADDO/SSUBO to INC/DEC, but LowerXALUOOp does. Leading to duplicate code.
When SADDO/SSUBO is used as a part of a condition, the X86 backend has to lower the instruction twice. One for the flags use and then once for the data use. These two selections should be kept in sync so they end up with one node providing the data and the flags. This doesn't seem to be happening for INC/DEC.

llvm-svn: 350194
2019-01-01 18:44:42 +00:00
Sanjay Patel 738a863648 [x86] move/rename helper for horizontal op codegen; NFC
Preliminary commit as suggested in D56011.

llvm-svn: 350193
2019-01-01 16:08:36 +00:00
Nikita Popov c5a023b624 [BDCE] Regenerate test checks; NFC
llvm-svn: 350190
2019-01-01 12:27:23 +00:00
Nikita Popov d4bf57be6b [BDCE] Remove -instsimplify from BDCE test; NFC
To make it more obvious which part of the transformation is carried
out by BDCE. Also drop the CHECK-IO lines which only run -instsimplify
as they don't really seem meaningful if the main check doesn't run
-instsimplify either.

llvm-svn: 350189
2019-01-01 10:17:35 +00:00
Nikita Popov bc9986e9ad Reapply "[BDCE][DemandedBits] Detect dead uses of undead instructions"
This (mostly) fixes https://bugs.llvm.org/show_bug.cgi?id=39771.

BDCE currently detects instructions that don't have any demanded bits
and replaces their uses with zero. However, if an instruction has
multiple uses, then some of the uses may be dead (have no demanded bits)
even though the instruction itself is still live. This patch extends
DemandedBits/BDCE to detect such uses and replace them with zero.
While this will not immediately render any instructions dead, it may
lead to simplifications (in the motivating case, by converting a rotate
into a simple shift), break dependencies, etc.

The implementation tries to strike a balance between analysis power and
complexity/memory usage. Originally I wanted to track demanded bits on
a per-use level, but ultimately we're only really interested in whether
a use is entirely dead or not. I'm using an extra set to track which uses
are dead. However, as initially all uses are dead, I'm not storing uses
those user is also dead. This case is checked separately instead.

The previous attempt to land this lead to miscompiles, because cases
where uses were initially dead but were later found to be live during
further analysis were not always correctly removed from the DeadUses
set. This is fixed now and the added test case demanstrates such an
instance.

Differential Revision: https://reviews.llvm.org/D55563

llvm-svn: 350188
2019-01-01 10:05:26 +00:00
Ayonam Ray e00606a1b2 Reversing the commit in revision 350186. Revision causes regression in 4
tests.

llvm-svn: 350187
2019-01-01 07:28:55 +00:00
Ayonam Ray c471bb2e67 Omit range checks from jump tables when lowering switches with unreachable
default

During the lowering of a switch that would result in the generation of a jump
table, a range check is performed before indexing into the jump table, for the
switch value being outside the jump table range and a conditional branch is
inserted to jump to the default block. In case the default block is
unreachable, this conditional jump can be omitted. This patch implements
omitting this conditional branch for unreachable defaults.

Review Reference: D52002

llvm-svn: 350186
2019-01-01 06:37:50 +00:00
Chen Zheng 4952e668f8 [InstCombine] canonicalize MUL with NEG operand
-X * Y --> -(X * Y)
X * -Y --> -(X * Y)

Differential Revision: https://reviews.llvm.org/D55961

llvm-svn: 350185
2019-01-01 01:09:20 +00:00
Nico Weber 745983ba0e [gn build] Add some llvm/tools: llvm-exegesis, llvm-extract, llvm-link
Also add build file for dependency llvm/lib/ExecutionEngine/MCJIT.

The exegesis stuff is pretty hairy and knows a lot about Target internals (in
general, not specifically in the GN build). I put the llvm-tblgen -gen-exegesis
call in llvm/tools/llvm-exegesis/lib/X86, instead of in llvm/lib/Target/X86
where it is in CMake land, and asked on D52932 why it's in that place in the
CMake build.

Needed for check-llvm.

Differential Revision: https://reviews.llvm.org/D56167

llvm-svn: 350184
2018-12-31 23:48:22 +00:00
Nico Weber a85ad5259f [gn build] Add some llvm/tools: llvm-rc, llvm-rtdyld
Also add build file for dependencies llvm/lib/ExecutionEngine,
llvm/lib/ExecutionEngine/RuntimeDyld.

Needed for check-llvm.

Differential Revision: https://reviews.llvm.org/D56165

llvm-svn: 350183
2018-12-31 23:32:15 +00:00
Simon Pilgrim 8b503c795e [X86] Add PR34641 masked shld/shrd test cases
llvm-svn: 350181
2018-12-31 19:46:18 +00:00
Craig Topper c25f1f8f17 [X86] Add additional RUN lines to prepare for D56156. NFC
llvm-svn: 350180
2018-12-31 19:09:32 +00:00
Craig Topper ed3ffae4a4 [SelectionDAG] Add SIGN_EXTEND_VECTOR_INREG support to computeKnownBits.
Differential Revision: https://reviews.llvm.org/D56168

llvm-svn: 350179
2018-12-31 19:09:30 +00:00
Craig Topper bb0873cf46 [X86] Add X86ISD::VSRAI to computeKnownBitsForTargetNode.
Differential Revision: https://reviews.llvm.org/D56169

llvm-svn: 350178
2018-12-31 19:09:27 +00:00
Simon Pilgrim f2b9d10477 Keep tablegen commands in alphabetical order. NFCI.
Mentioned on D56167.

llvm-svn: 350176
2018-12-31 14:51:53 +00:00
Michal Gorny 7343e24f78 [test] Fix propagating HOME envvar to unittests
Propagate HOME environment variable to unittests.  This is necessary
to fix test failures resulting from pw_home pointing to a non-existing
directory while being overriden with HOME.  Apparently Gentoo users
hit this sometimes when they override build directory for Portage.

Original bug report: https://bugs.gentoo.org/674088

Differential Revision: https://reviews.llvm.org/D56162

llvm-svn: 350175
2018-12-31 13:48:12 +00:00
Martin Storsjo 74d93f9b24 [AArch64] Accept "sve" as arch feature in assembler
Differential Revision: https://reviews.llvm.org/D56128

llvm-svn: 350174
2018-12-31 10:22:04 +00:00
Alexander Potapenko cea4f83371 [MSan] Handle llvm.is.constant intrinsic
MSan used to report false positives in the case the argument of
llvm.is.constant intrinsic was uninitialized.
In fact checking this argument is unnecessary, as the intrinsic is only
used at compile time, and its value doesn't depend on the value of the
argument.

llvm-svn: 350173
2018-12-31 09:42:23 +00:00
Craig Topper 802c4979ae [DAGCombiner] Add missing one use check on the shuffle in the bitcast(shuffle(bitcast(s0),bitcast(s1))) -> shuffle(s0,s1) transform.
Found while trying out some other changes so I don't really have a test case.

llvm-svn: 350172
2018-12-31 05:40:46 +00:00
Nico Weber fde9e0975f [gn build] Make `ninja check-clang` also run Clang's unit tests
Also add a build file for clang/lib/ASTMatchers/Dynamic, which is only needed
by tests (and clang/tools/extra).

Also make llvm/utils/gn/build/sync_source_lists_from_cmake.py check that every
CMakeLists.txt file below {lld,clang}/unittests has a corresponding BUILD.gn
file, so we notice if new test binaries get added (since the failure mode for
missing GN build files for tests is just the tests silently not running in the
GN build).

Also add a unittest() macro for defining unit test targets, and add a lengthy
comment there about where the unit test binaries go and why.

With this, the build files for //clang are complete.

Differential Revision: https://reviews.llvm.org/D56116

llvm-svn: 350171
2018-12-31 00:10:47 +00:00
Martin Storsjo 2018777836 [AArch64] Implement the .arch_extension directive
Differential Revision: https://reviews.llvm.org/D56131

llvm-svn: 350169
2018-12-30 21:06:32 +00:00
Martin Storsjo 0a5d5b1377 [llvm-objcopy] [COFF] Use Error/Expected returns instead of calling reportError. NFC.
Differential Revision: https://reviews.llvm.org/D55922

llvm-svn: 350168
2018-12-30 20:35:43 +00:00
Kang Zhang 9d78c60bf4 [PowerPC] Fix machine verify pass error for PATCHPOINT pseudo instruction that bad machine code
Summary:
For SDAG, we pretend patchpoints aren't special at all until we emit the code for the pseudo.
Then the verifier runs and it seems like we have a use of an undefined register (the register will 
be reserved later, but the verifier doesn't know that).

So this patch call setUsesTOCBasePtr before emit the code for the pseudo, so verifier can know 
X2 is a reserved register.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D56148

llvm-svn: 350165
2018-12-30 15:13:51 +00:00
David Bolvansky 90004149cc [NFC] Fixed extra semicolon warning
-This line, and those below, will be ignored--

M    lib/Support/Error.cpp

llvm-svn: 350162
2018-12-30 13:18:17 +00:00
Kang Zhang 4aa6453767 [PowerPC] Fix ADDE, SUBE do not know how to promote operator
Summary:
This patch is created to fix the Bugzilla bug 39815:
https://bugs.llvm.org/show_bug.cgi?id=39815 

This patch is to support promotion integer result for the instruction ADDE, SUBE.

Reviewed By: hfinkel

Differential Revision: https://reviews.llvm.org/D56119

llvm-svn: 350161
2018-12-30 07:48:09 +00:00
Craig Topper a32e353afa [X86] Don't mark SEXTLOAD from v4i8/v4i16/v8i8 as Custom on pre-sse4.1.
This seems to be getting in the way more than its helping. This does mean we stop scalarizing some cases, but I'm not convinced the scalarization was really better.

Some of the changes to vsel-cmp-load.ll are a regression but D56156 should fix it.

llvm-svn: 350159
2018-12-30 03:05:07 +00:00
Craig Topper f237ce159e [X86] Add custom type legalization for SIGN_EXTEND_VECTOR_INREG from 16i16/v32i8 to v4i64 when v4i64 needs splitting.
This allows us to sign extend to v4i32 first. And then share that extension to implement the final steps to v4i64 using a pcmpgt and punpckl and punpckh.

We already do something similar for SIGN_EXTEND with -x86-experimental-vector-widening-legalization.

llvm-svn: 350158
2018-12-30 02:30:34 +00:00
Nemanja Ivanovic 0dad994a10 [PowerPC][NFC] Macro for register set defs for the Asm Parser
We have some unfortunate code in the back end that defines a bunch of register
sets for the Asm Parser. Every time another class is needed in the parser, we
have to add another one of those definitions with explicit lists of registers.
This NFC patch simply provides macros to use to condense that code a little bit.

Differential revision: https://reviews.llvm.org/D54433

llvm-svn: 350156
2018-12-29 16:13:11 +00:00
Nemanja Ivanovic 0f7715afe1 [PowerPC] Complete the custom legalization of vector int to fp conversion
A recent patch has added custom legalization of vector conversions of
v2i16 -> v2f64. This just rounds it out for other types where the input vector
has an illegal (narrower) type than the result vector. Specifically, this will
handle the following conversions:

v2i8 -> v2f64
v4i8 -> v4f32
v4i16 -> v4f32

Differential revision: https://reviews.llvm.org/D54663

llvm-svn: 350155
2018-12-29 13:40:48 +00:00
Chen Zheng 763c8973bf [InstCombine] [NFC] update testcases for canonicalize MUL with NEG operand
llvm-svn: 350154
2018-12-29 12:18:15 +00:00
Nemanja Ivanovic 3c7ac649ec [PowerPC] Fix CR Bit spill pseudo expansion
The current CRBIT spill pseudo-op expansion creates a KILL instruction
that kills the CRBIT and defines the enclosing CR field. However, this
paints a false picture to the register allocator that all bits in the CR
field are killed so copies of other bits out of the field become dead and
removable.
This changes the expansion to preserve the KILL flag on the CRBIT as an
implicit use and to treat the CR field as an undef input.

Thanks to Hal Finkel for the review and Uli Weigand for implementation input.

Differential revision: https://reviews.llvm.org/D55996

llvm-svn: 350153
2018-12-29 11:43:54 +00:00
Simon Atanasyan a6424e7c4e [mips] Show an error on attempt to use 64-bit PC-relative relocation
The following code requests 64-bit PC-relative relocations unsupported
by MIPS ABI. Now it triggers an assertion. It's better to show an error
message.
```
foo:
  .quad bar - foo
```

llvm-svn: 350152
2018-12-29 10:10:02 +00:00
Simon Atanasyan b243d8d42a [mips] Show a regular error message on attempt to use one byte relocation
llvm-svn: 350151
2018-12-29 10:09:55 +00:00
Craig Topper 7bb1d50455 [X86] Add test case from PR38217. NFC
llvm-svn: 350150
2018-12-29 07:14:30 +00:00
Max Kazantsev 201534d753 Drop SE cache early because loop parent can change in LoopSimplifyCFG
llvm-svn: 350145
2018-12-29 04:26:22 +00:00
Heejin Ahn 4d98dfb67d [WebAssembly] Fix comments in ExplicitLocals (NFC)
llvm-svn: 350144
2018-12-29 02:42:04 +00:00
Richard Trieu a87b70d1db Add vtable anchor to classes.
llvm-svn: 350142
2018-12-29 02:02:13 +00:00
Craig Topper 0a6cec6f9f [X86] Don't mark SEXTLOAD v4i8->v4i64 and v8i8->v8i64 as custom under vector widening legalization.
This was tricking us into making these operations and then letting them get scalarized later. But I can't prove that the scalarized version is actually better.

llvm-svn: 350141
2018-12-29 01:17:11 +00:00
Anna Thomas bae11e7999 [UnrollRuntime] NFC: Updated exiting tests and added more tests
Added more tests for multiple exiting blocks to the LatchExit.
Today these cases are not supported. Patch to follow soon.

llvm-svn: 350135
2018-12-28 19:21:50 +00:00
Craig Topper f814d28eb3 [X86] Directly emit X86ISD::PMULUDQ from the ReplaceNodeResults handling of v2i8/v2i16/v2i32 multiply.
Previously we emitted a multiply and some masking that was supposed to matched to PMULUDQ, but the masking could sometimes be removed before we got a chance to match it. So instead just emit the PMULUDQ directly.

Remove the DAG combine that was added when the ReplaceNodeResults code was originally added. Add a new DAG combine to avoid regressions in shrink_vmul.ll

Some of the shrink_vmul.ll test cases now pick PMULUDQ instead of PMADDWD/PMULLD, but I think this should be an improvement on most CPUs.

I think all of this can go away if/when we switch to -x86-experimental-vector-widening-legalization

llvm-svn: 350134
2018-12-28 19:19:39 +00:00
Anna Thomas 98743fa77a [UnrollRuntime] NFC: Add comment and verify LCSSA
Added -verify-loop-lcssa to test cases.
Updated comments in ConnectProlog.

llvm-svn: 350131
2018-12-28 18:52:16 +00:00
Diogo N. Sampaio 9123f82cc4 [AArch64] Add command-line option for SB
SB (Speculative Barrier) is only mandatory from 8.5
onwards but is optional from Armv8.0-A. This patch adds a command
line option to enable SB, as it was previously only possible to
enable by selecting -march=armv8.5-a.

This patch also moves to FeatureSB the old FeatureSpecRestrict.

Reviewers: pbarrio, olista01, t.p.northover, LukeCheeseman	

Differential Revision: https://reviews.llvm.org/D55921

llvm-svn: 350126
2018-12-28 17:14:58 +00:00
Aleksandr Urakov d5b685a9b2 [CodeView] Extend the `MemberAttributes` interface with the `isStatic` method
Summary:
This patch extends the MemberAttributes interface with the isStatic method.
It is needed for D56126.

Reviewers: zturner, rnk

Reviewed By: zturner

Differential Revision: https://reviews.llvm.org/D56127

llvm-svn: 350125
2018-12-28 17:03:24 +00:00
Dmitry Preobrazhensky ddac5c9ba5 [AMDGPU][MC][DOC] Updated AMD GPU assembler description.
Minor bugfixing and improvements.

See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572

llvm-svn: 350120
2018-12-28 11:48:23 +00:00
Max Kazantsev 8f70c9bf49 [NFC] Add failing test on LCSSA form preservation of LoopSimplifyCFG
llvm-svn: 350119
2018-12-28 10:43:37 +00:00
Hiroshi Inoue 1ea98f040e [PowerPC] handle ISD:TRUNCATE in BitPermutationSelector
This is the last one in a series of patches to support better code generation for bitfield insert.
BitPermutationSelector already support ISD::ZERO_EXTEND but not TRUNCATE.
This patch adds support for ISD:TRUNCATE in BitPermutationSelector.

For example of this test case, 
struct s64b {
  int a:4;
  int b:16;
  int c:24;
};
void bitfieldinsert64b(struct s64b *p, unsigned char v) {
  p->b = v;
}

the selection DAG loos like:

t14: i32,ch = load<(load 4 from %ir.0)> t0, t2, undef:i64
       t18: i32 = and t14, Constant:i32<-1048561>
            t4: i64,ch = CopyFromReg t0, Register:i64 %1
          t22: i64 = AssertZext t4, ValueType:ch:i8
        t23: i32 = truncate t22
      t16: i32 = shl nuw nsw t23, Constant:i32<4>
    t19: i32 = or t18, t16
  t20: ch = store<(store 4 into %ir.0)> t14:1, t19, t2, undef:i64

By handling truncate in the BitPermutationSelector, we can use information from AssertZext when selecting t19 and skip the mask operation corresponding to t18.
So the generated sequences with and without this patch are

without this patch
	rlwinm 5, 5, 0, 28, 11 # corresponding to t18
	rlwimi 5, 4, 4, 20, 27
with this patch
	rlwimi 5, 4, 4, 12, 27

Differential Revision: https://reviews.llvm.org/D49076

llvm-svn: 350118
2018-12-28 08:00:39 +00:00
Max Kazantsev 530ff8f3cc Temporarily disable term folding in LoopSimplifyCFG, add tests
llvm-svn: 350117
2018-12-28 06:22:39 +00:00
Max Kazantsev 80e4b40f3e [LoopSimplifyCFG] Delete dead blocks in RPO
Deletion of dead blocks in arbitrary order may lead to failure
of assertion in `DeleteDeadBlock` that requires that we have
deleted all predecessors before we can delete the current block.
We should instead delete them in RPO order.

llvm-svn: 350116
2018-12-28 06:08:51 +00:00
QingShan Zhang f2d9df61c7 [PowerPC] Remove the implicit use of the register if it is replaced by Imm
If we are changing the MI operand from Reg to Imm, we need also handle its implicit use if have.

Differential Revision: https://reviews.llvm.org/D56078

llvm-svn: 350115
2018-12-28 03:38:09 +00:00
Zi Xuan Wu 5187444345 [NFC] clang-format functions related to r350113
llvm-svn: 350114
2018-12-28 02:45:17 +00:00
Zi Xuan Wu a02a3feecf [PowerPC] Fix assert from machine verify pass that atomic pseudo expanding causes mismatched register class
For atomic value operand which less than 4 bytes need to be masked. 
And the related operation to calculate the newvalue can be done in 32 bit gprc. 
So just use gprc for mask and value calculation.

Differential Revision: https://reviews.llvm.org/D56077

llvm-svn: 350113
2018-12-28 02:12:55 +00:00
Chen Zheng 5ede950df9 [PowerPC] fix register class after converting X-FORM instruction to D-FORM instruction
Differential Revision: https://reviews.llvm.org/D55806

llvm-svn: 350111
2018-12-28 01:02:35 +00:00
Chandler Carruth 05b5bd8b85 [CallSite removal] Add and flesh out APIs on the new `CallBase` base class that previously were only available on the `CallSite` wrapper.
Summary:
This will make migrating code easier and generally seems like a good collection
of API improvements.

Some of these APIs seem like more consistent / better naming of existing
ones. I've retained the old names for migration simplicit and am just
adding the new ones in this commit. I'll try to garbage collect these
once CallSite is gone.

Subscribers: sanjoy, mcrosier, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D55638

llvm-svn: 350109
2018-12-27 23:40:17 +00:00
Nico Weber c38717ff84 [gn build] Add check-clang target and make it work
With this, check-clang runs and passes all of clang's lit tests. It doesn't run
any of its unit tests yet.

Like with check-lld, running just ninja -C out/gn will build all prerequisites
needed to run tests, but it won't run the tests (so that the build becomes
clean after one build). Running ninja -C out/gn check-clang will build
prerequisites if needed and run the tests. The check-clang target never becomes
clean and runs tests every time.

Differential Revision: https://reviews.llvm.org/D56095

llvm-svn: 350108
2018-12-27 23:38:58 +00:00
Craig Topper 787ad92bf6 [X86] Remove check that avoids creating PMULDQ with illegal types. Rely on SplitOpsAndApply to legalize it.
Create PMULDQ/PMULUDQ as long as the number of elements is a power of 2.

This seems to give some improvements in our ability to use SimplifyDemandedBits.

llvm-svn: 350084
2018-12-27 03:37:04 +00:00
Craig Topper a8f07e51f9 [X86] Factor the core code out of LowerSETCC into a helper that can create CMP/BT/PTEST/KORTEST etc. without making an X86ISD::SETCC node. NFCI
Make each of the helper functions only return their comparison node and the condition code. Leave X86ISD::SETCC creation to the LowerSETCC function itself.

Looking into whether we can use this code directly in BRCOND and SELECT lowering instead of going through LowerSETCC which creates an X86ISD::SETCC node we need to look through.

llvm-svn: 350082
2018-12-27 01:50:40 +00:00
Craig Topper 4f1ef9fc0f [X86] Merge getBitTestCondition into LowerAndToBT. Don't create X86ISD::SETCC node in the merged function. NFCI
Only one of the 3 callers of LowerAndToBT need the SETCC node. Two of them have to look through it to find the operands they really need. Instead create it after the one call that needs it.

LowerAndToBT now returns both the BT node and the X86 specific condition code separately.

llvm-svn: 350081
2018-12-27 01:50:38 +00:00
Wouter van Oortmerssen f227621036 [WebAssembly] Added basic support for if/else/end_if in MC layer.
Summary:
These instructions are currently unused in our backend, but for
completeness it is good to support them, so they can be used with
the assembler in hand-written code.

Tests are very basic, signature support missing much like other blocks.

Reviewers: dschuff, aheejin

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D55973

llvm-svn: 350079
2018-12-26 22:55:26 +00:00
Wouter van Oortmerssen 29c6ce5879 [WebAssembly] Make assembler check for proper nesting of control flow.
Summary:
It does so using a simple nesting stack, and gives clear errors upon
violation. This is unique to wasm, since most CPUs do not have
any nested constructs.

Had to add an end of file check to the general assembler for this.

Note: if/else/end instructions are not currently supported in our
tablegen defs, so these tests will be enabled in a follow-up.
They already pass the nesting check.

Reviewers: dschuff, aheejin

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D55797

llvm-svn: 350078
2018-12-26 22:46:18 +00:00
Sylvestre Ledru 82f43aab21 manpages: Update the URL for https
llvm-svn: 350077
2018-12-26 22:34:44 +00:00
Heejin Ahn ce1d50f9d7 [WebAssembly] Delete an unnecessary line in RegStackify
`OneUseInst` is set outside of the loop before and `OneUse` does not
change throughout the loop, so this line is not necessary.

llvm-svn: 350076
2018-12-26 22:33:35 +00:00
Heejin Ahn 99d3946398 [WebAssembly] Fix typos in comments in RegStackify (NFC)
llvm-svn: 350075
2018-12-26 22:27:46 +00:00
Craig Topper c9a6000755 [LoopIdiomRecognize] Add CTTZ support
Summary:
Existing LIR recognizes CTLZ where shifting input variable right until it is zero. (Shift-Until-Zero idiom)

This commit:
1. Augments Shift-Until-Zero idiom to recognize CTTZ where input variable is shifted left.
2. Prepare for BitScan idiom recognition.

Patch by Yuanfang Chen (tabloid.adroit)

Reviewers: craig.topper, evstupac

Reviewed By: craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D55876

llvm-svn: 350074
2018-12-26 21:59:48 +00:00
Reid Kleckner c168c6f86f [codeview] Check if this 'this' type of a method is a pointer
Fixes crash reported after r347354 for frontends that don't always emit
'this' pointers for methods. Now we will silently produce debug info
that makes functions like this look like static methods, which seems
reasonable.

llvm-svn: 350073
2018-12-26 21:52:17 +00:00
Justin Lebar 49fac56ea3 [NVPTX] Allow libcalls that are defined in the current module.
The patch adds a possibility to make library calls on NVPTX.

An important thing about library functions - they must be defined within
the current module. This basically should guarantee that we produce a
valid PTX assembly (without calls to not defined functions). The one who
wants to use the libcalls is probably will have to link against
compiler-rt or any other implementation.

Currently, it's completely impossible to make library calls because of
error LLVM ERROR: Cannot select: i32 = ExternalSymbol '...'. But we can
lower ExternalSymbol to TargetExternalSymbol and verify if the function
definition is available.

Also, there was an issue with a DAG during legalisation. When we expand
instruction into libcall, the inner call-chain isn't being "integrated"
into outer chain. Since the last "data-flow" (call retval load) node is
located in call-chain earlier than CALLSEQ_END node, the latter becomes
a leaf and therefore a dead node (and is being removed quite fast).
Proposed here solution relies on another data-flow pseudo nodes
(ProxyReg) which purpose is only to keep CALLSEQ_END at legalisation and
instruction selection phases - we remove the pseudo instructions before
register scheduling phase.

Patch by Denys Zariaiev!

Differential Revision: https://reviews.llvm.org/D34708

llvm-svn: 350069
2018-12-26 19:12:31 +00:00
Simon Pilgrim a8ff77bb34 [AMDGPU] Regenerate i64 shift tests.
To show codegen diff due to a future SimplifyDemandedBits patch.

llvm-svn: 350065
2018-12-26 12:09:10 +00:00
Max Kazantsev 28298e9647 [NFC] Use utility function for guards detection
llvm-svn: 350064
2018-12-26 08:22:25 +00:00
Petar Avramovic 09dff33349 [MIPS GlobalISel] Select G_SELECT
Add widen scalar for type index 1 (i1 condition) for G_SELECT.
Select G_SELECT for pointer, s32(integer) and smaller low level
types on MIPS32.

Differential Revision: https://reviews.llvm.org/D56001

llvm-svn: 350063
2018-12-25 14:42:30 +00:00
Max Kazantsev 9b25bf3960 [NFC] Reuse variables instead of re-calling getParent
llvm-svn: 350062
2018-12-25 07:20:06 +00:00
Kang Zhang d501a1e596 [PowerPC] Fix the bug of ISD::ADDE to set its second return type to glue
Summary:
This patch is to fix the bug imported by rL341634.
In above submit , the the return type of ISD::ADDE is 
14224: SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i64), 
but in fact, the second return type of ISD::ADDE should be 
MVT::Glue not MVT::i64.

Reviewed By: hfinkel

Differential Revision: https://reviews.llvm.org/D55977

llvm-svn: 350061
2018-12-25 03:29:51 +00:00
Nico Weber 495b9e0eb7 [gn build] Make NOSORT line actually work
GN wants the NOSORT line to be the first line of a comment block, not the last
line.

I sent https://gn-review.googlesource.com/c/gn/+/3560 to support having it in
the last line too, but since it will be a while until everyone has that change
even if it's expected, use the form that works today.

Differential Revision: https://reviews.llvm.org/D56065

llvm-svn: 350060
2018-12-24 23:06:29 +00:00
Craig Topper 0229da8f07 [X86] Use GetDemandedBits to simplify the operands of PMULDQ/PMULUDQ.
This is an alternative to what I attempted in D56057.

GetDemandedBits is a special version of SimplifyDemandedBits that allows simplifications even when the operand has other uses. GetDemandedBits will only do simplifications that allow a node to be bypassed. It won't create new nodes or alter any of the other users.

I had to add support for bypassing SIGN_EXTEND_INREG to GetDemandedBits.

Based on a patch that Simon Pilgrim sent me in email.

Fixes PR40142.

llvm-svn: 350059
2018-12-24 19:40:20 +00:00
Craig Topper 6356ad940b [X86] Add test cases for PR40142. NFC
llvm-svn: 350058
2018-12-24 19:40:17 +00:00
Eugene Leviant 4dc3a3f746 [HWASAN] Instrument memorty intrinsics by default
Differential revision: https://reviews.llvm.org/D55926

llvm-svn: 350055
2018-12-24 16:02:48 +00:00
Nico Weber ba9d5cf961 [gn build] Add build files for clang/tools/{c-arcmt-test,c-index-test} and their dependency clang/tools/libclang
libclang is somewhat incomplete. It's just enough to get check-clang to pass,
but that requires it to be pretty complete. The biggest thing is that it's not
built as a shared library on Linux. The libclang/BUILD.gn file has a comment
with details on what else is missing.

Differential Revision: https://reviews.llvm.org/D56059

llvm-svn: 350054
2018-12-24 15:45:04 +00:00
Roman Lebedev 629d9804e3 ReleaseNotes: X86 Target: bdver2 sched model was added (D52779)
llvm-svn: 350053
2018-12-24 12:12:26 +00:00
Max Kazantsev 0b455c2b71 Revert rL350048 and rL350050
These patches have broken almost all buildbots on test
DebugInfo/X86/addr_comments.ll. Reverting to green.

llvm-svn: 350052
2018-12-24 10:30:04 +00:00
David Blaikie 5353e64935 Fix build - follow-up to r350048 which broke headerless (v4) address pool
llvm-svn: 350050
2018-12-24 07:56:40 +00:00
Max Kazantsev edabb9ae56 [LoopSimplifyCFG] Delete dead exiting edges
This patch teaches LoopSimplifyCFG to remove dead exiting edges
from loops.

Differential Revision: https://reviews.llvm.org/D54025
Reviewed By: fedor.sergeev

llvm-svn: 350049
2018-12-24 07:41:33 +00:00
David Blaikie e20bf9ab91 DebugInfo: Use assembly label arithmetic for address pool size for easier reading/editing
llvm-svn: 350048
2018-12-24 07:35:10 +00:00
David Blaikie d671eb7e7c DebugInfo: Add assembly comments for debug_addr contribution header fields
llvm-svn: 350047
2018-12-24 07:09:50 +00:00
David Blaikie b917c3a41a llvm-dwarfdump: Skip address index info (and dump only the address, if found) when non-verbose dumping addrx forms
There's a few bugs here still - demonstrated with FIXITs in the test.

llvm-svn: 350046
2018-12-24 06:52:31 +00:00
Max Kazantsev 347c583772 Return "[LoopSimplifyCFG] Delete dead in-loop blocks"
The underlying bug that caused the revert should be fixed by rL348567.

Differential Revision: https://reviews.llvm.org/D54023

llvm-svn: 350045
2018-12-24 06:06:17 +00:00
George Burgess IV 7e12875c89 [LoopIdioms] More LocationSize::precise annotations; NFC
Both of these places reference memset-like loops. Memset is precise.

Trying to keep these patches super small so they're easily post-commit
verifiable, as requested in D44748.

llvm-svn: 350044
2018-12-24 05:55:50 +00:00
Craig Topper 0adc3fe9e7 [X86] Remove unused variables left after r350041. NFC
llvm-svn: 350043
2018-12-24 05:45:45 +00:00
George Burgess IV 610c76534f [SelectionDAGBuilder] Use ::precise LocationSizes; NFC
More migration so we can disable the implicit int -> LocationSize
conversion.

All of these are either scatter/gather'ed vector instructions, or direct
loads. Hence, they're all precise.

Perhaps if we see way more getTypeStoreSize calls, we can make a
getTypeStoreLocationSize (or similar) as a wrapper that applies this
::precise. Doesn't appear that it's a good idea to make getTypeStoreSize
return a LocationSize itself, however.

llvm-svn: 350042
2018-12-24 05:34:21 +00:00
Craig Topper d8217b23ff [X86] Move the optimization that turns 'CMP (AND+IMM64), 0' into SRL/SHL+TEST to X86ISelDAGToDAG.
This cleans more code out of EmitTest.

llvm-svn: 350041
2018-12-24 05:27:13 +00:00
Craig Topper 5eb5e2bc89 [X86] Autogenerate complete checks. NFC
llvm-svn: 350039
2018-12-24 01:59:31 +00:00
Craig Topper e8c50fc6af [X86] Remove the ANDN check from EmitTest.
Remove the TESTmr isel patterns and add another postprocessing combine for TESTrr+ANDrm->TESTmr. We already have a postprocessing combine for TESTrr+ANDrr->TESTrr. With this we can give ANDN a chance to match first. And clean it up during post processing if we ended up with just a regular AND.

This is another step towards my plan to gut EmitTest and do more flag handling during isel matching or by using optimizeCompare.

llvm-svn: 350038
2018-12-24 01:10:13 +00:00
Fangrui Song cd93d7ef43 [llvm-exegesis] Clustering: don't enqueue a point multiple times
Summary:
SetVector uses both DenseSet and vector, which is time/memory inefficient. The points are represented as natural numbers so we can replace the DenseSet part by indexing into a vector<char> instead.

Don't cargo cult the pseudocode on the wikipedia DBSCAN page. This is a standard BFS style algorithm (the similar loops have been used several times in other LLVM components): every point is processed at most once, thus the queue has at most NumPoints elements. We represent it with a vector and allocate it outside of the loop to avoid allocation in the loop body.

We check `Processed[P]` to avoid enqueueing a point more than once, which also nicely saves us a `ClusterIdForPoint_[Q].isUndef()` check.

Many people hate the oneshot abstraction but some favor it, therefore we make a compromise, use a lambda to abstract away the neighbor adding process.

Delete the comment `assert(Neighbors.capacity() == (Points_.size() - 1));` as it is wrong.

llvm-svn: 350035
2018-12-23 20:48:52 +00:00
Sanjay Patel 93f1074677 [DAGCombiner] limit shuffle to extend transform (PR40146)
It's dangerous to knowingly create an illegal vector type
no matter what stage of combining we're in.

This prevents the missed folding/scalarization seen in:
https://bugs.llvm.org/show_bug.cgi?id=40146

llvm-svn: 350034
2018-12-23 20:48:31 +00:00
Sanjay Patel 9e5588e1df [x86] add test for vector shuffle --> extend transform (PR40146); NFC
llvm-svn: 350033
2018-12-23 20:36:52 +00:00
Sanjay Patel 9933574ac3 [DAGCombiner] allow hoisting vector bitwise logic ahead of extends
llvm-svn: 350032
2018-12-23 19:58:16 +00:00
Sanjay Patel 8bc612f63b [x86] add tests for vector extend + logic ops; NFC
llvm-svn: 350031
2018-12-23 18:37:44 +00:00
Nico Weber 0c07407bb5 [gn build] Add build files for clang/tools/{arcmt-test,clang-check,clang-func-mapping}
Needed for check-clang.

Differential Revision: https://reviews.llvm.org/D56056

llvm-svn: 350026
2018-12-23 14:19:53 +00:00
Nico Weber 6df17c679d [gn build] Add build files for clang/tools/{clang-refactor,clang-rename}, clang/utils/hmaptool, clang/lib/Tooling/Refactoring
Needed for check-clang.

Differential Revision: https://reviews.llvm.org/D56055

llvm-svn: 350025
2018-12-23 14:17:13 +00:00
Nico Weber 9f20b9a202 [gn build] Add build files for clang/tools/{clang-diff,clang-import-test,diagtool and clang/lib/Tooling, clang/lib/Tooling/ASTDiff
Needed for check-clang.

Differential Revision: https://reviews.llvm.org/D56054

llvm-svn: 350024
2018-12-23 14:15:26 +00:00
Simon Atanasyan 4553cdafe1 [ORC] Rename register in the OrcMips64 resolver code comments. NFC
The `fp` and `s8` register names are synonyms. But `fp` better reflects
a purpose of the register.

llvm-svn: 350023
2018-12-23 12:05:04 +00:00
Simon Atanasyan 15b68b87d5 [ORC] clang-format OrcMips32 and OrcMips64 code. NFC
llvm-svn: 350022
2018-12-23 12:05:00 +00:00
Simon Atanasyan da29981707 [ORC] Remove redundant instruction from MIPS resolver code. NFC
It's redundant to restore the `$a3` register twice.

llvm-svn: 350021
2018-12-23 12:04:55 +00:00
George Burgess IV 5e4a03a089 [MemCpyOpt] Use LocationSize instead of ints; NFC
Trying to keep these patches super small so they're easily post-commit
verifiable, as requested in D44748.

srcSize is derived from the size of an alloca, and we quit out if the
size of that is > the size of the thing we're copying to. Hence, we
should always copy everything over, so these sizes are precise.

Don't make srcSize itself a LocationSize, since optionality isn't
helpful, and we do some comparisons against other sizes elsewhere in
that function.

llvm-svn: 350019
2018-12-23 06:40:39 +00:00
Craig Topper 006bac6880 [X86] Return false from hasAndNotCompare if the comparision value is a constant.
We won't end up using an ANDN instruction in this case so we should generate the same code we do for pre-BMI targets.

llvm-svn: 350018
2018-12-23 05:52:55 +00:00
George Burgess IV 69952979da [MemoryLocation] Use LocationSize instead of ints; NFC
Trying to keep these patches super small so they're easily post-commit
verifiable, as requested in D44748.

This one sadly isn't *super* small, but all of the changes here are
either to:
- libfuncs that are passed a constant size (memcpy, memset, ...)
- instructions that store/load a constant size

So they have to be precise

llvm-svn: 350017
2018-12-23 03:36:44 +00:00
George Burgess IV 8c5413f3f7 [Loads] Use LocationSize instead of ints; NFC
Keeping these patches super small so they're easily post-commit
verifiable, as requested in D44748.

This tries to find literal loads/stores of the given type, so this has
to be precise.

llvm-svn: 350016
2018-12-23 03:10:56 +00:00
George Burgess IV 1329cf1791 [Lint] Use LocationSize instead of ints; NFC
Keeping these patches super small so they're easily post-commit
verifiable, as requested in D44748.

llvm-svn: 350015
2018-12-23 02:50:08 +00:00
George Burgess IV 685e781d55 [AAEval] Use LocationSize instead of ints; NFC
Keeping these patches super small so they're easily post-commit
verifiable, as requested in D44748.

llvm-svn: 350014
2018-12-23 02:39:58 +00:00
Craig Topper 3cc92a28ce [X86] Fix an old FIXME about folding the zero constant into the OR instruction we use for sequentially consistent fence in 32-bit mode without SSE2.
llvm-svn: 350013
2018-12-23 01:54:43 +00:00
Craig Topper dfb8a427ff [X86] Autogenerate complete checks. NFC
llvm-svn: 350012
2018-12-23 01:54:41 +00:00
David Blaikie 2a38c17b34 DebugInfo: Accurately propagate the section used by a relocation when accessing ranges defined by low/high_pc
This is difficult/not possible to test in LLVM, but is visible as a
crash in LLD when parsing DWARF to generate gdb-index.

This function is called by llvm-dwarfdump when parsing high_pc for
non-verbose output (to print the actual high_pc rather than the low_pc
relative value), but in that case llvm-dwarfdump doesn't print section
names (if it did, it would hit this problem).

We could add some other features to llvm-dwarfdump to expose this, but
nothing really springs to my mind. I will add a test to lld, though.

llvm-svn: 350010
2018-12-22 22:20:40 +00:00
David Blaikie 25179613f6 llvm-dwarfdump: Dump the section name/number for addr attributes
llvm-svn: 350009
2018-12-22 20:34:58 +00:00
George Burgess IV 640be69249 [Analysis] More LocationSize cleanup; NFC
Keeping these patches super small so they're easily post-commit
verifiable, as requested in D44748.

llvm-svn: 350008
2018-12-22 18:23:21 +00:00
George Burgess IV a2ab74837f [Analysis] s/uint64_t/LocationSize; NFC
Let the gradual cleanup from D44748 continue. :)

llvm-svn: 350007
2018-12-22 17:42:08 +00:00
Sanjay Patel 4b537aaf6d [DAGCombiner] allow narrowing of add followed by truncate
trunc (add X, C ) --> add (trunc X), C'

If we're throwing away the top bits of an 'add' instruction, do it in the narrow destination type.
This makes the truncate-able opcode list identical to the sibling transform done in IR (in instcombine).

This change used to show regressions for x86, but those are gone after D55494. 
This gets us closer to deleting the x86 custom function (combineTruncatedArithmetic) 
that does almost the same thing.

Differential Revision: https://reviews.llvm.org/D55866

llvm-svn: 350006
2018-12-22 17:10:31 +00:00
Sanjay Patel 52c02d70e2 [x86] add load fold patterns for movddup with vzext_load
The missed load folding noticed in D55898 is visible independent of that change 
either with an adjusted IR pattern to start or with AVX2/AVX512 (where the build 
vector becomes a broadcast first; movddup is not produced until we get into isel 
via tablegen patterns).

Differential Revision: https://reviews.llvm.org/D55936

llvm-svn: 350005
2018-12-22 16:59:02 +00:00
Roman Lebedev da1df56e5d NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. a/c/d) with trunc (PR36419)
llvm-svn: 350000
2018-12-22 10:38:05 +00:00
Roman Lebedev c90611db06 [NFC][CodeGen][X86][AArch64] Bit extract: add nounwind attr to drop .cfi noise
Forgot about that.

llvm-svn: 349999
2018-12-22 09:58:13 +00:00
Roman Lebedev 29d8af283a [NFC][CodeGen][X86][AArch64] Tests for bit extract (pat. b) with trunc (PR36419)
@bextr64_32_b1 is extracted from hotpath of real-world code
(RawSpeed BitStream<>::peekBitsNoFill()) after `clang -O3`.

@bextr64_32_b2/@bextr64_32_b0 is the same pattern,
but with trunc done last, showing how i think it can be handled:
https://rise4fun.com/Alive/K4B
https://rise4fun.com/Alive/qC9

It is possible that middle-end should do some of this, too.

https://bugs.llvm.org/show_bug.cgi?id=36419

llvm-svn: 349998
2018-12-22 09:40:14 +00:00
David Blaikie 9efb0153f0 llvm-dwarfdump: Remove extraneous space between '(' and 'indexed'
When dumping string or address indexes

llvm-svn: 349997
2018-12-22 08:43:08 +00:00
David Blaikie c04d2bf22a llvm-dwarfdump: Print the section name/number for addr_index attributes
(addr attributes coming shortly)

llvm-svn: 349996
2018-12-22 08:33:55 +00:00
David Blaikie 87ae80fb2f DebugInfo: Refactor named section dumping into a reusable helper
Currently the section name (& possibly number) is only printed on
addresses in ranges - but no reason it couldn't also be displayed on
other addresses (like low/high PC).

Refactor in that direction by pulling out the section lookup and name
ambiguity dumping logic into a reusable helper.

llvm-svn: 349995
2018-12-22 08:23:10 +00:00