604e142844
Combine these together - should probably have some text associated
...
that says what why what we just asserted is wrong.
llvm-svn: 116333
2010-10-12 19:44:17 +00:00
eb7b91d417
Mark variable 'NoImplicitFloatOps' used only in an assert as used.
...
llvm-svn: 116323
2010-10-12 18:18:03 +00:00
0e57a9f7a9
Add MOVi ARM encoding.
...
llvm-svn: 116321
2010-10-12 18:09:12 +00:00
395a898b2b
Initial va_arg support for x86-64. Patch by David Meyer!
...
llvm-svn: 116319
2010-10-12 18:00:49 +00:00
feeae27ad9
Nuke unused wrapper function.
...
llvm-svn: 116318
2010-10-12 17:53:25 +00:00
aec745326a
Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.
...
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.
The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.
llvm-svn: 116314
2010-10-12 17:15:00 +00:00
6fead930af
Add encoding information for the remainder of the generic arithmetic
...
ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
dd6eb5b5a1
PR8359: The ARM backend may end up allocating registers D16 to D31 when
...
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
llvm-svn: 116310
2010-10-12 16:22:47 +00:00
7cd5cda6bb
Rework alloca handling so that we can load or store from casted
...
address that we've looked through.
Fixes compilation problems in tramp3d from earlier patch.
llvm-svn: 116296
2010-10-12 05:39:06 +00:00
db3bcc9910
Handle a wider arrangement of loads.
...
llvm-svn: 116284
2010-10-12 00:43:21 +00:00
cb85497ddf
Delete a redundant check.
...
llvm-svn: 116280
2010-10-12 00:19:24 +00:00
060d5ba248
More SmallVectorImpls.
...
llvm-svn: 116279
2010-10-12 00:15:27 +00:00
c450d2caa5
Shrink a SmallVector with a known maximum size.
...
llvm-svn: 116278
2010-10-12 00:13:43 +00:00
c8da21b04c
Constify.
...
llvm-svn: 116277
2010-10-12 00:12:29 +00:00
7224bcef8f
Use SmallVectorImpl in a bunch of places.
...
llvm-svn: 116276
2010-10-12 00:11:18 +00:00
e790afcbe1
More ARM scheduling itinerary fixes.
...
llvm-svn: 116266
2010-10-11 23:41:41 +00:00
a8d3a7f93d
Support AA chaining.
...
llvm-svn: 116264
2010-10-11 23:39:34 +00:00
844dd0ad00
Fix the pass manager's search order for immutable passes, and make it
...
stop searching when it has found a match.
llvm-svn: 116262
2010-10-11 23:19:01 +00:00
b7c2962d20
MC machine encoding for simple aritmetic instructions that use a shifted
...
register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
109ff296c8
Second set of ARM/MC/ELF changes.
...
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
llvm-svn: 116257
2010-10-11 23:01:44 +00:00
94ad008beb
Proper VST scheduling itineraries.
...
llvm-svn: 116251
2010-10-11 22:03:18 +00:00
d42340ecfd
Use a sane mechanism for that assert.
...
llvm-svn: 116249
2010-10-11 22:01:22 +00:00
57feeed92f
Replace FindLiveRangeContaining() with getVNInfoAt() in LiveIntervalAnalysis.
...
This helps hiding the LiveRange class which really should be private.
llvm-svn: 116244
2010-10-11 21:45:03 +00:00
72b91c1765
We're not going to handle dynamic allocas anywhere else.
...
llvm-svn: 116240
2010-10-11 21:37:35 +00:00
fe2a89683a
Change explicit search Apple specific code to only reference __eprintf on x86.
...
llvm-svn: 116239
2010-10-11 21:34:24 +00:00
71ef1af66b
Make sure that the call stack adjustments have default operands. Also
...
leave custom lowerings for later.
Fixes some nightly tests.
llvm-svn: 116232
2010-10-11 21:20:02 +00:00
6c4353ecee
PowerPC varargs functions store live-in registers on the stack. Make sure we use
...
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.
This fixes PR8357.
llvm-svn: 116222
2010-10-11 20:43:09 +00:00
e2a0b6841a
Found a bug turning this on by default. Disable again for now.
...
llvm-svn: 116220
2010-10-11 20:26:21 +00:00
46cc854e5e
Fix help text.
...
llvm-svn: 116218
2010-10-11 20:15:02 +00:00
5501b7e805
Change flag from Enable to Disable since we're enabled by default.
...
Also don't use fast-isel on non-darwin since it's untested.
llvm-svn: 116217
2010-10-11 20:05:22 +00:00
e01c9001c9
Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand
...
llvm-svn: 116214
2010-10-11 19:02:04 +00:00
5476a274c8
More binary encoding stuff, taking advantage of the new "by name" operand
...
matching in tblgen to do the predicate operand.
llvm-svn: 116213
2010-10-11 18:51:51 +00:00
2276e87a65
Turn on arm fast isel by default.
...
llvm-svn: 116212
2010-10-11 18:48:18 +00:00
2f6531eb8c
Properly handle reloading and spilling around partial redefines in
...
LocalRewriter.
This is a bit of a hack that adds an implicit use operand to model the
read-modify-write nature of a partial redef. Uses and defs are rewritten in
separate passes, and a single operand would never be processed twice.
<rdar://problem/8518892>
llvm-svn: 116210
2010-10-11 18:10:36 +00:00
0f5bfd27a3
MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.
...
llvm-svn: 116201
2010-10-11 11:36:19 +00:00
e1bcb43bb9
Copy and pasteo.
...
llvm-svn: 116198
2010-10-11 08:40:05 +00:00
7ac602bc8e
Whitespace cleanup in ARM fast isel.
...
llvm-svn: 116197
2010-10-11 08:38:55 +00:00
eae1b38550
Add srem libcall support to ARM fast isel.
...
llvm-svn: 116196
2010-10-11 08:37:26 +00:00
e11017c19e
Add i8 sdiv support for ARM fast isel.
...
llvm-svn: 116195
2010-10-11 08:31:54 +00:00
511aa31965
Implement select handling for ARM fast-isel.
...
llvm-svn: 116194
2010-10-11 08:27:59 +00:00
1ef5e84c31
Per discussion with Sanjiv, remove the PIC16 target from mainline. When/if
...
it comes back, it will be largely a rewrite, so keeping the old codebase
in tree isn't helping anyone.
llvm-svn: 116190
2010-10-11 05:44:40 +00:00
8dedb62019
X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents.
...
llvm-svn: 116188
2010-10-11 05:29:15 +00:00
00765e5be0
X86: MinGW should always use libgcc on Windows.
...
llvm-svn: 116177
2010-10-10 23:11:06 +00:00
7a573a5e1f
X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).
...
llvm-svn: 116174
2010-10-10 22:04:34 +00:00
bee1f7f5ba
Fix Whitespace.
...
llvm-svn: 116173
2010-10-10 22:04:20 +00:00
eb313a46fc
fix the default va_arg expansion (in the realignment case) to not implicitly
...
truncate the stack pointer to 32-bits on a 64-bit machine.
llvm-svn: 116169
2010-10-10 18:36:26 +00:00
d10babfd65
fix the expansion of va_arg instruction on PPC to know the arg
...
alignment for PPC32/64, avoiding some masking operations.
llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.
llvm-svn: 116168
2010-10-10 18:34:00 +00:00
b8d7efe785
Now using a variant of the existing inlining heuristics to decide whether to create a given specialization of a function in PartialSpecialization. If the total performance bonus across all callsites passing the same constant exceeds the specialization cost, we create the specialization.
...
llvm-svn: 116158
2010-10-09 22:06:36 +00:00
d84bb168cc
Silence compiler warning.
...
llvm-svn: 116156
2010-10-09 16:36:44 +00:00
a6a984bd96
MC-COFF: Fix .bss section size. Fixes PR8335. Patch by NAKAMUTA Takumi!
...
llvm-svn: 116155
2010-10-09 16:04:45 +00:00
86bbd71088
MC-COFF: Implement InitSections. Fixes PR8335.
...
llvm-svn: 116151
2010-10-09 15:44:27 +00:00
c8dbdfd4ba
MC-COFF: Add COFFAsmParser. Completes PR8343.
...
llvm-svn: 116150
2010-10-09 11:01:07 +00:00
530ce85b3e
Fix Whitespace.
...
llvm-svn: 116149
2010-10-09 11:00:50 +00:00
be52c62a6d
MC-COFF: Assert on non-coff sections.
...
llvm-svn: 116148
2010-10-09 11:00:37 +00:00
d7a404d85f
Add VLD4 scheduling itineraries.
...
llvm-svn: 116143
2010-10-09 04:07:58 +00:00
3d89823102
MC: Move ParseDirectiveELFType into ELFAsmParser. COFF uses .type for something else.
...
llvm-svn: 116142
2010-10-09 03:47:55 +00:00
a762400bed
Finish vld3 and vld4.
...
llvm-svn: 116140
2010-10-09 01:45:34 +00:00
4187f4942e
Complete vld2 instruction itineries.
...
llvm-svn: 116136
2010-10-09 01:26:12 +00:00
1c7fa43e6f
Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1.
...
llvm-svn: 116135
2010-10-09 01:15:04 +00:00
05f13e94bf
Correct some load / store instruction itinerary mistakes:
...
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
llvm-svn: 116134
2010-10-09 01:03:04 +00:00
59ebe44049
Check to make sure that the iterator isn't at the beginning of the basic block
...
before decrementing. <rdar://problem/8529919>
llvm-svn: 116126
2010-10-09 00:03:48 +00:00
c951cfe6a0
add jit support for the new psuedo instructions I added for
...
the add/or xform. The JIT isn't mcized yet, boo.
This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.
llvm-svn: 116125
2010-10-08 23:59:27 +00:00
8eeb5013cd
machine a mutable machineinstr down into emitInstruction.
...
llvm-svn: 116124
2010-10-08 23:54:01 +00:00
548587c31c
Fix the store part of this as well. Fixes smg2000.
...
llvm-svn: 116123
2010-10-08 23:52:16 +00:00
959fcc6c63
Rename SplitEditor::rewrite to finish() and break it out into a couple of new
...
functions: computeRemainder and rewrite.
When the remainder breaks up into multiple components, remember to rewrite those
uses as well.
llvm-svn: 116121
2010-10-08 23:42:21 +00:00
df2aae0c5a
Avoid compiler warning: comparison between signed and unsigned integer.
...
llvm-svn: 116119
2010-10-08 23:01:57 +00:00
b1b0ef7d03
Extract method ProcessUses from LocalRewriter::RewriteMBB. Both parent and child
...
are still way too long, but it's a start.
No functional change intended.
llvm-svn: 116116
2010-10-08 22:14:41 +00:00
fc3642b205
Do not check that the bodies of two defs of same linkonce global are the same.
...
Such a check does not make any sense in presense of inlining and other compiler-dependent stuff.
This should fix bunch of warnings on mingw32.
llvm-svn: 116113
2010-10-08 21:50:04 +00:00
c43c930690
Implement a few more binary encoding bits. Still very early stage proof-of-
...
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
05cae8326d
Classify value numbers into connected components in linear time.
...
llvm-svn: 116105
2010-10-08 21:19:28 +00:00
af8b4871a8
Call InitSections in llc and clang so that the binaries produced by them
...
are easier to diff with those produced by llvm-mc.
llvm-svn: 116095
2010-10-08 19:37:38 +00:00
2fd85d7cd2
Filter out illegal formulae after updating offsets, not before, so that
...
formulae which become illegal as a result of the offset updating don't
escape.
This is for rdar://8529692. No testcase yet, because the given cases
hit use-list ordering differences.
llvm-svn: 116093
2010-10-08 19:33:26 +00:00
d57f9ecd4a
Recommit 116056, now with the missing file...
...
llvm-svn: 116083
2010-10-08 19:24:18 +00:00
4ac0d16c40
Don't waste time unfolding simple loads. The unfolded copy won't be hoisted.
...
llvm-svn: 116081
2010-10-08 18:59:19 +00:00
8c5e7e51bd
Fix operand latency computation in cases where the definition operand is
...
implicit. e.g.
%D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>
%Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...
The real definition indices are 0,1.
llvm-svn: 116080
2010-10-08 18:42:25 +00:00
cc0e18dd4a
CrashRecovery: Fix raise() override to actually send the right signal, *cough*.
...
llvm-svn: 116072
2010-10-08 18:31:34 +00:00
b770c00610
Reapply 116059, this time without the fatfingered pasto at the top.
...
''const'ify getMachineOpValue() and associated helpers.'
llvm-svn: 116067
2010-10-08 17:45:54 +00:00
00351b7731
Reverting 116059. Bots are unhappy with it.
...
llvm-svn: 116064
2010-10-08 17:28:40 +00:00
cf97db2402
reverting 116056: win64_params.ll may need to be conditionalized?
...
llvm-svn: 116063
2010-10-08 17:22:42 +00:00
dd1c289a6a
Line number 0 indicates there is no source line/file name info available for this construct.
...
llvm-svn: 116061
2010-10-08 17:18:54 +00:00
e2d30cd4b5
'const'ify getMachineOpValue() and associated helpers.
...
llvm-svn: 116059
2010-10-08 16:52:44 +00:00
99463ca8cf
Start separating out code metrics into code size metrics and code performance metrics. Partial Specialization will apply the former to function specializations, and the latter to all callsites that can use a specialization, in order to decide whether to create a specialization
...
llvm-svn: 116057
2010-10-08 13:57:31 +00:00
a07b5c291d
Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.
...
llvm-svn: 116056
2010-10-08 10:31:30 +00:00
056b694de1
Change register allocation order for ARM VFP and NEON registers to put the
...
callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
llvm-svn: 116055
2010-10-08 06:15:13 +00:00
35e6ce479c
fix a subtle bug I introduced in my refactoring, where we stopped preferring
...
the i8 versions of instructions in some cases. In test6, we started
generating:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
## <MCInst #478 CMP64mi32
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
instead of:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
## <MCInst #479 CMP64mi8
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
Fix this and add some comments.
llvm-svn: 116053
2010-10-08 05:12:14 +00:00
dd77477690
reapply: Use the new TB_NOT_REVERSABLE flag instead of special
...
reapply: reimplement the second half of the or/add optimization. We should now
with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.
llvm-svn: 116040
2010-10-08 03:57:25 +00:00
626656a562
reapply the patch reverted in r116033:
...
"Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'"
With a critical fix: the add pseudos clobber EFLAGS.
llvm-svn: 116039
2010-10-08 03:54:52 +00:00
d4e9c3b43a
Update CMake.
...
llvm-svn: 116034
2010-10-08 02:30:03 +00:00
8f21f9c1fb
Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into
...
'add'", which seems to have broken just about everything.
llvm-svn: 116033
2010-10-08 02:07:32 +00:00
5b2a411c77
Revert "Use the new TB_NOT_REVERSABLE flag instead of special ", which depends
...
on r116007, which I am about to revert.
llvm-svn: 116032
2010-10-08 02:07:29 +00:00
efdf08b5b8
Revert "reimplement the second half of the or/add optimization. We should now",
...
which depends on r116007, which I am about to revert.
llvm-svn: 116031
2010-10-08 02:07:26 +00:00
15bc2438d9
Move to thumb2 loads, fixes a problem with incoming registers
...
as thumb1.
Fixes lencod.
llvm-svn: 116027
2010-10-08 01:13:17 +00:00
134f415bf8
reimplement the second half of the or/add optimization. We should now
...
only end up emitting LEA instead of OR. If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.
Add some testcases that we emit "or" in cases where we used to produce
an "add".
llvm-svn: 116026
2010-10-08 01:05:10 +00:00
0bb2f9afa9
Enable binary encoding of some simple instructions.
...
llvm-svn: 116022
2010-10-08 00:39:21 +00:00
a7b6d58f45
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
...
llvm-svn: 116018
2010-10-08 00:21:28 +00:00
e2245542ce
Use the new TB_NOT_REVERSABLE flag instead of special
...
casing FsMOVAPDrr/FsMOVAPSrr.
llvm-svn: 116016
2010-10-08 00:03:02 +00:00
0921bfdf36
simplify some map operations.
...
llvm-svn: 116014
2010-10-07 23:57:02 +00:00
aaf4643a31
MC-COFF: Handle relaxation in COFF better. Fixes PR8321.
...
llvm-svn: 116013
2010-10-07 23:55:40 +00:00
5947e1626a
Delete the FormulaSorter class and inline its one method into its
...
one user. This code will be restructured soon and FormulaSorter
is getting in the way.
llvm-svn: 116012
2010-10-07 23:52:18 +00:00
1b61fd9bff
Fix a spello.
...
llvm-svn: 116011
2010-10-07 23:43:09 +00:00
34f37e0d04
Charge a formula for explicit multiplies on scaled registers too,
...
not just base registers.
llvm-svn: 116010
2010-10-07 23:41:58 +00:00
49d638b45a
Use size_t for consistency.
...
llvm-svn: 116009
2010-10-07 23:37:58 +00:00
8e72611058
When merging one use into another, transfer the offsets from
...
the old use to the new one.
llvm-svn: 116008
2010-10-07 23:36:45 +00:00
4fb38d3cd3
Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'
...
is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies. However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).
While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA. This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.
This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20
the add r/i cases are coming next.
llvm-svn: 116007
2010-10-07 23:36:18 +00:00
0f1677e190
After splitting, the remaining LiveInterval may be fragmented into multiple
...
connected components. These components should be allocated different virtual
registers because there is no reason for them to be allocated together.
Add the ConnectedVNInfoEqClasses class to calculate the connected components,
and move values to new LiveIntervals.
Use it from SplitKit::rewrite by creating new virtual registers for the
components.
llvm-svn: 116006
2010-10-07 23:34:34 +00:00
a7b68d6d95
Fix LSR to keep the RegUseTracker up to date when combining users.
...
This doesn't usually matter, because the other heuristics usually
succeed regardless, but it's good to keep the register use
bookkeeping consistent.
llvm-svn: 116005
2010-10-07 23:33:43 +00:00
57da4caa85
Remove LoopIndexSplit pass. It is neither maintained nor used by anyone.
...
llvm-svn: 116004
2010-10-07 23:29:37 +00:00
f41f11c37e
Unbreak cmake build.
...
llvm-svn: 116003
2010-10-07 23:12:15 +00:00
412e37bd34
Code refactoring.
...
llvm-svn: 116002
2010-10-07 23:12:15 +00:00
1c090c00bc
Reduce casting in various tables by defining the table
...
with the right types.
llvm-svn: 116001
2010-10-07 23:08:41 +00:00
70a7b54f97
simplify code: don't build up vector only to assert it is empty.
...
llvm-svn: 115997
2010-10-07 22:26:19 +00:00
df7a4f2515
Now with fewer extraneous semicolons!
...
llvm-svn: 115996
2010-10-07 22:25:06 +00:00
91029094e0
Trivial MC code emitter shell. No instruction forms actually handled yet.
...
llvm-svn: 115993
2010-10-07 22:12:50 +00:00
139edad73a
Correctly check if a path is a directory. Fix by Brian Korver.
...
llvm-svn: 115991
2010-10-07 22:05:57 +00:00
3a24f9230a
Provie a clearner interface so that FE can decide whether a function has prototype or not.
...
llvm-svn: 115988
2010-10-07 22:03:01 +00:00
8aed386d82
Include the auto-generated bits for machine encoding.
...
llvm-svn: 115987
2010-10-07 21:57:55 +00:00
3e1e447ca2
Remember to promote load/store types for stack to register size.
...
llvm-svn: 115984
2010-10-07 21:40:18 +00:00
f5c60d8156
convert test to use the existing classes that the multipatterns
...
use. Since TEST is completely different than all other binops,
don't define a multipattern for it.
This completes factorization of binops.
llvm-svn: 115982
2010-10-07 21:31:03 +00:00
ae8d67d3bb
convert cmp to use a multipattern
...
llvm-svn: 115978
2010-10-07 20:56:25 +00:00
5c31bf0619
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
...
llvm-svn: 115977
2010-10-07 20:50:20 +00:00
07b5b1802e
ARM instruction don't have instruction prefixes, so remove the helper functions
...
for them from the MCCodeEmitter.
llvm-svn: 115975
2010-10-07 20:41:30 +00:00
0df7ea4c24
Move tool_output_file into its own file.
...
llvm-svn: 115973
2010-10-07 20:32:40 +00:00
9786868939
Add initialization routines for Instrumentation.
...
llvm-svn: 115971
2010-10-07 20:17:24 +00:00
a8c0bbb869
reduce redundancy between pattern copies.
...
llvm-svn: 115968
2010-10-07 20:14:23 +00:00
9fece2bea2
the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.
...
llvm-svn: 115967
2010-10-07 20:06:24 +00:00
546c11c72f
Improve comment.
...
llvm-svn: 115966
2010-10-07 20:05:18 +00:00
f7ef5dfccc
Add initialization routines to InstCombine.
...
llvm-svn: 115965
2010-10-07 20:04:55 +00:00
752b60bc01
convert adc/sbb to a multipattern. Because the adde/sube nodes
...
are not defined as returning EFLAGS (like add_flag and friends),
the entire multipattern and several of the subclasses need to be
cloned.
This could be handled through better instantiation support in tblgen,
but it isn't meta enough.
llvm-svn: 115964
2010-10-07 20:01:55 +00:00
44621e4306
Add initialization routines for VMCore.
...
llvm-svn: 115963
2010-10-07 19:51:21 +00:00
e9d5d0736c
Add initialization routines for Target.
...
llvm-svn: 115957
2010-10-07 18:50:11 +00:00
c6a6e9ba7c
Fix obvious mistake pointed out by Michael Spencer.
...
llvm-svn: 115952
2010-10-07 18:47:10 +00:00
9bfd9679f9
Print more loop info.
...
llvm-svn: 115951
2010-10-07 18:47:07 +00:00
7c31730053
Print out MBB number when rewriting.
...
llvm-svn: 115950
2010-10-07 18:47:05 +00:00
80fc0762f3
Add initialization routines for CodeGen.
...
llvm-svn: 115949
2010-10-07 18:41:20 +00:00
98eb3ec6c5
Add an implementation of the initialization routine for IPA.
...
llvm-svn: 115947
2010-10-07 18:31:27 +00:00
6875c2ea26
Add initialization routines for Analysis and IPA.
...
llvm-svn: 115946
2010-10-07 18:31:00 +00:00
bf70a035f0
Add an initialization routine for libLLVMipo.a
...
llvm-svn: 115933
2010-10-07 18:09:59 +00:00
49715fd494
Cache interval iterators in SplitEditor::addTruncSimpleRange so we only have to
...
do one find().
llvm-svn: 115929
2010-10-07 17:56:39 +00:00
9575af4b06
Clean up debug printing.
...
llvm-svn: 115928
2010-10-07 17:56:35 +00:00
4698c5d7f7
Next step on the getting-rid-of-static-ctors train: begin adding per-library
...
initialization functions that initialize the set of passes implemented in
that library. Add C bindings for these functions as well.
llvm-svn: 115927
2010-10-07 17:55:47 +00:00
82d38df40c
Fix a warning when building with clang++.
...
llvm-svn: 115924
2010-10-07 17:04:18 +00:00
ac1ffa27b6
Add the missing cases to the type->registerclass conversion function.
...
llvm-svn: 115921
2010-10-07 16:32:42 +00:00
a845022ddd
Implement two virtual functions in SPUTargetLowering.
...
Before the implementation of isLegalAddressingMode, some rare cases
of code were miscompiled if optimized with the LoopStrengthReduce pass.
It is unclear (to me) if LSR is "allowed" to produce wrong code with a
bad TargetLowering, or if the bug is elsewhere and this patch just
hides it.
llvm-svn: 115919
2010-10-07 16:24:35 +00:00
87002b592e
Minor cosmetic change: fix DOSish \r\n.
...
llvm-svn: 115910
2010-10-07 07:21:04 +00:00
1666b61357
MC-COFF: Fix symbol aliases. Fixes PR8251.
...
llvm-svn: 115909
2010-10-07 06:29:33 +00:00
a2583ea9f2
Use the correct register class for load instructions - fixes
...
compilation of MultiSource/Benchmarks/Bullet.
llvm-svn: 115907
2010-10-07 05:50:44 +00:00
76a9752d45
Use the correct register class here.
...
llvm-svn: 115906
2010-10-07 05:39:19 +00:00
a98be90efe
Use the thumb2 conditional move instruction.
...
llvm-svn: 115905
2010-10-07 05:31:49 +00:00
6d74673366
Remove in-progress assertion, add TODO.
...
llvm-svn: 115904
2010-10-07 05:14:08 +00:00
5e19bfcde3
Move the pass initialization helper functions into the llvm namespace, and add
...
a header declaring them all. This is also where we will declare per-library pass-set
initializer functions down the road.
llvm-svn: 115900
2010-10-07 04:13:08 +00:00
1958cefd69
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
...
llvm-svn: 115898
2010-10-07 01:50:48 +00:00
67677515ac
add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,
...
allowing us to convert ADD over. deletes 160 lines of .td file.
llvm-svn: 115897
2010-10-07 01:37:01 +00:00
4fc52f6fa0
Fix a few issues in ArithBinOpEFLAGS that made it specific to and.
...
Start using ArithBinOpEFLAGS for OR, XOR, and SUB.
This removes 500 lines from the .td file. Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.
llvm-svn: 115896
2010-10-07 01:26:27 +00:00
26d6a0449a
Convert 'and' to single instance of a multipattern
...
which instantiates the 34 versions of and all in one
swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.
No change in the generated .inc files.
llvm-svn: 115893
2010-10-07 01:10:20 +00:00
5b255c2dd6
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
...
llvm-svn: 115890
2010-10-07 00:53:56 +00:00
b71a77d7b8
add a new BinOpAI class to represent the immediate form that directly acts on EAX.
...
This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.
llvm-svn: 115885
2010-10-07 00:43:39 +00:00
742adc328a
Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
...
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
894d2e6146
add a bunch of classes for other common patterns.
...
As usual, no change in generated .inc files.
llvm-svn: 115882
2010-10-07 00:35:28 +00:00
6da4d820fa
Since the Hello pass is built as a loadable dynamic library, don't try to convert it to new-style registration yet.
...
llvm-svn: 115881
2010-10-07 00:31:16 +00:00
e17d7212f1
Define a new BinOpRI8 class and use it to define the imm8 versions of and.
...
llvm-svn: 115880
2010-10-07 00:12:45 +00:00
b19bae4e3e
Constrain the offset register to a *_NOSP register class when inserting LEA
...
instructions.
This unbreaks the machine code verifier and fixes PR8317.
llvm-svn: 115879
2010-10-07 00:07:26 +00:00
356f16c142
add the pattern operator to match to X86TypeInfo, use this to
...
convert AND64ri32 to use BinOpRI.
llvm-svn: 115878
2010-10-07 00:01:39 +00:00
b2dd88db6b
Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.
...
This function looks like it is about ready to be generated by TebleGen.
llvm-svn: 115876
2010-10-06 23:56:46 +00:00
18842783cc
Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.
...
This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.
llvm-svn: 115875
2010-10-06 23:54:39 +00:00
1a065e4e5b
Skip unused registers when verifying LiveIntervals.
...
llvm-svn: 115874
2010-10-06 23:54:35 +00:00
25cd3bfbd7
remove trailing whitespace
...
llvm-svn: 115860
2010-10-06 22:46:47 +00:00
bff84d418f
First in a sequence of ARM/MC/*ELF* specific work.
...
Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute()
Added ARMAsmPrinter::emitAttributes() (plural s).
TODO:
.cpu attribute needs to be refactored
llvm-svn: 115859
2010-10-06 22:36:46 +00:00
883936ce0b
Another case of 256 sections not being enough :-)
...
llvm-svn: 115858
2010-10-06 22:28:19 +00:00
af08ad4350
Appease the clang self-host buildbot by providing a correct instantiation.
...
llvm-svn: 115857
2010-10-06 22:23:20 +00:00
24ab1ce8c2
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
...
llvm-svn: 115853
2010-10-06 22:01:26 +00:00
f49540cb4f
Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).
...
llvm-svn: 115845
2010-10-06 21:36:43 +00:00
2c95027258
Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-needed
...
"lane" operand modifier.
llvm-svn: 115843
2010-10-06 21:22:32 +00:00
2e3e2a006b
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
...
pseudo instructions.
llvm-svn: 115840
2010-10-06 21:16:16 +00:00
5f2d6a5cd9
Get binding and visibility info from the the alias, but Type from the symbol
...
being aliased.
llvm-svn: 115836
2010-10-06 21:02:29 +00:00
ad8134f03b
Hide analysis group registration behind a macro, just like pass registration.
...
llvm-svn: 115835
2010-10-06 21:02:27 +00:00
9a33ec24eb
Add support for DW_TAG_unspecified_parameters.
...
llvm-svn: 115833
2010-10-06 20:50:40 +00:00
233b3a2f95
Add a 'pattern' arg to the ARM PseudoNeonI class.
...
llvm-svn: 115831
2010-10-06 20:36:55 +00:00
e535b01a74
MC: Add missing forward in MCLoggingStreamer.
...
llvm-svn: 115830
2010-10-06 20:36:47 +00:00
5ed50b6151
Revert "RequiresUnique" patch. This should be handled at a lower level.
...
llvm-svn: 115827
2010-10-06 20:18:44 +00:00
d444577382
If a symbol is global, reloc against it even if it is in a mergeable section.
...
llvm-svn: 115817
2010-10-06 19:27:21 +00:00
ec0da969fb
Remove unused variables.
...
llvm-svn: 115802
2010-10-06 18:11:50 +00:00
8025f89860
target operand flag values aren't a bitmask
...
llvm-svn: 115798
2010-10-06 16:51:55 +00:00
83b2a3337f
Make sure weak symbols are listed after the local ones.
...
llvm-svn: 115795
2010-10-06 16:47:31 +00:00
8f3d2c9058
Correctly handle GOTPCREL relocations.
...
llvm-svn: 115793
2010-10-06 16:23:36 +00:00
aadc5596f1
ComputeLinearIndex doesn't need its TLI argument.
...
llvm-svn: 115792
2010-10-06 16:18:29 +00:00
10f60fa411
Change RequiresMerge to RequiresUnique. It's a better description of what this
...
fix is trying to accomplish.
This code could still use some polishing.
llvm-svn: 115759
2010-10-06 07:03:52 +00:00
49d4c0bd18
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
...
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
cd8fe46d4b
If the destination module all ready has a copy of the global coming from the
...
source module *and* it must be merged (instead of simply replaced or appended
to), then merge instead of replacing or adding another global.
The ObjC __image_info section was being appended to because of this
failure. This caused a crash because the linker expects the image info section
to be a specific size.
<rdar://problem/8198537>
llvm-svn: 115753
2010-10-06 06:16:30 +00:00
6e85be2ecf
enhance X86TypeInfo to include information about the encoding and
...
operand kind for immediates. Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it. AND64ri32 needs some
more refactoring before it can make the switcheroo.
llvm-svn: 115752
2010-10-06 05:55:42 +00:00
94eff91dc0
add a class for _REV nodes.
...
llvm-svn: 115748
2010-10-06 05:35:22 +00:00
a46073b56b
sink more intelligence into the ITy base class. Now it knows
...
that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).
llvm-svn: 115747
2010-10-06 05:28:38 +00:00
b6da2be7e8
refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info.
...
llvm-svn: 115745
2010-10-06 05:20:57 +00:00
7bbd809b6c
with tblgen suitably extended, we can now get the load node from typeinfo.
...
llvm-svn: 115744
2010-10-06 04:58:43 +00:00
ad205575fc
lib/System/Win32/Signals.inc: Enable LLVM_DISABLE_CRT_DEBUG also on mingw.
...
llvm-svn: 115731
2010-10-06 02:15:22 +00:00
0198ce06fc
Provide a fast "get me the target triple from the module" API. This can
...
drastically reduce the linking time during LTO.
Patch by Shantonu Sen!
llvm-svn: 115728
2010-10-06 01:22:42 +00:00
1fc81e90f7
lets go all meta and define new X86 type wrappers that declare the associated
...
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)
llvm-svn: 115727
2010-10-06 00:45:24 +00:00
eadaeaab93
introduce a new BinOpRM class and use it to factor AND*rm. This points out
...
that I need a heavier handed approach to get ultimate factorization.
llvm-svn: 115726
2010-10-06 00:30:49 +00:00
9402633637
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
...
where !cast is just as short.
llvm-svn: 115722
2010-10-06 00:19:21 +00:00
04c342ea20
replace stuff like:
...
let AsmString = !strconcat(
!strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
!strconcat("\t", asm));
with:
let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
:)
llvm-svn: 115720
2010-10-06 00:05:18 +00:00
61ea00b494
allow !strconcat to take more than two operands to eliminate
...
!strconcat(!strconcat(!strconcat(!strconcat
Simplify some x86 td files to use it.
llvm-svn: 115719
2010-10-05 23:58:18 +00:00
d7565c3a06
Use a relocation against the symbol if it is a PLT and the symbol is in another
...
section. Common because of linkonce sections.
llvm-svn: 115718
2010-10-05 23:57:26 +00:00
b9f2d50d5f
Comment out fastisel debugging message.
...
llvm-svn: 115717
2010-10-05 23:50:58 +00:00
97b1368ae3
associate the instruction suffix letter with the integer gpr
...
register class, and use this to simplify use of BinOpRR.
llvm-svn: 115716
2010-10-05 23:43:04 +00:00
7359194b63
introduce a new BinOpRR class, and convert 4 and instructions to use it.
...
llvm-svn: 115715
2010-10-05 23:32:05 +00:00
8cfc459274
Random cleanup and make the intermediate register in fptosi a
...
32-bit fp reg, not 64-bit.
Fixes SingleSource.
llvm-svn: 115711
2010-10-05 23:13:24 +00:00
4d5156c7d0
Count uses in all nested loops, not just the deepest.
...
llvm-svn: 115710
2010-10-05 23:10:12 +00:00
56e2925e6c
Remove SplitAnalysis::removeUse. It was only used to make SplitAnalysis
...
reusable, but that is no longer relevant since a split will always replace the
original.
llvm-svn: 115709
2010-10-05 23:10:09 +00:00
0445e2a053
dupli always has an interval now.
...
llvm-svn: 115708
2010-10-05 23:10:04 +00:00
cff5b0ea36
Move cmov pseudo instructions to InstrCompiler,
...
convert all the rest of the cmovs to the multiclass,
with good results:
X86InstrCMovSetCC.td | 598 +--------------------------------------------------
X86InstrCompiler.td | 61 +++++
2 files changed, 77 insertions(+), 582 deletions(-)
llvm-svn: 115707
2010-10-05 23:09:10 +00:00
1a1c600110
Use #NAME# to have the CMOV multiclass define things with the same names as before
...
(e.g. CMOVBE16rr instead of CMOVBErr16).
llvm-svn: 115705
2010-10-05 23:00:14 +00:00
c25b39702f
Another step towards getting rid of static ctors for pass registration: have INITIALIZE_PASS AND INITIALIZE_AG_PASS
...
expand to an initializeMyPass() function (in additional to the extant static ctors). Eventually, these will be called
from a big InitializeAllPasses() function, and the PassInfo's they create (which would be leaked if this code were used
at the moment) will be handed off to a PassRegistry for ownership.
llvm-svn: 115703
2010-10-05 22:58:16 +00:00
7538ed80a9
enhance tblgen to support anonymous defm's, use this to
...
simplify the X86 CMOVmr's.
llvm-svn: 115702
2010-10-05 22:51:56 +00:00
fa25dd9548
convert cmov mr patterns to use a multipattern. Death to redundancy
...
and verbosity
llvm-svn: 115701
2010-10-05 22:42:54 +00:00
0ad137e98e
Implement more alias cases.
...
llvm-svn: 115699
2010-10-05 22:26:43 +00:00
0067ee02f9
switch CMOVBE to the multipattern:
...
21 insertions(+), 53 deletions(-)
Moar change coming before I switch the rest.
llvm-svn: 115697
2010-10-05 22:23:58 +00:00
2dfa8be26a
We can split around loops with multiple exits now.
...
llvm-svn: 115696
2010-10-05 22:19:35 +00:00
89d276aa48
Update SplitEditor API to reflect the fact that the original live interval is
...
never kept after splitting.
Keeping the original interval made sense when the split region doesn't modify
the register, and the original is spilled. We can get the same effect by
detecting reloaded values when spilling around copies.
llvm-svn: 115695
2010-10-05 22:19:33 +00:00
b46d32367f
Intervals are half-open.
...
llvm-svn: 115694
2010-10-05 22:19:29 +00:00
907d86db22
fix a bug I introduced in r115669, which ended up with MOV64mr_TC
...
not getting marked as mayStore. This fixes llvm-gcc bootstrap.
llvm-svn: 115693
2010-10-05 22:16:48 +00:00
c3a767e9b0
add a multiclass for cmov's, but don't start using it yet.
...
llvm-svn: 115692
2010-10-05 22:01:02 +00:00
aa02c1c91d
use a multipattern to define setcc instructions:
...
X86InstrCMovSetCC.td | 200 ++++++---------------------------------------------
1 file changed, 27 insertions(+), 173 deletions(-)
llvm-svn: 115689
2010-10-05 21:34:29 +00:00
3844da781f
256 sections should be enough for anyone...
...
llvm-svn: 115687
2010-10-05 21:20:07 +00:00
8f4f1d1136
move SETB pseudos into the same place in InstrCompiler.td
...
llvm-svn: 115686
2010-10-05 21:18:04 +00:00
13111b08fb
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
...
gross hack (having the asmmatcher handle the alias).
llvm-svn: 115685
2010-10-05 21:09:45 +00:00
c58a37ea51
Don't crash in a strange .size directive.
...
llvm-svn: 115684
2010-10-05 21:02:45 +00:00
ab85ef9e55
distribute the rest of the contents of X86Instr64bit.td out to
...
the right places. X86Instr64bit.td now dies, long live x86-64!
llvm-svn: 115669
2010-10-05 20:49:15 +00:00
671bab1c7d
When we find a reaching definition, make sure it is visited from all paths by
...
erasing it from the visited set. That ensures we create the right phi defs.
llvm-svn: 115666
2010-10-05 20:36:28 +00:00
b0cedd5f96
Don't use nextIndex to check for live out of instruction.
...
Insert copy after defining instruction.
Fix LiveIntervalMap::extendTo to properly handle live segments starting before
the current basic block.
Make sure the open live range is extended to the inserted copy's use slot.
llvm-svn: 115665
2010-10-05 20:36:25 +00:00
27c763d342
move the rest of the simple 64-bit arithmetic into InstrArithmetic.td
...
llvm-svn: 115663
2010-10-05 20:35:37 +00:00
c2f5e5764f
continue moving 64-bit stuff into X86InstrArithmetic.td
...
llvm-svn: 115660
2010-10-05 20:23:31 +00:00
a65d17a5ca
Fix Punctuation.
...
llvm-svn: 115657
2010-10-05 19:48:12 +00:00
a3b34ed2df
MC-COFF: Fix (PR8278) temporary symbol relocations.
...
llvm-svn: 115656
2010-10-05 19:48:03 +00:00
b91bac6c96
Add support for a fill value in the .zero directive.
...
llvm-svn: 115655
2010-10-05 19:42:57 +00:00
9a414901db
Tweak VNInfo printing.
...
llvm-svn: 115650
2010-10-05 18:48:57 +00:00
1c9afa1aeb
Add assert for valid slot indexes.
...
llvm-svn: 115649
2010-10-05 18:48:55 +00:00
e929899a3f
Increase the number of bits used internally by the ARM target to represent the
...
addressing mode from four to five.
llvm-svn: 115645
2010-10-05 18:14:55 +00:00
b1d0789357
Implement a simple alias case and refactor the code a bit so that the
...
isInSymtab and isLocal logic in the two loops don't get easily out of sync.
llvm-svn: 115643
2010-10-05 18:01:23 +00:00
d8d1dcc09a
Use a more efficient lowering of uint64_t --> float that can take advantage of hardware signed integer conversion without
...
having to do a double cast (uint64_t --> double --> float). This is based on the algorithm from compiler_rt's __floatundisf
for X86-64.
llvm-svn: 115634
2010-10-05 17:24:05 +00:00
7552d15d19
move 64-bit add and adc to InstrArithmetic.
...
llvm-svn: 115632
2010-10-05 16:59:08 +00:00
182e87caaf
rewrote two addr constraints so that they are only set, not set and then nestedly cleared.
...
llvm-svn: 115631
2010-10-05 16:52:25 +00:00
39c70f4833
split the 32-bit integer arithmetic instructions out to their own file.
...
llvm-svn: 115627
2010-10-05 16:39:12 +00:00
d03e81dba8
Produce a undefined reference to _GLOBAL_OFFSET_TABLE_ when needed.
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llvm-svn: 115623
2010-10-05 15:48:37 +00:00
6547a50f49
After printing "Running 'Graphviz' program... " and running the
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Graphviz program, print something with a newline, to avoid leaving
the line unfinished.
llvm-svn: 115620
2010-10-05 15:30:27 +00:00
bce26a1ee0
On ELF we need to know which symbols are used in relocations to decide if
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they should be in the symbol table or not. Instead of "guessing", just compute
the symbol table after the relocations are known.
llvm-svn: 115619
2010-10-05 15:11:03 +00:00
1818dd510e
integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.
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llvm-svn: 115608
2010-10-05 07:13:35 +00:00
1b3aa8678e
move 32-bit shift and rotates out to their own file.
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llvm-svn: 115607
2010-10-05 07:00:12 +00:00
89497a990e
add new file
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llvm-svn: 115606
2010-10-05 06:52:35 +00:00
a68466c202
move sign and zero extensions out to their own file.
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llvm-svn: 115605
2010-10-05 06:52:26 +00:00
84571a1581
move some instructions from Instr64Bit -> InstrInfo.
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bswap32 doesn't read eflags.
llvm-svn: 115604
2010-10-05 06:47:35 +00:00
da8c94ef44
move CMOV_FR32 and friends to InstrCompiler, since they are
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pseudo instructions.
Move POPCNT to InstrSSE since they are SSE4 instructions.
llvm-svn: 115603
2010-10-05 06:41:40 +00:00
Eric Christopher