4709ab9124
AMDGPU: Set correct sched model on v_mad_u64_u32
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llvm-svn: 317645
2017-11-08 00:48:25 +00:00
90c7593a75
AMDGPU: Remove global isGCN predicates
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These are problematic because they apply to everything,
and can easily clobber whatever more specific predicate
you are trying to add to a function.
Currently instructions use SubtargetPredicate/PredicateControl
to apply this to patterns applied to an instruction definition,
but not to free standing Pats. Add a wrapper around Pat
so the special PredicateControls requirements can be appended
to the final predicate list like how Mips does it.
llvm-svn: 314742
2017-10-03 00:06:41 +00:00
b865ef534a
[AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16
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This change implements features postponed in https://reviews.llvm.org/D35424 because of a dependency on https://reviews.llvm.org/D36322
Reviewers: SamWot, artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D36694
llvm-svn: 311011
2017-08-16 15:16:32 +00:00
ff64aa514b
[AMDGPU][MC][GFX9] Added integer clamping support for VOP3 opcodes
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See Bug 34152: https://bugs.llvm.org//show_bug.cgi?id=34152
Reviewers: SamWot, artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D36674
llvm-svn: 311006
2017-08-16 13:51:56 +00:00
1e32550de6
[AMDGPU][MC][GFX9] Added 16-bit renamed and "_legacy" VALU opcodes
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See Bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629
Reviewers: vpykhtin, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D36322
llvm-svn: 310497
2017-08-09 17:10:47 +00:00
50805a0b83
[AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI
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See bug 32621: https://bugs.llvm.org//show_bug.cgi?id=32621
Reviewers: vpykhtin, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D35902
llvm-svn: 310251
2017-08-07 13:14:12 +00:00
abf2839478
[AMDGPU][MC][GFX9] Added support of VOP3 'op_sel' modifier
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See bug 33591: https://bugs.llvm.org//show_bug.cgi?id=33591
Reviewers: vpykhtin, artem.tamazov, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D35424
llvm-svn: 308740
2017-07-21 13:54:11 +00:00
4685b70a77
[AMDGPU] resubmit r308179: CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions
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llvm-svn: 308310
2017-07-18 14:23:26 +00:00
9a7442d088
Revert r308179 which causes tablegen to spam stderr on every build.
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Original commit log:
[AMDGPU] CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions
llvm-svn: 308270
2017-07-18 07:40:47 +00:00
a2b9e2f755
[AMDGPU] CodeGen: check dst operand type to determine if omod is supported for VOP3 instructions
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Summary:
Previously, CodeGen checked first src operand type to determine if omod is supported by instruction. This isn't correct for some instructions: e.g. V_CMP_EQ_F32 has floating-point src operands but desn't support omod.
Changed .td files to check if dst operand instead of src operand.
Reviewers: arsenm, vpykhtin
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D35350
llvm-svn: 308179
2017-07-17 14:23:38 +00:00
1a61ab8172
[AMDGPU] Add intrinsics for alignbit and alignbyte instructions
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Differential Revision: https://reviews.llvm.org/D34046
llvm-svn: 305098
2017-06-09 19:03:00 +00:00
e5c7832311
[AMDGPU] Force qsads instrs to use different dest register than source registers
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The V_MQSAD_PK_U16_U8, V_QSAD_PK_U16_U8, and V_MQSAD_U32_U8 take more than 1 pass in hardware. For these three instructions, the destination registers must be different than all sources, so that the first pass does not overwrite sources for the following passes.
Differential Revision: https://reviews.llvm.org/D33783
llvm-svn: 304998
2017-06-08 18:21:19 +00:00
ca5d2efe5a
[AMDGPU] V_DIV_FIXUP_F16 is not a commutable operation
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Differential Revision: https://reviews.llvm.org/D33808
llvm-svn: 304619
2017-06-03 00:16:44 +00:00
f7659d71eb
[AMDGPU] SDWA: Add assembler support for GFX9
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Summary:
Added separate pseudo and real instruction for GFX9 SDWA instructions.
Currently supports only in assembler.
Depends D32493
Reviewers: vpykhtin, artem.tamazov
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D33132
llvm-svn: 303620
2017-05-23 10:08:55 +00:00
ee324ffc1f
AMDGPU: Fix min3/max3 combines for f16/i16
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Fix missing instruction definitions for min3/max3.
llvm-svn: 303284
2017-05-17 19:25:06 +00:00
03852a9dca
[AMDGPU][MC] Removed V_MQSAD_U16_U8
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This instruction does not really exist
See Bug 33018: https://bugs.llvm.org//show_bug.cgi?id=33018
Reviewers: vpykhtin, artem.tamazov
Differential Revision: https://reviews.llvm.org/D33126
llvm-svn: 303055
2017-05-15 12:37:03 +00:00
14104e0d0f
[AMDGPU][MC] Added support for several VI-specific opcodes (s_wakeup, etc)
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Added support for VI:
- s_endpgm_saved
- s_wakeup
- s_rfe_restore_b64
- v_perm_b32
Enabled for VI:
- v_mov_fed_b32
- v_mov_fed_b32_e64
See bug 32593: https://bugs.llvm.org//show_bug.cgi?id=32593
Reviewers: artem.tamazov, vpykhtin
Differential Revision: https://reviews.llvm.org/D31931
llvm-svn: 300076
2017-04-12 17:10:07 +00:00
3bff0c8c59
[AMDGPU][MC] Corrected encoding of V_MQSAD_U32_U8 for CI
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Corrected encoding of V_MQSAD_U32_U8 for CI
See bug 32552: https://bugs.llvm.org//show_bug.cgi?id=32552
Reviewers: vpykhtin
Differential Revision: https://reviews.llvm.org/D31810
llvm-svn: 300070
2017-04-12 15:36:09 +00:00
895d377dc7
[AMDGPU][MC] Fix for Bug 28204 + LIT tests
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Fixed v_mad_i64_i32/u64_u32 encoding
Reviewers: artem.tamazov
Differential Revision: https://reviews.llvm.org/D30828
llvm-svn: 298502
2017-03-22 13:31:01 +00:00
03612631cb
AMDGPU: Add definition for v_xad_u32
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llvm-svn: 296515
2017-02-28 20:27:30 +00:00
10268f93e8
AMDGPU: Use v_med3_{f16|i16|u16}
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llvm-svn: 296401
2017-02-27 22:40:39 +00:00
c9f2517e96
AMDGPU: Add some of the new gfx9 VOP3 instructions
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llvm-svn: 296382
2017-02-27 21:04:41 +00:00
9be7b0d485
AMDGPU: Add VOP3P instruction format
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Add a few non-VOP3P but instructions related to packed.
Includes hack with dummy operands for the benefit of the assembler
llvm-svn: 296368
2017-02-27 18:49:11 +00:00
3b99f12a4e
AMDGPU: Remove modifiers from v_div_scale_*
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They seem to produce nonsense results when used.
This should be applied to the release branch.
llvm-svn: 292472
2017-01-19 06:04:12 +00:00
2a87a42035
[AMDGPU] Handle f16 select{_cc}
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- Select `select` to `v_cndmask_b32`
- Expand `select_cc`
- Refactor patterns
Differential Revision: https://reviews.llvm.org/D26714
llvm-svn: 287074
2016-11-16 03:16:26 +00:00
81da114e65
AMDGPU: Set hasExtraSrcRegAllocReq on v_div_scale_*
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This doesn't solve any problems I know about, but this should have
more conservative assumptions about the operands'
llvm-svn: 286913
2016-11-15 00:05:42 +00:00
f86e4b7266
[AMDGPU] Add f16 support (VI+)
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Differential Revision: https://reviews.llvm.org/D25975
llvm-svn: 286753
2016-11-13 07:01:11 +00:00
115a61560e
AMDGPU: Add VI i16 support
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Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 286464
2016-11-10 16:02:37 +00:00
2d2d33f1dc
Revert "AMDGPU: Add VI i16 support"
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This reverts commit r285939 and r285948. These broke some conformance tests.
llvm-svn: 285995
2016-11-04 13:06:34 +00:00
2b3379cdff
AMDGPU: Add VI i16 support
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Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 285939
2016-11-03 17:13:50 +00:00
355103f6c0
[AMDGPU] Refactor VOP1 and VOP2 instruction TD definitions
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Differential revision: https://reviews.llvm.org/D24738
llvm-svn: 282234
2016-09-23 09:08:07 +00:00
e330cfa294
[AMDGPU] Refactor VOP3 instruction TD definitions
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Differential revision: https://reviews.llvm.org/D24664
llvm-svn: 281965
2016-09-20 10:41:16 +00:00
Matt Arsenault