Commit Graph

326226 Commits

Author SHA1 Message Date
Matt Arsenault 60c8b8bcf2 AMDGPU: Allow getMemOperandWithOffset to analyze stack accesses
Report soffset as a base register if the scratch resource can be
ignored.

llvm-svn: 371149
2019-09-05 23:54:35 +00:00
Matt Arsenault 59ff77ee38 AMDGPU: Fix emitting multiple stack loads for stack passed workitems
The same stack is loaded for each workitem ID, and each use. Nothing
prevents you from creating multiple fixed stack objects with the same
offsets, so this was creating a load for each unique frame index,
despite them being the same offset. Re-use the same frame index so the
loads are CSEable.

llvm-svn: 371148
2019-09-05 23:40:14 +00:00
Eli Friedman 9dd453ce8d [AArch64] Add testcase for codegen for sdiv by 2.
llvm-svn: 371147
2019-09-05 23:40:03 +00:00
Matt Arsenault 524a9d5774 InstCombine: Fix crash on icmp of gep with addrspacecasted null
llvm-svn: 371146
2019-09-05 23:39:21 +00:00
Jonas Devlieghere a8a816c163 [Reproducer] Add a `cont` to ModuleCXX.test
On more than one occasion I've found this test got stuck during replay
while waiting for a packet from debugserver when the debugger was in the
process of being destroyed. For some reason it's more prevalent on the
downstream Swift fork. Adding a cont mitigates the problem while I
investigate.

llvm-svn: 371144
2019-09-05 23:36:57 +00:00
David Blaikie 707be7ef9c llvm-reduce: Use %python from lit to get the correct/valid python binary for the reduction script
llvm-svn: 371143
2019-09-05 23:33:44 +00:00
Matt Arsenault 2a7304c806 AMDGPU: Fix Register copypaste error
llvm-svn: 371141
2019-09-05 23:07:10 +00:00
Alina Sbirlea 35548e80d6 [AliasSetTracker] Correct AAInfo check.
Properly check if NewAAInfo conflicts with AAInfo.
Update local variable and alias set that a change occured when a conflict is found.
Resolves PR42969.

llvm-svn: 371139
2019-09-05 23:00:36 +00:00
Vitaly Buka 9020f11377 [SimplifyCFG] Don't SimplifyBranchOnICmpChain with ExtraCase
Summary:
Here we try to avoid issues with "explicit branch" with SimplifyBranchOnICmpChain
which can check on undef. Msan by design reports branches on uninitialized
memory and undefs, so we have false report here.

In general msan does not like when we convert

```
// If at least one of them is true we can MSAN is ok if another is undefs
if (a || b)
  return;
```
into
```
// If 'a' is undef MSAN will complain even if 'b' is true
if (a)
  return;
if (b)
  return;
```

Example

Before optimization we had something like this:
```
while (true) {
  bool maybe_undef = doStuff();

  while (true) {
    char c = getChar();
    if (c != 10 && c != 13)
     continue
    break;
  }

  // we know that c == 10 || c == 13 if we get here,
  // so msan know that branch is not affected by maybe_undef
  if (maybe_undef || c == 10 || c == 13)
    continue;
  return;
}
```

SimplifyBranchOnICmpChain will convert that into
```
while (true) {
  bool maybe_undef = doStuff();

  while (true) {
    char c = getChar();
    if (c != 10 && c != 13)
      continue;
    break;
  }

  // however msan will complain here:
  if (maybe_undef)
    continue;

  // we know that c == 10 || c == 13, so either way we will get continue
  switch(c) {
    case 10: continue;
    case 13: continue;
  }
  return;
}
```

Reviewers: eugenis, efriedma

Reviewed By: eugenis, efriedma

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67205

llvm-svn: 371138
2019-09-05 22:49:34 +00:00
Matt Arsenault f54daffc2d AMDGPU: Avoid constructing new std::vector in initCandidate
Approximately 30% of the time was spent in the std::vector
constructor. In one testcase this pushes the scheduler to being the
second slowest pass.

I'm not sure I understand why these vector are necessary. The default
scheduler initCandidate seems to use some pre-existing vectors for the
pressure.

llvm-svn: 371136
2019-09-05 22:44:06 +00:00
Nico Weber 3e144ab7fd gn build: Merge r371134
llvm-svn: 371135
2019-09-05 22:40:47 +00:00
Francis Visoiu Mistrih d39720399c [Remarks] Add comparison operators to the Remark object
and related structs.

This also adds tests for the remarks::Remark object in general.

llvm-svn: 371134
2019-09-05 22:35:37 +00:00
Jonas Devlieghere f5687d7c12 Remove `bugreport` command
The bugreport command exists to create domain-specific bug reports.
Currently it has one implementation for filing bugs on the unwinder. As
far as we can tell, it has never been of use. Although not exactly the
same as the reproducers, it's a bit confusing to have two parallel
command trees for (kind of) the same thing.

Differential revision: https://reviews.llvm.org/D65469

llvm-svn: 371132
2019-09-05 21:43:32 +00:00
Sterling Augustine 3270941f1e Add gdb pretty printers for a wide variety of libc++ data structures (take 2).
Summary:
This patch is an exact duplicate of https://reviews.llvm.org/D65609, except
that it uses the newly introduced testing framework to detect if gdb is present
so that the tests won't fail on machines without gdb.

Reviewers: echristo, EricWF

Subscribers: christof, ldionne, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67238

llvm-svn: 371131
2019-09-05 21:35:05 +00:00
Sterling Augustine a127795617 Don't assume libcxx_gdb is always set.
libc++abi also uses this file, but doesn't use the same CMakeLists.txt.

llvm-svn: 371130
2019-09-05 21:34:54 +00:00
Jan Korous 995ff8a77e [ADT] Add makeArrayRef(std::array<>) template specialization
llvm-svn: 371129
2019-09-05 21:27:25 +00:00
Jan Korous e9a78e992b [Bitstream] Add BitCodeAbbrev(std::initializer_list) constructor
llvm-svn: 371128
2019-09-05 21:26:53 +00:00
DeForest Richards 4533b4a3a6 Docs: Update Community section on homepage
This commit includes the following changes: Adds a Getting Involved section under Community. Moves the Development Process section under Community. Moves Sphinx Quickstart Template and How to submit an LLVM bug report from User Guides section to Getting Involved.

llvm-svn: 371127
2019-09-05 21:24:47 +00:00
Vedant Kumar 1261f1b980 [libcxx] Codesign test executables if necessary
If LLVM_CODESIGNING_IDENTITY is set, test executables need to be
codesigned.

Differential Revision: https://reviews.llvm.org/D66496

llvm-svn: 371126
2019-09-05 21:24:23 +00:00
David Bolvansky 5916799293 [GSYM][NFC] Fixed -Wdocumentation warning
lib/DebugInfo/GSYM/InlineInfo.cpp:68:12: warning: parameter 'Inline' not found in the function declaration [-Wdocumentation]

llvm-svn: 371125
2019-09-05 21:09:58 +00:00
Nico Weber a47dc841cd Implement Microsoft-compatible mangling for decomposition declarations.
Match cl.exe's mangling for decomposition declarations.

Decomposition declarations are considered to be anonymous structs,
and use the same convention as for anonymous struct/union declarations.

Naming confirmed to match https://godbolt.org/z/K2osJa

Patch from Eric Astor <epastor@google.com>!

Differential Revision: https://reviews.llvm.org/D67202

llvm-svn: 371124
2019-09-05 21:08:50 +00:00
Nico Weber 36b0571d21 gn build: Merge r371121
llvm-svn: 371123
2019-09-05 20:58:38 +00:00
David Bolvansky 872108bea5 [Diagnostics] Minor improvements for -Wxor-used-as-pow
Extracted from D66397; implemented suggestion for 2^64; tests revisited.

llvm-svn: 371122
2019-09-05 20:50:48 +00:00
Puyan Lotfi dc97ca9f25 [MIR] MIRNamer pass for improving MIR test authoring experience.
This patch reuses the MIR vreg renamer from the MIRCanonicalizerPass to cleanup
names of vregs in a MIR file for MIR test authors. I found it useful when
writing a regression test for a globalisel failure I encountered recently and
thought it might be useful for other folks as well.

Differential Revision: https://reviews.llvm.org/D67209

llvm-svn: 371121
2019-09-05 20:44:33 +00:00
Sterling Augustine bf7602b261 Add testing infrastructure to check if gdb is available for testing.
Reviewers: echristo, EricWF

Subscribers: mgorny, christof, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67194

llvm-svn: 371120
2019-09-05 20:44:08 +00:00
Nico Weber 1d138a47e2 gn build: Merge r371117
llvm-svn: 371119
2019-09-05 20:38:24 +00:00
Jan Korous 7e36ecd66d [clang][Index] Replace CodegenNameGenerator with ASTNameGenerator
Follow-up to: 3ff8c3b73f, d5d15b4c1f

Should be NFC since the original patch just moved the code.

llvm-svn: 371117
2019-09-05 20:33:52 +00:00
Daniel Sanders f803237926 [globalisel][knownbits] Account for missing type constraints
Now that we look through copies, it's possible to visit registers that
have a register class constraint but not a type constraint. Avoid looking
through copies when this occurs as the SrcReg won't be able to determine
it's bit width or any known bits.

Along the same lines, if the initial query is on a register that doesn't
have a type constraint then the result is a default-constructed KnownBits,
that is, a 1-bit fully-unknown value.

llvm-svn: 371116
2019-09-05 20:26:02 +00:00
Daniel Sanders e55c4f33ec [globalisel][knownbits] Correct a typo that prevented a test working as intended
llvm-svn: 371115
2019-09-05 20:25:52 +00:00
Jessica Paquette 20e8667098 Recommit "[AArch64][GlobalISel] Teach AArch64CallLowering to handle basic sibling calls"
Recommit basic sibling call lowering (https://reviews.llvm.org/D67189)

The issue was that if you have a return type other than void, call lowering
will emit COPYs to get the return value after the call.

Disallow sibling calls other than ones that return void for now. Also
proactively disable swifterror tail calls for now, since there's a similar issue
with COPYs there.

Update call-translator-tail-call.ll to include test cases for each of these
things.

llvm-svn: 371114
2019-09-05 20:18:34 +00:00
Alexandre Ganea 3181773116 Revert: [DebugInfo] Add debug location to stubs generated by CGDeclCXX and mark them as artificial
llvm-svn: 371113
2019-09-05 20:12:20 +00:00
Jan Korous afd8249278 [AST][NFC] Doc comments for ASTNameGenerator
llvm-svn: 371112
2019-09-05 20:04:11 +00:00
Eli Friedman cae1e47f6e [IfConversion] Fix diamond conversion with unanalyzable branches.
The code was incorrectly counting the number of identical instructions,
and therefore tried to predicate an instruction which should not have
been predicated.  This could have various effects: a compiler crash,
an assembler failure, a miscompile, or just generating an extra,
unnecessary instruction.

Instead of depending on TargetInstrInfo::removeBranch, which only
works on analyzable branches, just remove all branch instructions.

Fixes https://bugs.llvm.org/show_bug.cgi?id=43121 and
https://bugs.llvm.org/show_bug.cgi?id=41121 .

Differential Revision: https://reviews.llvm.org/D67203

llvm-svn: 371111
2019-09-05 20:02:38 +00:00
Sylvestre Ledru 4e281f70ca doc update: explain that Z3 is only for clang SA - thanks to LebedevRI for the suggestion
llvm-svn: 371110
2019-09-05 19:50:56 +00:00
Sylvestre Ledru 37fcd3a33e document the LLVM_ENABLE_Z3_SOLVER option
llvm-svn: 371109
2019-09-05 19:38:15 +00:00
Roman Lebedev 071ce66729 [NFC][InstCombine] Overhaul 'unsigned add overflow' tests, ensure that all 3 patterns have full test coverage
llvm-svn: 371108
2019-09-05 19:13:15 +00:00
Craig Topper 0fde412140 [X86] Enable BuildSDIVPow2 for i16.
We're able to use a 32-bit ADD and CMOV here and should work
well with our other i16->i32 promotion optimizations.

llvm-svn: 371107
2019-09-05 18:49:52 +00:00
Francis Visoiu Mistrih 07f967d94d [Remarks] Don't serialize metadata if a string table is not used
For YAML remarks with no string table, the mode should not affect the
output.

llvm-svn: 371106
2019-09-05 18:30:20 +00:00
Nico Weber f6400e75eb gn build: Merge r371103
llvm-svn: 371105
2019-09-05 18:15:50 +00:00
Craig Topper b8d6ba3ca2 [X86] Override BuildSDIVPow2 for X86.
As noted in PR43197, we can use test+add+cmov+sra to implement
signed division by a power of 2.

This is based off the similar version in AArch64, but I've
adjusted it to use target independent nodes where AArch64 uses
target specific CMP and CSEL nodes. I've also blocked INT_MIN
as the transform isn't valid for that.

I've limited this to i32 and i64 on 64-bit targets for now and only
when CMOV is supported. i8 and i16 need further investigation to be
sure they get promoted to i32 well.

I adjusted a few tests to enable cmov to demonstrate the new
codegen. I also changed twoaddr-coalesce-3.ll to 32-bit mode
without cmov to avoid perturbing the scenario that is being
set up there.

Differential Revision: https://reviews.llvm.org/D67087

llvm-svn: 371104
2019-09-05 18:15:07 +00:00
Jan Korous 00e04b0a6d [Support] Add writeFileAtomically() to FileUtilities
Differential Revision: https://reviews.llvm.org/D66859

llvm-svn: 371103
2019-09-05 18:10:29 +00:00
Nico Weber 1465a40cf8 gn build: (manually) merge r358706
llvm-svn: 371102
2019-09-05 18:03:18 +00:00
Roman Lebedev 8360c42e25 [InstCombine] foldICmpBinOp(): consider inverted check in 'unsigned sub overflow' check
A follow-up for r329011.
This may be changed to produce @llvm.sub.with.overflow in a later patch,
but for now just make things more consistent overall.

A few observations stem from this:
* There does not seem to be a similar one-instruction fold for uadd-overflow
* I'm not sure we'll want to canonicalize `B u> A` as `usub.with.overflow`,
  so since the `icmp` here no longer refers to `sub`,
  reconstructing `usub.with.overflow` will be problematic,
  and will likely require standalone pass (similar to DivRemPairs).

https://rise4fun.com/Alive/Zqs

Name: (A - B) u> A --> B u> A
  %t0 = sub i8 %A, %B
  %r = icmp ugt i8 %t0, %A
=>
  %r = icmp ugt i8 %B, %A

Name: (A - B) u<= A --> B u<= A
  %t0 = sub i8 %A, %B
  %r = icmp ule i8 %t0, %A
=>
  %r = icmp ule i8 %B, %A

Name: C u< (C - D) --> C u< D
  %t0 = sub i8 %C, %D
  %r = icmp ult i8 %C, %t0
=>
  %r = icmp ult i8 %C, %D

Name: C u>= (C - D) --> C u>= D
  %t0 = sub i8 %C, %D
  %r = icmp uge i8 %C, %t0
=>
  %r = icmp uge i8 %C, %D

llvm-svn: 371101
2019-09-05 17:41:02 +00:00
Roman Lebedev ecb7ea1ae7 [InstCombine] foldICmpBinOp(): consider inverted check in 'unsigned add overflow' check
A follow-up for r342004.
This will be changed to produce @llvm.add.with.overflow in a later patch,
but for now just make things more consistent overall.

https://rise4fun.com/Alive/qxE

Name: (Op1 + X) u< Op1 --> ~Op1 u< X
  %t0 = add i8 %Op1, %X
  %r = icmp ult i8 %t0, %Op1
=>
  %n = xor i8 %Op1, -1
  %r = icmp ult i8 %n, %X

Name: (Op1 + X) u>= Op1 --> ~Op1 u>= X
  %t0 = add i8 %Op1, %X
  %r = icmp uge i8 %t0, %Op1
=>
  %n = xor i8 %Op1, -1
  %r = icmp uge i8 %n, %X

;-------------------------------------------------------------------------------

Name: Op0 u> (Op0 + X) --> X u> ~Op0
  %t0 = add i8 %Op0, %X
  %r = icmp ugt i8 %Op0, %t0
=>
  %n = xor i8 %Op0, -1
  %r = icmp ugt i8 %X, %n

Name: Op0 u<= (Op0 + X) --> X u<= ~Op0
  %t0 = add i8 %Op0, %X
  %r = icmp ule i8 %Op0, %t0
=>
  %n = xor i8 %Op0, -1
  %r = icmp ule i8 %X, %n

llvm-svn: 371100
2019-09-05 17:40:49 +00:00
Roman Lebedev 1d9e0dcc9d [InstCombine][NFC] Tests for 'unsigned sub overflow' check
----------------------------------------
Name: unsigned sub, overflow, v0
  %sub = sub i8 %x, %y
  %ov = icmp ugt i8 %sub, %x
=>
  %agg = usub_overflow i8 %x, %y
  %sub = extractvalue {i8, i1} %agg, 0
  %ov = extractvalue {i8, i1} %agg, 1

Done: 1
Optimization is correct!

----------------------------------------
Name: unsigned sub, no overflow, v0
  %sub = sub i8 %x, %y
  %ov = icmp ule i8 %sub, %x
=>
  %agg = usub_overflow i8 %x, %y
  %sub = extractvalue {i8, i1} %agg, 0
  %not.ov = extractvalue {i8, i1} %agg, 1
  %ov = xor %not.ov, -1

Done: 1
Optimization is correct!

llvm-svn: 371099
2019-09-05 17:40:37 +00:00
Roman Lebedev 745046c23f [InstCombine][NFC] Tests for 'unsigned add overflow' check
----------------------------------------
Name: unsigned add, overflow, v0
  %add = add i8 %x, %y
  %ov = icmp ult i8 %add, %x
=>
  %agg = uadd_overflow i8 %x, %y
  %add = extractvalue {i8, i1} %agg, 0
  %ov = extractvalue {i8, i1} %agg, 1

Done: 1
Optimization is correct!

----------------------------------------
Name: unsigned add, overflow, v1
  %add = add i8 %x, %y
  %ov = icmp ult i8 %add, %y
=>
  %agg = uadd_overflow i8 %x, %y
  %add = extractvalue {i8, i1} %agg, 0
  %ov = extractvalue {i8, i1} %agg, 1

Done: 1
Optimization is correct!

----------------------------------------
Name: unsigned add, no overflow, v0
  %add = add i8 %x, %y
  %ov = icmp uge i8 %add, %x
=>
  %agg = uadd_overflow i8 %x, %y
  %add = extractvalue {i8, i1} %agg, 0
  %not.ov = extractvalue {i8, i1} %agg, 1
  %ov = xor %not.ov, -1

Done: 1
Optimization is correct!

----------------------------------------
Name: unsigned add, no overflow, v1
  %add = add i8 %x, %y
  %ov = icmp uge i8 %add, %y
=>
  %agg = uadd_overflow i8 %x, %y
  %add = extractvalue {i8, i1} %agg, 0
  %not.ov = extractvalue {i8, i1} %agg, 1
  %ov = xor %not.ov, -1

Done: 1
Optimization is correct!

llvm-svn: 371098
2019-09-05 17:40:28 +00:00
Cyndy Ishida 541ab7130e [TextAPI] update interface file for filtered iter
Summary:
This is a simple change that allows easy iterator semantics for symbols held in interface file.
Not being used, so harmless change right now, but will be once TBD-v4 is submitted.

Reviewers: ributzka, steven_wu

Reviewed By: ributzka

Subscribers: javed.absar, kristof.beyls, dexonsmith, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67204

llvm-svn: 371097
2019-09-05 17:33:44 +00:00
DeForest Richards e3e6624ca2 Docs: Move Documentation sections to separate pages.
Updates the links on the homepage by moving the User Guides, Programming Documentation, and Subsystem Documentation sections to separate pages. Also changes "Overview" to "About" at the top of the LLVM Docs homepage. This work is part of the Google Season of Docs project.

llvm-svn: 371096
2019-09-05 17:30:52 +00:00
Sanjay Patel 10412a69f9 [x86] fix horizontal math bug exposed by improved demanded elements analysis (PR43225)
https://bugs.llvm.org/show_bug.cgi?id=43225

llvm-svn: 371095
2019-09-05 17:28:17 +00:00
Craig Topper 97aa42f5df [X86] Add a FIXME about why the CWD/CDQ/CQO have a bogus implicit def of the A register. NFC
The instructions copy the sign bit of the A register to every bit
of the D register. But they don't write to the A register.

llvm-svn: 371094
2019-09-05 17:24:34 +00:00