b6d981bddd
Same isPhysRegAvailable bug as local register allocator.
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llvm-svn: 47500
2008-02-22 20:31:32 +00:00
52c15b3e6d
Really really bad local register allocator bug. On X86, it was never using ESI, EDI, and EBP because of a bug in RALocal::isPhysRegAvailable(). For example, when
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it checks if ESI is available, it then looks at registers aliases to ESI. SIL is marked -2 (not allocatable) but isPhysRegAvailable() incorrectly assumes it is in use and returns false for ESI.
llvm-svn: 47499
2008-02-22 20:30:53 +00:00
a1977d32f0
Add debugging printfs.
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llvm-svn: 47496
2008-02-22 19:57:06 +00:00
ea1ef87ea2
Make sure reload of implicit uses are issued before remat's.
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llvm-svn: 47492
2008-02-22 19:22:06 +00:00
eabc5f39af
Pass alignment on ByVal parameters, from FE, all
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the way through. It is now used for codegen.
llvm-svn: 47484
2008-02-22 17:49:45 +00:00
c373911461
Enable re-materialization of instructions which have virtual register operands if
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the definition of the operand also reaches its uses.
llvm-svn: 47475
2008-02-22 09:24:50 +00:00
271aef2b03
Fix compiler warning.
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llvm-svn: 47468
2008-02-22 01:48:00 +00:00
f3057a939d
Fix a regression in 403.gcc and 186.crafty introduced in 47383. To test
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that a value is >= 32, check that all of the high bits are zero, not
just one or more.
llvm-svn: 47467
2008-02-22 01:12:31 +00:00
3422b673d1
Make the clobber analysis a bit more smart: we only are careful about
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early clobbers if the clobber list contains a *register* not some thing
like {memory}, {dirflag} etc.
llvm-svn: 47457
2008-02-21 20:54:31 +00:00
bdd4c8b04d
Treat clobber operands like early clobbers: if we have
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any, we force sdisel to do all regalloc for an asm. This
leads to gross but correct codegen.
This fixes the rest of PR2078.
llvm-svn: 47454
2008-02-21 19:43:13 +00:00
15526b2e52
Clear PhysRegPartUse for the sub register as well.
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llvm-svn: 47453
2008-02-21 19:35:27 +00:00
963192f40b
Adjust the MaxAlignment for the special register scavenging spill slot.
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llvm-svn: 47452
2008-02-21 19:33:53 +00:00
31160f5b98
Help testing.
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llvm-svn: 47448
2008-02-21 19:20:21 +00:00
7254826c40
Better names as per Evan's request
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llvm-svn: 47435
2008-02-21 16:11:38 +00:00
95528943e9
Atomic op support. If any gcc test uses __sync builtins, it might start failing on archs that haven't implemented them yet
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llvm-svn: 47430
2008-02-21 06:45:13 +00:00
4da4f85090
Add support for matching mem operands. This fixes PR1133, patch by
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Eli Friedman. This implements CodeGen/Generic/2008-02-20-MatchingMem.ll.
llvm-svn: 47428
2008-02-21 05:27:19 +00:00
83c93d5afd
Fix a (harmless) but where vregs were added to the used reg lists for
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inline asms.
Fix PR2078 by marking aliases of registers used when a register is
marked used. This prevents EAX from being allocated when AX is listed
in the clobber set for the asm.
llvm-svn: 47426
2008-02-21 04:55:52 +00:00
911f6bd799
Clean up some spilling code using MachineRegisterInfo.
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llvm-svn: 47416
2008-02-21 00:34:19 +00:00
eac9e5ef21
Remove one of the fixmes that I put in there. From Evan:
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No need to go up more levels. A def of a register also sets its sub-registers
(so if PhysRegInfo[SuperReg] is NULL, it means SuperReg's super registers are
not previously defined).
llvm-svn: 47399
2008-02-20 20:56:45 +00:00
cf2d1aa485
Improve some comments explaining the "handle kills" stuff better.
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llvm-svn: 47395
2008-02-20 19:35:34 +00:00
0b72219681
Fix comment.
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llvm-svn: 47389
2008-02-20 19:09:14 +00:00
57b4eedad9
assert is more effective reminder then FIXME tag for unimplemented features.
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llvm-svn: 47388
2008-02-20 18:37:40 +00:00
e7b462b329
LegalizeTypes support for scalarizing a vector store
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and splitting extract_subvector. This fixes nine
"make check" testcases, for example
2008-02-04-ExtractSubvector.ll and (partially)
CodeGen/Generic/vector.ll.
llvm-svn: 47384
2008-02-20 17:38:09 +00:00
34fc7dbf5b
Convert Legalize to use the APInt form of ComputeMaskedBits.
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llvm-svn: 47383
2008-02-20 16:57:27 +00:00
360c86aed5
Add explicit keywords.
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llvm-svn: 47382
2008-02-20 16:44:09 +00:00
d0ff91dac5
Convert DAGCombiner to use the APInt form of ComputeMaskedBits.
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llvm-svn: 47381
2008-02-20 16:33:30 +00:00
b717fdaa7b
Use APInt::intersects.
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llvm-svn: 47380
2008-02-20 16:30:17 +00:00
18991d78fa
Fix newly-introduced 4.3 warnings
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llvm-svn: 47375
2008-02-20 12:07:57 +00:00
035eaacd1f
Update gcc 4.3 warnings fix patch with recent head changes
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llvm-svn: 47368
2008-02-20 11:10:28 +00:00
579f07135a
Unbreak build with gcc 4.3: provide missed includes and silence most annoying warnings.
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llvm-svn: 47367
2008-02-20 11:08:44 +00:00
b912351ec9
Added some comments and reformatted others. No functionality change.
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Added two "FIXMEs" for code that looks dubious to me (but I could be
wrong).
llvm-svn: 47366
2008-02-20 09:15:16 +00:00
406fdbd3ad
More constification of things. More comments added. No functionality
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changes. (Sorry for any formatting changes that creeped in.)
llvm-svn: 47362
2008-02-20 07:36:31 +00:00
2a8037b5f5
Fix an incredibly subtle bug exposed by Ted's change to APInt profiling.
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AddNodeIDNode does profiling for a ConstantSDNode, but so does
SelectionDAG::getConstant. This profiling should be moved to a common
static function in ConstantSDNode.
llvm-svn: 47359
2008-02-20 06:28:01 +00:00
59cc15955f
No functionality change:
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- Constified some MachineOperand values.
- Added/Modified some comments.
llvm-svn: 47358
2008-02-20 06:10:21 +00:00
295711f583
Add GetResultInst. First step for multiple return value support.
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llvm-svn: 47348
2008-02-19 22:15:16 +00:00
3266ff9a6f
PR1909: Tail merging pass ran wild. It makes no sense to merge blocks in order to save a single instruction since a branch will be inserted for each BB.
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llvm-svn: 47301
2008-02-19 02:09:37 +00:00
6200c225e0
- When DAG combiner is folding a bit convert into a BUILD_VECTOR, it should check if it's essentially a SCALAR_TO_VECTOR. Avoid turning (v8i16) <10, u, u, u> to <10, 0, u, u, u, u, u, u>. Instead, simply convert it to a SCALAR_TO_VECTOR of the proper type.
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- X86 now normalize SCALAR_TO_VECTOR to (BIT_CONVERT (v4i32 SCALAR_TO_VECTOR)). Get rid of X86ISD::S2VEC.
llvm-svn: 47290
2008-02-18 23:04:32 +00:00
b2e4b7adde
- Remove the previous check which broke coalescer-commute3.ll
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- For now, conservatively ignore copy MI whose source is a physical register. Commuting its def MI can cause a physical register live interval to be live through a loop (since we know it's live coming into the def MI).
llvm-svn: 47281
2008-02-18 18:56:31 +00:00
0b2c8858df
New helper function getMBBFromIndex() that given an index in any instruction of an MBB returns a pointer the MBB. Reviewed by Evan.
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llvm-svn: 47267
2008-02-18 09:35:30 +00:00
8f90724a53
For now, avoid commuting def MI for copy MI's whose source is not killed. That simply trade a live interval for another and because only the non-two-address operands can be folded into loads, may end up pessimising code.
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llvm-svn: 47262
2008-02-18 08:40:53 +00:00
fedcf477b5
I cannot find a libgcc function for this builtin. Therefor expanding it to a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support.
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llvm-svn: 47213
2008-02-16 14:46:26 +00:00
b289516a71
Teach LegalizeTypes how to expand the operands of
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br_cc. This fixes 5 "make check" failures.
llvm-svn: 47212
2008-02-16 10:29:26 +00:00
652e4618e2
Refactor some code; check if commuteInstruction is able to commute the instruction.
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llvm-svn: 47208
2008-02-16 02:32:17 +00:00
9b254eed32
llvm.memory.barrier, and impl for x86 and alpha
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llvm-svn: 47204
2008-02-16 01:24:58 +00:00
f861fbaae8
Fix typos.
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llvm-svn: 47200
2008-02-16 01:09:25 +00:00
27ae573900
Rename CountMemOperands to ComputeMemOperandsEnd to reflect what
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it actually does. Simplify CountOperands a little by reusing
ComputeMemOperandsEnd. And reword some comments for both.
llvm-svn: 47198
2008-02-16 00:36:48 +00:00
856c01204b
Revert 47177, which was incorrect.
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llvm-svn: 47196
2008-02-16 00:25:40 +00:00
a3cefeaf0c
Make tblgen a little smarter about constants smaller than i32. Currently,
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tblgen will complain if a sign-extended constant does not fit into a
data type smaller than i32, e.g., i16. This causes a problem when certain
hex constants are used, such as 0xff for byte masks or immediate xor
values.
tblgen will try the sign-extended value first and, if the sign extended
value would overflow, it tries to see if the unsigned value will fit.
Consequently, a software developer can now safely incant:
(XORHIr16 R16C:$rA, 0xffff)
which is somewhat clearer and more informative than incanting:
(XORHIr16 R16C:$rA, (i16 -1))
even if the two are bitwise equivalent.
Tblgen also outputs the 64-bit unsigned constant in the generated ISel code
when getTargetConstant() is invoked.
llvm-svn: 47188
2008-02-15 23:05:48 +00:00
803bb6d699
The copy instruction being coalesced will be removed, it is not a kill.
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llvm-svn: 47179
2008-02-15 21:36:51 +00:00
c278c4aba0
Skip over the defs and start at the uses when looking for operands
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with the TIED_TO attribute.
llvm-svn: 47177
2008-02-15 20:59:17 +00:00
Evan Cheng