842f99a6ee
Always merge profitable shifts on A9, not just when they have a single use.
...
llvm-svn: 141248
2011-10-05 23:39:02 +00:00
87aa18378e
Remove a check from ARM shifted operand isel helper methods, which were blocking
...
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.
llvm-svn: 141247
2011-10-05 23:38:50 +00:00
f793e7ed5c
Get the proper call site numbers for the landing pads. Also remove a magic
...
number (18) for the proper addressing mode.
llvm-svn: 141245
2011-10-05 23:28:57 +00:00
ee9b576a2a
Override TRI::getSubClassWithSubReg for X86.
...
There are fewer registers with sub_8bit sub-registers in 32-bit mode
than in 64-bit mode. In 32-bit mode, sub_8bit behaves the same as
sub_8bit_hi.
llvm-svn: 141206
2011-10-05 20:26:33 +00:00
664e9f55bf
PTX: Fixup a case where getRegClassFor() should be used instead of custom code.
...
llvm-svn: 141199
2011-10-05 18:32:25 +00:00
c6b742f98a
Fix assertion string.
...
llvm-svn: 141197
2011-10-05 18:17:49 +00:00
426a804825
Make sure candidate for delay slot filler is not a return instruction.
...
llvm-svn: 141196
2011-10-05 18:16:09 +00:00
14e4149f4e
Add RA to the set of registers that are defined if instruction is a call.
...
llvm-svn: 141194
2011-10-05 18:11:44 +00:00
10c5b12f99
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
...
llvm-svn: 141190
2011-10-05 17:16:40 +00:00
6e8129e127
Ensure OpCode is not used uninitialized.
...
llvm-svn: 141184
2011-10-05 15:13:13 +00:00
36ffaa809f
Comment out a variable that is only used in commented out code.
...
llvm-svn: 141183
2011-10-05 15:12:44 +00:00
b0e6d04a00
Remove a bunch of unused variables in the PTX backend (warned about by gcc-4.6).
...
llvm-svn: 141182
2011-10-05 15:11:08 +00:00
9ebdf46b5a
MipsDelaySlotFiller.cpp: Appease msvc to specify llvm::next() explicitly.
...
llvm-svn: 141174
2011-10-05 10:11:02 +00:00
2226b4be09
Add braces around something that throws me for a loop.
...
llvm-svn: 141173
2011-10-05 08:59:10 +00:00
6a7aa237cc
There is no point in setting out-parameters for a ComplexPattern function when
...
it returns false, at least as far as I could tell by reading the code.
llvm-svn: 141172
2011-10-05 08:59:05 +00:00
b58a9665bd
Change C++ style comments to C style comments in X86 disassembler. Patch from Joe Abbey.
...
llvm-svn: 141162
2011-10-05 03:29:32 +00:00
02e760add3
Insert space.
...
llvm-svn: 141158
2011-10-05 02:22:49 +00:00
8e532eb92f
Do not examine variadic or implicit operands if instruction is a return (jr).
...
llvm-svn: 141157
2011-10-05 02:21:58 +00:00
0d7dfc0b1f
Clean up function Filler::delayHasHazard.
...
llvm-svn: 141156
2011-10-05 02:18:58 +00:00
7b204688e7
Remove function Filler::insertCallUses.
...
Record the registers used and defined by a call in Filler::insertDefsUses.
llvm-svn: 141154
2011-10-05 02:04:17 +00:00
d9c8aab894
Clean up Filler::findDelayInstr.
...
llvm-svn: 141152
2011-10-05 01:57:46 +00:00
e7b0697412
Remove function Filler::isDelayFiller. Check if I is the same instruction that
...
filled the last delay slot visited.
llvm-svn: 141151
2011-10-05 01:30:09 +00:00
5d4e4ea3d5
Clean up Filler::runOnMachineBasicBlock. Change interface of
...
Filler::findDelayInstr.
llvm-svn: 141150
2011-10-05 01:23:39 +00:00
9e6034444a
Define a statistic for the number of slots that were filled with useful
...
instructions (instructions that are not NOP).
llvm-svn: 141149
2011-10-05 01:19:13 +00:00
8b3666af1b
Remove unnecessary check. isDelayFiller(MBB, I) will evaluate to true before
...
I->getDesc().hasDelaySlot() does.
llvm-svn: 141148
2011-10-05 01:15:31 +00:00
7d398636a2
Add comments and move assignment statement. If sawStore is true, sawLoad does
...
not have to be set.
llvm-svn: 141147
2011-10-05 01:09:37 +00:00
b345b5c424
Correct description string of enable-mips-delay-filler.
...
llvm-svn: 141146
2011-10-05 01:06:57 +00:00
324be98a3c
Look at the number of entries in the jump table and jump to a 'trap' block if
...
the value exceeds that number.
llvm-svn: 141143
2011-10-05 00:39:32 +00:00
202803e39c
Checkpoint for SJLJ EH code.
...
This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.
llvm-svn: 141140
2011-10-05 00:02:33 +00:00
0ca562ec4c
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
...
llvm-svn: 141135
2011-10-04 23:26:17 +00:00
5dcda64338
Adding back support for printing operands symbolically to ARM's new disassembler
...
using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 141129
2011-10-04 22:44:48 +00:00
e25602696e
Teach PPCInstrInfo to handle sub-classes.
...
This has already been done for most other targets.
llvm-svn: 141083
2011-10-04 15:28:47 +00:00
3b309efe38
Set operation actions to legal types only.
...
llvm-svn: 141075
2011-10-04 12:05:35 +00:00
04001625e4
Operations should be custom lowered only if their type is legal.
...
Test: CellSPU/v2i32.ll when running with -promote-elements
llvm-svn: 141074
2011-10-04 10:03:32 +00:00
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
...
llvm-svn: 141065
2011-10-04 06:30:42 +00:00
e7fbce7acb
ARM assembly parsing and encoding for VMOV immediate.
...
llvm-svn: 141046
2011-10-03 23:38:36 +00:00
69e6f90eb2
Tidy up. 80 columns.
...
llvm-svn: 141043
2011-10-03 23:03:26 +00:00
1eab54f8ba
Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.
...
llvm-svn: 141042
2011-10-03 22:44:15 +00:00
46b6646059
ARM parsing/encoding for VCMP/VCMPE.
...
llvm-svn: 141038
2011-10-03 22:30:24 +00:00
374ee194f2
Check-pointing the new SjLj EH lowering.
...
This code will replace the version in ARMAsmPrinter.cpp. It creates a new
machine basic block, which is the dispatch for the return from a longjmp
call. It then shoves the address of that machine basic block into the correct
place in the function context so that the EH runtime will jump to it directly
instead of having to go through a compare-and-jump-to-the-dispatch bit. This
should be more efficient in the common case.
llvm-svn: 141031
2011-10-03 21:25:38 +00:00
c3a6357ee3
Add support for 64-bit logical NOR.
...
llvm-svn: 141029
2011-10-03 21:23:18 +00:00
48a72ca0cb
Add support for 64-bit count leading ones and zeros instructions.
...
llvm-svn: 141028
2011-10-03 21:16:50 +00:00
4ab23b5273
ARM assembly parsing and encoding for VMRS/FMSTAT.
...
llvm-svn: 141025
2011-10-03 21:12:43 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
...
llvm-svn: 141024
2011-10-03 21:06:13 +00:00
5dd3425b77
Thumb2 ADD/SUB can take SP as a destination register.
...
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
llvm-svn: 141020
2011-10-03 20:51:59 +00:00
3caf8cb310
Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer
...
registers.
llvm-svn: 141019
2011-10-03 20:38:08 +00:00
a279d9bd6a
Add support for 64-bit integer multiply instructions.
...
llvm-svn: 141017
2011-10-03 20:01:11 +00:00
cdcc74563c
Add definitions of instructions which move values between 64-bit integer
...
registers and 64-bit HI and LO registers. Fix encoding of the 32-bit versions
of the instructions.
llvm-svn: 141015
2011-10-03 19:28:44 +00:00
786bdb9e14
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
...
llvm-svn: 141007
2011-10-03 17:28:23 +00:00
cc349c8dd8
Add the returns_twice attribute to LLVM.
...
llvm-svn: 141001
2011-10-03 14:45:37 +00:00
0d0be47d03
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
...
llvm-svn: 140997
2011-10-03 08:14:29 +00:00
31854ba017
Fix VEX disassembling to ignore REX.RXBW bits in 32-bit mode.
...
llvm-svn: 140993
2011-10-03 07:51:09 +00:00
7aea69d949
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
...
llvm-svn: 140974
2011-10-02 21:08:12 +00:00
21c33657d6
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
...
llvm-svn: 140971
2011-10-02 16:56:09 +00:00
d07a59f288
Fix disassembling of INVEPT and INVVPID to take operands
...
llvm-svn: 140955
2011-10-01 21:20:14 +00:00
88cb33e0d4
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
...
llvm-svn: 140954
2011-10-01 19:54:56 +00:00
a88cb23da7
Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."
...
to appease nightly testers. Not quite there yet.
llvm-svn: 140953
2011-10-01 19:30:36 +00:00
d072b73d78
No one should be using the method directly. Assert if they do.
...
llvm-svn: 140947
2011-10-01 12:47:34 +00:00
f977ff5fb5
Add a convenience method to tell if two things are equal.
...
llvm-svn: 140946
2011-10-01 12:44:28 +00:00
4a4772fae2
Use the ARMConstantPoolMBB class to handle the MBB values.
...
llvm-svn: 140943
2011-10-01 09:30:42 +00:00
6dbc9fe82b
Add ARMConstantPoolMBB to hold an MBB value in the constant pool.
...
llvm-svn: 140942
2011-10-01 09:19:10 +00:00
c5a86069ca
Remove dead code.
...
llvm-svn: 140941
2011-10-01 09:05:12 +00:00
9ff05f740f
Remove now dead methods and ivar.
...
llvm-svn: 140940
2011-10-01 09:04:18 +00:00
c214cb055d
Use the new ARMConstantPoolSymbol class to handle external symbols.
...
llvm-svn: 140939
2011-10-01 08:58:29 +00:00
d7fa016720
Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class.
...
llvm-svn: 140938
2011-10-01 08:36:59 +00:00
d115c4d300
Remove now dead methods and ivar from ARMConstantPoolValue.
...
llvm-svn: 140937
2011-10-01 08:02:05 +00:00
7753d66468
Switch over to using ARMConstantPoolConstant for global variables, functions,
...
and block addresses.
llvm-svn: 140936
2011-10-01 08:00:54 +00:00
f117a35de0
Some more refactoring.
...
* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.
llvm-svn: 140935
2011-10-01 07:52:37 +00:00
6722556380
Add a Create method that accepts 'kind' and 'pcadj' arguments.
...
llvm-svn: 140934
2011-10-01 06:44:24 +00:00
396c211ae1
Refactoring: Separate out the ARM constant pool Constant from the ARM constant
...
pool value.
It's not used right now, but will be soon.
llvm-svn: 140933
2011-10-01 06:40:33 +00:00
21360a4949
Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
...
useful if an optimization assumes the stack has been realigned. Credit to
Eli for his assistance.
rdar://10043857
llvm-svn: 140924
2011-10-01 02:03:18 +00:00
237dceff90
Store sub-class lists as a bit vector.
...
This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
llvm-svn: 140898
2011-09-30 22:19:07 +00:00
1352be2bd3
Move getCommonSubClass() into TRI.
...
It will soon need the context.
llvm-svn: 140896
2011-09-30 22:18:51 +00:00
d76f43e18c
Correct for my over-eager delete finger.
...
llvm-svn: 140892
2011-09-30 22:02:45 +00:00
ee09394644
Register the MC object streamer.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140887
2011-09-30 21:29:38 +00:00
44220ca045
Register Asm backend. Add functions to MipsAsmBackend.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140886
2011-09-30 21:23:45 +00:00
587fe6cd52
Add MCELFObjectTargetWriter and MCAsmBackend classes.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140885
2011-09-30 21:04:02 +00:00
3bad73a900
Update CMake build.
...
llvm-svn: 140879
2011-09-30 20:44:33 +00:00
750ecec7d5
Initial implementation of MipsMCCodeEmitter.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140878
2011-09-30 20:40:03 +00:00
7ba8a8d656
Add definitions of Mips64 rotate instructions.
...
llvm-svn: 140870
2011-09-30 18:51:46 +00:00
e8e4dbf468
Constify 'isLSDA' and move a method out-of-line.
...
llvm-svn: 140868
2011-09-30 18:42:06 +00:00
4e0dbee62b
ARM Darwin default relocation model is PIC.
...
This matches clang, so default options in llc and friends are now closer to
clang's defaults.
llvm-svn: 140863
2011-09-30 17:41:35 +00:00
9727af7657
isCommutable should be 0 for DSUBu.
...
llvm-svn: 140862
2011-09-30 17:26:36 +00:00
d2222c386c
ARM Fixup valus for movt/movw are for the whole value.
...
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.
rdar://9653509
llvm-svn: 140861
2011-09-30 17:23:05 +00:00
ea3f90ae40
PTX: Various stylistic and code readability changes recommended by Jim Grosbach.
...
llvm-svn: 140855
2011-09-30 14:36:36 +00:00
957a6d5c51
PTX: Add programmable rounding mode specifier for int <-> fp conversion instrs.
...
Also take this opportunity to clean up the rounding mode pass.
llvm-svn: 140854
2011-09-30 13:46:52 +00:00
3111d11f23
PTX: Attempt to cleanup/unify the handling of FP rounding modes. This requires
...
us to manually provide Pat<> definitions for all FP instruction patterns.
llvm-svn: 140849
2011-09-30 12:54:43 +00:00
61e256aa69
Mips64 shift instructions.
...
llvm-svn: 140841
2011-09-30 03:18:46 +00:00
7769a77710
Mips64 arithmetic and logical instructions with one source register and
...
immediate.
llvm-svn: 140839
2011-09-30 02:08:54 +00:00
efc761a1eb
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
...
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
f2619ee3ff
Fill delay slot with useful instructions. Modified from Sparc's version of delay
...
slot filler.
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140825
2011-09-29 23:52:13 +00:00
69bc3de4fc
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
...
llvm-svn: 140824
2011-09-29 23:50:42 +00:00
a1127b2fa2
Support creating a constant pool value for a machine basic block.
...
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.
llvm-svn: 140823
2011-09-29 23:48:44 +00:00
36036412e2
Mips64 arithmetic and logical instructions with two source registers.
...
llvm-svn: 140806
2011-09-29 20:37:56 +00:00
95031ed837
Clean up uses of switch instructions so they are not dependent on the operand ordering. Patch by Stepan Dyatkovskiy.
...
llvm-svn: 140803
2011-09-29 20:21:17 +00:00
abcc57669d
PTX: Fix broken shared library build
...
llvm-svn: 140783
2011-09-29 14:25:48 +00:00
dd1904e7a6
Expand the x86 V_SET0* pseudos right after register allocation.
...
This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.
llvm-svn: 140776
2011-09-29 05:10:54 +00:00
15b3c9c684
Target/ARM: Unbreak! CMake! Build!
...
llvm-svn: 140774
2011-09-29 03:32:49 +00:00
bf64024a39
Delete NEONMoveFix, now unused.
...
llvm-svn: 140773
2011-09-29 02:56:45 +00:00
f7ad189033
Use ExecutionDepsFix instead of NEONMoveFix.
...
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
llvm-svn: 140772
2011-09-29 02:48:41 +00:00
Cameron Zwarich