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Author SHA1 Message Date
Gadi Haber 19c4fc5e62 This is a large patch for X86 AVX-512 of an optimization for reducing code size by encoding EVEX AVX-512 instructions using the shorter VEX encoding when possible. 
There are cases of AVX-512 instructions that have two possible encodings. This is the case with instructions that use vector registers with low indexes of 0 - 15 and do not use the zmm registers or the mask k registers.
The EVEX encoding prefix requires 4 bytes whereas the VEX prefix can take only up to 3 bytes. Consequently, using the VEX encoding for these instructions results in a code size reduction of ~2 bytes even though it is compiled with the AVX-512 features enabled.

Reviewers: Craig Topper, Zvi Rackoover, Elena Demikhovsky 
Differential Revision: https://reviews.llvm.org/D27901

llvm-svn: 290663
 2016-12-28 10:12:48 +00:00
Craig Topper 8f6827c945 [AVX-512] Add patterns to select masked logical operations if the select has a floating point type. 
This is needed in order to replace the masked floating point logical op intrinsics with native IR.

llvm-svn: 280195
 2016-08-31 05:37:52 +00:00
Craig Topper 0f8fb47637 [AVX-512] Add test cases for masked floating point logic operations with bitcasts between the logic ops and the select. We don't currently select masked operations for these cases. 
Test cases taken from optimized clang output after trying to convert the masked floating point logical op intrinsics to native IR.

llvm-svn: 280194
 2016-08-31 05:37:50 +00:00
Craig Topper de8b1a0012 [X86] Regenerate a test using update_llc_test_checks.py. 
llvm-svn: 280193
 2016-08-31 05:37:47 +00:00
Craig Topper 9f51c9ef15 [AVX512] Fix PANDN combining for v4i32/v8i32 when VLX is enabled. 
v4i32/v8i32 ANDs aren't promoted to v2i64/v4i64 when VLX is enabled.

llvm-svn: 271826
 2016-06-05 05:35:11 +00:00
Robert Khasanov 37c3ad6c20 [AVX512] Enabling bit logic lowering 
Added lowering tests.

llvm-svn: 224132
 2014-12-12 17:02:18 +00:00