Commit Graph

14 Commits

Author SHA1 Message Date
Ranjeet Singh ca2b3e7b5c [ARM] Add mrrc/mrrc2 intrinsics and update existing mcrr/mcrr2 intrinsics.
Reapplying patch in r272777 which was reverted
because the llvm patch which added support
for generating the mcrr/mcrr2 instructions
from the intrinsic was causing an assertion
failure. This has now been fixed in llvm.

llvm-svn: 272983
2016-06-17 00:59:41 +00:00
Ranjeet Singh d48760da64 Reverting r272777 because one of the tests
added in the llvm patch is causing an assertion
to fail.

llvm-svn: 272790
2016-06-15 14:21:28 +00:00
Ranjeet Singh 8d5ad5bdf2 [ARM] Add mrrc/mrrc2 intrinsics and update existing mcrr/mcrr2 intrinsics.
Patch adds intrinsics for mrrc/mrrc2. The
intrinsics for mrrc/mrrc2 return a single
uint64_t to represent two 32 bit values.

The mcrr/mcrr2 intrinsic was changed to
accept a single uint64_t instead of two
32 bit values as the input for consistency.

Differential Revision: http://reviews.llvm.org/D21179

llvm-svn: 272777
2016-06-15 11:32:18 +00:00
Ranjeet Singh 61c47fd86a [ARM] Add load/store co-processor intrinsics.
Differential Revision: http://reviews.llvm.org/D20563

llvm-svn: 271275
2016-05-31 13:31:25 +00:00
Ranjeet Singh b631aafee3 [ARM] Fix cdp intrinsic
- Fixed cdp intrinsic to only accept compile time
  constant values previously you could pass in a
  variable to the builtin which would result in
  illegal llvm assembly output

Differential Revision: http://reviews.llvm.org/D20394

llvm-svn: 270058
2016-05-19 13:04:34 +00:00
Ahmed Bougacha 5946ca4fc4 [ARM] Mark mcr/mrc builtin operands as required-immediate.
An early error message is better than the "cannot select" alternative.

llvm-svn: 246094
2015-08-26 22:21:07 +00:00
Yi Kong 1d268af094 ARM: Add dbg builtin intrinsic
llvm-svn: 216452
2014-08-26 12:48:06 +00:00
Yi Kong 26d104a9ec ARM: Prefetch intrinsics
llvm-svn: 215568
2014-08-13 19:18:14 +00:00
Yi Kong 4efadfb0b0 [ARM] Implement ISB memory barrier intrinsic
Adds support for __builtin_arm_isb. Also corrects DSB and ISB instructions
modelling by adding has-side-effects property.

llvm-svn: 212277
2014-07-03 16:01:25 +00:00
Rafael Espindola 0633865e5b Really fix the declaration of __clear_cache.
When I tested gcc's behaviour before, I forgot the extern "C", so it
would warn when the types *did* match.

So in the end
* __clear_cache takes two void pointers.
* aarch64 was correct before.
* libgcc's manual is wrong.
* this patch fixes arm.

llvm-svn: 181810
2013-05-14 18:06:10 +00:00
Rafael Espindola 2219fc5821 Fix __clear_cache on ARM.
Current gcc's produce an error if __clear_cache is anything but

__clear_cache(char *a, char *b);

It looks like we had just implemented a gcc bug that is now fixed.

llvm-svn: 181784
2013-05-14 12:45:47 +00:00
Logan Chien 57086ce248 Fix PR 11709: Change the definition of va_list to meet AAPCS requirement
AAPCS ABI Section 7.1.4 [1] specifies that va_list
should be defined as struct __va_list { void *__ap;};
And in C++, it is defined in namespace std.

[1] http://infocenter.arm.com/help/topic
         /com.arm.doc.ihi0042d/IHI0042D_aapcs.pdf

Patch by Weiming Zhao.

llvm-svn: 165609
2012-10-10 06:56:20 +00:00
John McCall e155a3d8aa __builtin_va_list is void* on ARM, not char*.
rdar://problem/9391966

llvm-svn: 131080
2011-05-09 02:19:37 +00:00
Daniel Dunbar 999daa57c7 Builtins/ARM: __clear_cache doesn't seem to have a consistent prototype, declare
the builtin as void __clear_cache(...) to workaround this, which appears to
match what GCC does.

llvm-svn: 108487
2010-07-16 00:31:23 +00:00