b486144c12
HexagonPacketizer patch.
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llvm-svn: 154616
2012-04-12 21:06:38 +00:00
b25fda95f6
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
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llvm-svn: 152997
2012-03-17 18:46:09 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
30804c24ca
Optimize redundant sign extends and negation of predicates.
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llvm-svn: 150606
2012-02-15 18:52:27 +00:00
d9811eb7be
Revert "Optimize redundant sign extends and negation of predicates"
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as it's breaking the build.
This reverts commit 11241abca5e2a313412fed594bb9d9fa2a2057fb.
llvm-svn: 150604
2012-02-15 18:32:25 +00:00
4736aee81e
Optimize redundant sign extends and negation of predicates
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llvm-svn: 150601
2012-02-15 18:22:18 +00:00
6f35837048
Use TSFlag bit to describe instruction properties.
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Creating the isPredicated TSFlag enables the code
to use the property defined in the instruction format
instead of using a large switch statement.
llvm-svn: 150078
2012-02-08 18:25:47 +00:00
d06df96a7c
VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).
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This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling.
Patch by Sergei Larin!
llvm-svn: 149547
2012-02-01 22:13:57 +00:00
1213a7a57f
Hexagon backend support
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llvm-svn: 146412
2011-12-12 21:14:40 +00:00
Sirish Pande