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Author SHA1 Message Date
Zakk Chen 9998b00c2e [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. 
Fix the unexpected of using op1's element type as shift amount type.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D98501
 2021-03-17 10:47:49 -07:00
Hsiangkai Wang 6e360460f1 [RISCV] Use v8-v23 as argument registers to conform to the proposal. 
The maximum LMUL is 8. We need 16 vector registers for two LMUL-8
arguments. The modification follows the proposal of psABI in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171

Differential Revision: https://reviews.llvm.org/D95134
 2021-01-22 07:55:24 +08:00
Craig Topper 79cbb003c5 [RISCV] Don't use tail agnostic policy on instructions where destination is tied to source 
If the destination is tied, then user has some control of the
register used for input. They would have the ability to control
the value of any tail elements. By using tail agnostic we take
this option away from them.

Its not clear that the intrinsics are defined such that this isn't
supposed to work. And undisturbed is a valid implementation for agnostic
so code wouldn't even fail to work on all systems if we always used
agnostic.

The vcompress intrinsic is defined to require tail undisturbed so
at minimum we need this for that instruction or need to redefine
the intrinsic.

I've made an exception here for vmv.s.x/fmv.s.f and reduction
instructions which only write to element 0 regardless of the tail
policy. This allows us to keep the agnostic policy on those which
should allow better redundant vsetvli removal.

An enhancement would be to check for undef input and keep the
agnostic policy, but we don't have good test coverage for that yet.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D93878
 2020-12-29 10:37:58 -08:00
Monk Chiang 3183add534 [RISCV] Define the remaining vector fixed-point arithmetic intrinsics. 
This patch base on D93366, and define vector fixed-point intrinsics.
    1. vaaddu/vaadd/vasubu/vasub
    2. vsmul
    3. vssrl/vssra
    4. vnclipu/vnclip

  We work with @rogfer01 from BSC to come out this patch.

  Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
  Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

  Differential Revision: https://reviews.llvm.org/D93508
 2020-12-20 22:57:07 -08:00