Craig Topper
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262a72f50f
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[RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32.
Reduces the amount of vector ALU operations and reduces vector
register pressure.
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2021-04-26 15:43:02 -07:00 |
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Hsiangkai Wang
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6e360460f1
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[RISCV] Use v8-v23 as argument registers to conform to the proposal.
The maximum LMUL is 8. We need 16 vector registers for two LMUL-8
arguments. The modification follows the proposal of psABI in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171
Differential Revision: https://reviews.llvm.org/D95134
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2021-01-22 07:55:24 +08:00 |
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Fraser Cormack
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1d4411e9ea
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[RISCV] Add vector integer min/max ISel patterns
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D94012
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2021-01-05 09:15:50 +00:00 |