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Commit Graph

Author	SHA1	Message	Date
Hsiangkai Wang	6e360460f1	[RISCV] Use v8-v23 as argument registers to conform to the proposal. The maximum LMUL is 8. We need 16 vector registers for two LMUL-8 arguments. The modification follows the proposal of psABI in https://github.com/riscv/riscv-elf-psabi-doc/pull/171 Differential Revision: https://reviews.llvm.org/D95134	2021-01-22 07:55:24 +08:00
Monk Chiang	2aed9bc98a	[RISCV] Define vector narrowing type-convert intrinsic. Define intrinsics: 1. vfncvt.xu.f.w/vfncvt.x.f.w 2. vfncvt.rtz.xu.f.w/vfncvt.rtz.x.f.w 3. vfncvt.f.xu.w/vfncvt.f.x.w 4. vfncvt.f.f.w/vfncvt.rod.f.f.w We work with @rogfer01 from BSC to come out this patch. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Monk Chiang <monk.chiang@sifive.com> Differential Revision: https://reviews.llvm.org/D93932	2020-12-31 11:48:28 +08:00

Author

SHA1

Message

Date

Hsiangkai Wang

6e360460f1

[RISCV] Use v8-v23 as argument registers to conform to the proposal.

The maximum LMUL is 8. We need 16 vector registers for two LMUL-8
arguments. The modification follows the proposal of psABI in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171

Differential Revision: https://reviews.llvm.org/D95134

2021-01-22 07:55:24 +08:00

Monk Chiang

2aed9bc98a

[RISCV] Define vector narrowing type-convert intrinsic.

Define intrinsics:
  1. vfncvt.xu.f.w/vfncvt.x.f.w
  2. vfncvt.rtz.xu.f.w/vfncvt.rtz.x.f.w
  3. vfncvt.f.xu.w/vfncvt.f.x.w
  4. vfncvt.f.f.w/vfncvt.rod.f.f.w

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Monk Chiang <monk.chiang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93932

2020-12-31 11:48:28 +08:00

2 Commits