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Author SHA1 Message Date
Craig Topper 5a9a8c7cd4 [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 
This confirms we handle most instrutions gracefully. We do
currently fail for vslide1up and vslide1down though.
 2021-04-01 20:34:28 -07:00
Hsiangkai Wang 6e360460f1 [RISCV] Use v8-v23 as argument registers to conform to the proposal. 
The maximum LMUL is 8. We need 16 vector registers for two LMUL-8
arguments. The modification follows the proposal of psABI in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171

Differential Revision: https://reviews.llvm.org/D95134
 2021-01-22 07:55:24 +08:00
Monk Chiang 1d04cbeb43 [RISCV] Define vector single-width type-convert intrinsic. 
Define intrinsics:
  1. vfcvt.xu.f.v/vfcvt.x.f.v
  2. vfcvt.rtz.xu.f.v/vfcvt.rtz.x.f.v
  3. vfcvt.f.xu.v/vfcvt.f.x.v

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Monk Chiang <monk.chiang@sifive.com>

Differential Revision: https://reviews.llvm.org/D93933
 2020-12-31 11:49:30 +08:00