5f24d10381
80 columns
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llvm-svn: 33489
2007-01-24 18:50:57 +00:00
6730e12ae4
PEI is now responsible for adding MaxCallFrameSize to frame size and align the stack. Each target can further adjust the frame size if necessary.
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llvm-svn: 33460
2007-01-23 09:38:11 +00:00
16e58be1bc
hasFP() is now a virtual method of MRegisterInfo.
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llvm-svn: 33455
2007-01-23 00:57:47 +00:00
706b6797a0
One more try...
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llvm-svn: 33400
2007-01-20 10:17:53 +00:00
b268184363
Last check-in was bogus. There is no need to align the stack if the function is a leaf function (and without alloca).
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llvm-svn: 33399
2007-01-20 10:11:56 +00:00
86468ccaf3
Backend is reponsible for aligning the stack.
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llvm-svn: 33388
2007-01-20 02:08:16 +00:00
a0554d90e8
* PIC codegen for X86/Linux has been implemented
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* PIC-aware internal structures in X86 Codegen have been refactored
* Visibility (default/weak) has been added
* Docs fixes (external weak linkage, visibility, formatting)
llvm-svn: 33136
2007-01-12 19:20:47 +00:00
4efbbc963f
Really big cleanup.
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- New target type "mingw" was introduced
- Same things for both mingw & cygwin are marked as "cygming" (as in
gcc)
- .lcomm is supported here, so allow LLVM to use it
- Correctly use underscored versions of setjmp & _longjmp for both mingw
& cygwin
llvm-svn: 32833
2007-01-03 11:43:14 +00:00
74b46e8c05
Fix naming inconsistency.
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llvm-svn: 32823
2007-01-02 21:33:40 +00:00
735fcf74d8
f64 <-> i64 bit_convert using movq in 64-bit mode.
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llvm-svn: 32587
2006-12-14 21:55:39 +00:00
0fd32e9ade
Added MOVSS2DIrr and MOVDI2SSrr to foldMemeoryOperand().
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llvm-svn: 32583
2006-12-14 19:44:45 +00:00
9bfb1e1f29
What should be the last unnecessary <iostream>s in the library.
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llvm-svn: 32333
2006-12-07 22:21:48 +00:00
e312c152d2
MI keeps a ptr of TargetInstrDescriptor, use it.
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llvm-svn: 32296
2006-12-07 01:21:59 +00:00
67fc141db5
Match TargetInstrInfo changes.
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llvm-svn: 32098
2006-12-01 21:52:58 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
de5fa025ab
Hopefully a good crack at making debugging work on intel -disable-fp-elim.
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llvm-svn: 31830
2006-11-17 21:19:15 +00:00
572dc9cb4e
Correct instructions for moving data between GR64 and SSE registers; also correct load i64 / store i64 from v2i64.
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llvm-svn: 31795
2006-11-16 23:33:25 +00:00
dc2c8748a7
Properly transfer kill / dead info.
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llvm-svn: 31765
2006-11-15 20:58:11 +00:00
dbd3d294e6
Matches MachineInstr changes.
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llvm-svn: 31712
2006-11-13 23:36:35 +00:00
286357480c
Fix a potential bug.
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llvm-svn: 31634
2006-11-10 09:13:37 +00:00
8c9c6d71ed
Add implicit def / use operands to MachineInstr.
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llvm-svn: 31633
2006-11-10 08:43:01 +00:00
14140059f0
Use TargetInstrInfo::getNumOperands() instead of MachineInstr::getNumOperands(). In preparation for implicit reg def/use changes.
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llvm-svn: 31616
2006-11-10 01:28:43 +00:00
1698c2999c
Remove M_2_ADDR_FLAG.
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llvm-svn: 31583
2006-11-09 02:22:54 +00:00
94b29e9e91
Dead code.
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llvm-svn: 31405
2006-11-03 02:08:41 +00:00
1da0ab2f58
Delete dead code; fix 80 col violations.
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llvm-svn: 30583
2006-09-22 21:43:59 +00:00
6f7072c66a
Added some eye-candy for Subtarget type checking
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Added X86 StdCall & FastCall calling conventions. Codegen will follow.
llvm-svn: 30446
2006-09-17 20:25:45 +00:00
de33f66286
Fixed a FuseTwoAddrInst() bug: consider GlobalAddress and JumpTableIndex
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in addition to immediate operands.
llvm-svn: 30205
2006-09-08 21:08:13 +00:00
11b0a5dbd4
Committing X86-64 support.
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llvm-svn: 30177
2006-09-08 06:48:29 +00:00
1b7f09cdf7
Some notes on better load folding we could do
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llvm-svn: 30155
2006-09-07 20:32:01 +00:00
7a150d3113
Fix a few dejagnu failures. e.g. fast-cc-merge-stack-adj.ll
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llvm-svn: 30113
2006-09-05 08:32:49 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
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def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
13a5dcddce
Fix a long-standing wart in the code generator: two-address instruction lowering
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actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
llvm-svn: 30108
2006-09-05 02:12:02 +00:00
60f1eecd3a
Constify some methods. Patch provided by Anton Vayvod, thanks!
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llvm-svn: 29756
2006-08-17 22:00:08 +00:00
f98bc5288e
Missing a space.
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llvm-svn: 29233
2006-07-20 22:52:28 +00:00
7c860afec6
Tidy up a few things.
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llvm-svn: 29213
2006-07-19 19:32:06 +00:00
18debc21db
Reduce size of routine. Shrinks .o by 37%.
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llvm-svn: 29210
2006-07-19 17:53:32 +00:00
fa9e60895b
Add shift and rotate by 1 instructions / patterns.
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llvm-svn: 28980
2006-06-29 00:36:51 +00:00
17ca732b6a
Cygwin support: use _alloca to allocate stack if > 4k. Patch by Anton Korobeynikov.
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llvm-svn: 28764
2006-06-13 05:14:44 +00:00
dc614c193e
Added X86FunctionInfo subclass of MachineFunction to record whether the
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function that is being lowered is forced to use FP. Currently this is only
true for main() / Cygwin.
llvm-svn: 28703
2006-06-06 23:30:24 +00:00
e8a42360c5
Cygwin support. Patch by Anton Korobeynikov!
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llvm-svn: 28672
2006-06-02 22:38:37 +00:00
25e44e008d
Rename instructions for consistency sake.
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llvm-svn: 28594
2006-05-31 19:00:07 +00:00
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
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llvm-svn: 28378
2006-05-18 00:12:58 +00:00
9fee442e63
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
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llvm-svn: 28324
2006-05-16 07:21:53 +00:00
b19ce6c810
More coverity fixes
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llvm-svn: 28266
2006-05-12 21:14:20 +00:00
9733bde74c
Fixing truncate. Previously we were emitting truncate from r16 to r8 as
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movw. That is we promote the destination operand to r16. So
%CH = TRUNC_R16_R8 %BP
is emitted as
movw %bp, %cx.
This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.
We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.
Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.
llvm-svn: 28164
2006-05-08 08:01:26 +00:00
ddb6cc1d8e
Better implementation of truncate. ISel matches it to a pseudo instruction
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that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.
llvm-svn: 28119
2006-05-05 05:40:20 +00:00
469647bf38
Remove and simplify some more machineinstr/machineoperand stuff.
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llvm-svn: 28105
2006-05-04 18:16:01 +00:00
10d6341618
Move some methods out of MachineInstr into MachineOperand
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llvm-svn: 28102
2006-05-04 17:52:23 +00:00
fef7a2d0f5
There shalt be only one "immediate" operand type!
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llvm-svn: 28099
2006-05-04 17:21:20 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
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llvm-svn: 28093
2006-05-04 01:15:02 +00:00
Jim Laskey