dc1764c5a4
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.
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llvm-svn: 181705
2013-05-13 14:10:04 +00:00
af22d91af0
s tightens up the encoding description for ARM post-indexed ldr instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL.
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llvm-svn: 180778
2013-04-30 09:00:12 +00:00
a83d5e9f91
ARM: Fix encoding of hint instruction for Thumb.
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"hint" space for Thumb actually overlaps the encoding space of the CPS
instruction. In actuality, hints can be defined as CPS instructions where imod
and M bits are all nil.
Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe,
sev) in DecodeT2CPSInstruction.
This commit adds a proper diagnostic message for Imm0_4 and updates all tests.
Patch by Mihail Popa <Mihail.Popa@arm.com>.
llvm-svn: 180617
2013-04-26 17:54:54 +00:00
27ff504653
ARM: Permit "sp" in ARM variant of STREXD instructions
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Patch from Mihail Popa
llvm-svn: 179854
2013-04-19 15:44:32 +00:00
a155ab2dd2
ARM: permit "sp" in ARM variants of MOVW/MOVT instructions
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llvm-svn: 179847
2013-04-19 09:58:09 +00:00
c313220b18
ARM: Correct printing of pre-indexed operands.
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According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes.
The MC disassembler was not obeying this when the offset is 0.
It was producing instructions like: str r0, [r1]!.
Correct syntax is: str r0, [r1, #0 ]!.
This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used.
Patch by Mihail Popa <Mihail.Popa@arm.com>
llvm-svn: 179398
2013-04-12 18:47:25 +00:00
c6047655a7
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.
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These instructions aren't universally available, but depend on a specific
extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new
feature is appropriate.
This also enables the feature by default on A-class cores which usually have
these extensions, to avoid breaking existing code and act as a sensible
default.
llvm-svn: 179171
2013-04-10 12:08:35 +00:00
772cf466da
Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when the upper bit is set.
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They should always be zero-extended, not sign extended. Added test case.
llvm-svn: 178275
2013-03-28 19:22:28 +00:00
f686be4674
Patch by Gordon Keiser!
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If PC or SP is the destination, the disassembler erroneously failed with the
invalid encoding, despite the manual saying that both are fine.
This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a
postindexed load, where the offset 0xc is applied to SP after the load occurs.
llvm-svn: 178017
2013-03-26 13:58:53 +00:00
0ba797e8f7
Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.
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The Printer will now print instructions with the correct alignment specifier syntax, like
vld1.8 {d16}, [r0:64]
llvm-svn: 175884
2013-02-22 10:01:33 +00:00
2efb59a719
Make ARMAsmParser accept the correct alignment specifier syntax in instructions.
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The parser will now accept instructions with alignment specifiers written like
vld1.8 {d16}, [r0:64]
, while also still accepting the incorrect syntax
vld1.8 {d16}, [r0, :64]
llvm-svn: 175164
2013-02-14 14:46:12 +00:00
168ffb36a5
Added a option to the disassembler to print immediates as hex.
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This is for the lldb team so most of but not all of the values are
to be printed as hex with this option. Some small values like the
scale in an X86 address were requested to printed in decimal
without the leading 0x.
There may be some tweaks need to places that may still be in
decimal that they want in hex. Specially for arm. I made my best
guess. Any tweaks from here should be simple.
I also did the best I know now with help from the C++ gurus
creating the cleanest formatImm() utility function and containing
the changes. But if someone has a better idea to make something
cleaner I'm all ears and game for changing the implementation.
rdar://8109283
llvm-svn: 169393
2012-12-05 18:13:19 +00:00
136d6746c5
Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst
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which would then cause an assert when printed. rdar://11437956
llvm-svn: 168960
2012-11-29 23:47:11 +00:00
4739f2eb19
ARM: Better disassembly for pc-relative LDR.
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When the operand is a plain immediate rather than a label, print it
as [pc, #imm] like we do for the Thumb2 wide encoding variant.
rdar://12154503
llvm-svn: 166991
2012-10-30 01:04:51 +00:00
6fd9624843
Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target
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is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement.
llvm-svn: 166982
2012-10-29 23:27:20 +00:00
62183c4e18
Add support for annotated disassembly output for X86 and arm.
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Per the October 12, 2012 Proposal for annotated disassembly output sent out by
Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc
tool now has a -mdis option to produced the marked up disassembly and a couple
of small example test cases have been added.
rdar://11764962
llvm-svn: 166445
2012-10-22 22:31:46 +00:00
00e071ad52
Diagnose invalid alignments on duplicating VLDn instructions.
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Patch by Chris Lidbury.
llvm-svn: 163323
2012-09-06 15:27:12 +00:00
fb3cdd83b0
Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions.
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Patch by Chris Lidbury.
llvm-svn: 163321
2012-09-06 15:17:49 +00:00
262f6f564f
Use correct part of complex operand to encode VST1 alignment.
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Patch by Chris Lidbury.
llvm-svn: 163318
2012-09-06 14:36:55 +00:00
b4e1ba7191
ARM: Move Thumb2 tests to Thumb2 test file and fix CHECK lines.
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These tests weren't actually being run before (missing ':' after CHECK).
llvm-svn: 161800
2012-08-13 22:25:44 +00:00
6a43bf7d74
Fix #13035 , a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue.
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llvm-svn: 161162
2012-08-02 08:29:50 +00:00
288e1af8c8
Fix #13138 , a bug around ARM instruction DSB encoding and decoding issue.
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llvm-svn: 161161
2012-08-02 08:21:27 +00:00
10dd40e42d
Fix #13241 , a bug around shift immediate operand for ARM instruction ADR.
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llvm-svn: 161159
2012-08-02 08:13:13 +00:00
1dc44dcedd
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
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llvm-svn: 159989
2012-07-10 12:51:09 +00:00
ff123d5c63
Fix the remaining TCL-style quotes found in the testsuite. This is
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another mechanical change accomplished though the power of terrible Perl
scripts.
I have manually switched some "s to 's to make escaping simpler.
While I started this to fix tests that aren't run in all configurations,
the massive number of tests is due to a really frustrating fragility of
our testing infrastructure: things like 'grep -v', 'not grep', and
'expected failures' can mask broken tests all too easily.
Essentially, I'm deeply disturbed that I can change the testsuite so
radically without causing any change in results for most platforms. =/
llvm-svn: 159547
2012-07-02 19:09:46 +00:00
5da53436d5
Convert the uses of '|&' to use '2>&1 |' instead, which works on old
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versions of Bash. In addition, I can back out the change to the lit
built-in shell test runner to support this.
This should fix the majority of fallout on Darwin, but I suspect there
will be a few straggling issues.
llvm-svn: 159544
2012-07-02 18:37:59 +00:00
a5a29f970e
Convert all tests using TCL-style quoting to use shell-style quoting.
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This was done through the aid of a terrible Perl creation. I will not
paste any of the horrors here. Suffice to say, it require multiple
staged rounds of replacements, state carried between, and a few
nested-construct-parsing hacks that I'm not proud of. It happens, by
luck, to be able to deal with all the TCL-quoting patterns in evidence
in the LLVM test suite.
If anyone is maintaining large out-of-tree test trees, feel free to poke
me and I'll send you the steps I used to convert things, as well as
answer any painful questions etc. IRC works best for this type of thing
I find.
Once converted, switch the LLVM lit config to use ShTests the same as
Clang. In addition to being able to delete large amounts of Python code
from 'lit', this will also simplify the entire test suite and some of
lit's architecture.
Finally, the test suite runs 33% faster on Linux now. ;]
For my 16-hardware-thread (2x 4-core xeon e5520): 36s -> 24s
llvm-svn: 159525
2012-07-02 12:47:22 +00:00
f1ef87ddbb
Correct decoder for T1 conditional B encoding
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llvm-svn: 158055
2012-06-06 09:12:53 +00:00
ddc67a7655
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
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llvm-svn: 156609
2012-05-11 09:28:27 +00:00
914223010c
Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
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for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some cases.
Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!
llvm-svn: 156118
2012-05-03 22:41:56 +00:00
9560af848c
Fixed disassembler for vstm/vldm ARM VFP instructions.
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llvm-svn: 156077
2012-05-03 16:38:40 +00:00
0fc56890ba
Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.
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llvm-svn: 155983
2012-05-02 09:43:18 +00:00
8a8e9d1b63
Specify cpu to unbreak tests.
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llvm-svn: 155604
2012-04-26 01:38:10 +00:00
70be447e5c
Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)
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instructions.
llvm-svn: 155453
2012-04-24 17:45:56 +00:00
c8d223e41e
Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)
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instructions.
llvm-svn: 155444
2012-04-24 15:55:00 +00:00
ca45af9a75
Added support for disassembling unpredictable swp/swpb ARM instructions.
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llvm-svn: 155004
2012-04-18 14:18:57 +00:00
d5c6a63a50
Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.
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llvm-svn: 155002
2012-04-18 14:09:07 +00:00
41f1fcd80e
Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
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llvm-svn: 155001
2012-04-18 13:12:50 +00:00
a2944116dc
Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.
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llvm-svn: 155000
2012-04-18 13:02:55 +00:00
9da1918c84
Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.
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llvm-svn: 154999
2012-04-18 12:48:43 +00:00
29ae538647
Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
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instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .
llvm-svn: 154884
2012-04-17 00:49:27 +00:00
72f18bbcff
Fixed a case of ARM disassembly getting an assert on a bad encoding
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of a VST instruction.
llvm-svn: 154544
2012-04-11 22:40:17 +00:00
d2980cd041
Fix ARM disassembly of VLD instructions with writebacks. And add test a case
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for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .
llvm-svn: 154459
2012-04-11 00:25:40 +00:00
aca6c822e6
Fix a number of problems with ARM fused multiply add/subtract instructions.
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1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676
llvm-svn: 154456
2012-04-11 00:13:00 +00:00
af3c79f0ac
Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.
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llvm-svn: 154101
2012-04-05 16:19:29 +00:00
d365397daa
Added support for handling unpredictable arithmetic instructions on ARM.
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llvm-svn: 154100
2012-04-05 16:13:15 +00:00
ac37acd31b
Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node.
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llvm-svn: 153874
2012-04-02 15:20:39 +00:00
f33086052d
Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu
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* Removed test/lib/llvm.exp - it is no longer needed
* Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files
left in the test suite so this code is no longer required. test/lit.cfg is
now much shorter and clearer
* Removed a lot of duplicate code in lit.local.cfg files that need access to
the root configuration, by adding a "root" attribute to the TestingConfig
object. This attribute is dynamically computed to provide the same
information as was previously provided by the custom getRoot functions.
* Documented the config.root attribute in docs/CommandGuide/lit.pod
llvm-svn: 153408
2012-03-25 09:02:19 +00:00
4afd7d2316
Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
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llvm-svn: 153252
2012-03-22 14:14:49 +00:00
d213f2111a
Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
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llvm-svn: 153251
2012-03-22 13:24:43 +00:00
a6ea32afdd
Added soft fail cases for the disassembler when decoding MUL instructions on ARM.
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llvm-svn: 153250
2012-03-22 13:14:39 +00:00
7e7d5eefb2
Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test
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case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .
llvm-svn: 153218
2012-03-21 20:54:32 +00:00
32a49333ec
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
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llvm-svn: 153089
2012-03-20 15:54:56 +00:00
520eb3ba8a
Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.
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llvm-svn: 152127
2012-03-06 18:33:12 +00:00
f0269b4270
Change ARMInstPrinter::printPredicateOperand() so it will not abort if it
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runs into the undefined 15 condition code value.
llvm-svn: 151844
2012-03-01 22:13:02 +00:00
924f9a671d
Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
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Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.
llvm-svn: 150664
2012-02-16 06:28:33 +00:00
d9ba4fd48f
Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage.
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llvm-svn: 150169
2012-02-09 10:56:31 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
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Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
0ac9058f89
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
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llvm-svn: 144683
2011-11-15 19:55:00 +00:00
3e2c6f380c
ARM VLDR/VSTR instructions don't need a size suffix.
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Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
llvm-svn: 144583
2011-11-14 23:03:21 +00:00
69d57cf9c4
Simplify some uses of utohexstr.
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As a side effect hex is printed lowercase instead of uppercase now.
llvm-svn: 144013
2011-11-07 21:00:59 +00:00
fbb704f551
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
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llvm-svn: 143557
2011-11-02 18:03:14 +00:00
69e54a740c
Fix disassembly of some VST1 instructions.
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llvm-svn: 143507
2011-11-01 22:18:13 +00:00
40703f4252
More not-crashing NEON disassembly updates for the vld refactoring.
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llvm-svn: 143351
2011-10-31 17:17:32 +00:00
5524ce7d82
Fix illegal disassembly testcase.
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llvm-svn: 143231
2011-10-28 21:45:09 +00:00
dde461c8b1
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
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llvm-svn: 143208
2011-10-28 18:02:13 +00:00
f211416dde
Add testcase for r143162.
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llvm-svn: 143163
2011-10-27 22:54:14 +00:00
295b1e84ce
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
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llvm-svn: 142817
2011-10-24 18:04:29 +00:00
16c8fc5191
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
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llvm-svn: 142626
2011-10-20 22:23:58 +00:00
608c60c773
Fix decoding tests for fixed MSR encodings.
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llvm-svn: 142624
2011-10-20 22:01:48 +00:00
54a20ed0f1
Thumb2 assembly parsing and encoding for LDC/STC.
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llvm-svn: 141811
2011-10-12 20:54:17 +00:00
8c799c9826
Update test for r141704.
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llvm-svn: 141705
2011-10-11 20:18:50 +00:00
21efa7d6e1
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
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Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
287d6ef088
Fix an incorrect decoder test.
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llvm-svn: 140579
2011-09-26 23:08:34 +00:00
b75772201f
Fix incorrect disassembly test.
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llvm-svn: 140423
2011-09-23 22:05:54 +00:00
737beaf86d
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
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llvm-svn: 140420
2011-09-23 21:26:40 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
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llvm-svn: 140415
2011-09-23 21:07:25 +00:00
f52c68f0ca
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
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llvm-svn: 140283
2011-09-21 23:44:46 +00:00
2b35d7cff1
Port over more Thumb2 encoding tests to decoding tests.
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llvm-svn: 140152
2011-09-20 17:44:48 +00:00
ddfcec92d9
Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests.
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llvm-svn: 140032
2011-09-19 18:07:10 +00:00
09a9b6b953
Add a testcase for another corner-case decoding.
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llvm-svn: 139970
2011-09-16 23:15:29 +00:00
3ca958cd19
Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).
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llvm-svn: 139964
2011-09-16 22:29:48 +00:00
9764bced10
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
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llvm-svn: 139958
2011-09-16 22:17:02 +00:00
fe82365cb0
Fix disassembly of Thumb2 LDRSH with a #-0 offset.
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llvm-svn: 139943
2011-09-16 21:08:33 +00:00
30fc19a6dd
Port over more Thumb2 assembly tests to disassembly tests.
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llvm-svn: 139915
2011-09-16 17:56:04 +00:00
b489e3b408
Port over more Thumb2 assembly tests to disassembly tests.
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llvm-svn: 139912
2011-09-16 17:22:48 +00:00
3eb2470eed
Make use of Eli's FileCheck sorcery to improve this test.
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llvm-svn: 139645
2011-09-13 21:37:50 +00:00
7f0e98fd7f
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
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llvm-svn: 139639
2011-09-13 20:46:26 +00:00
2a206c44b7
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
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llvm-svn: 139542
2011-09-12 21:28:46 +00:00
a9ebf6fb64
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
...
llvm-svn: 139522
2011-09-12 18:56:30 +00:00
53db43b560
LDM writeback is not allowed if Rn is in the target register list.
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llvm-svn: 139432
2011-09-09 23:13:33 +00:00
5bfb0e0a85
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
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llvm-svn: 139422
2011-09-09 22:24:36 +00:00
2fefa427d5
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
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llvm-svn: 139328
2011-09-08 22:42:49 +00:00
7db8d697cf
Thumb2 assembly parsing and encoding for LDRD(immediate).
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Refactor operand handling for STRD as well. Tests for that forthcoming.
llvm-svn: 139322
2011-09-08 22:07:06 +00:00
18d17aa6b7
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
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llvm-svn: 139256
2011-09-07 21:10:42 +00:00
8067df9503
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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llvm-svn: 139250
2011-09-07 19:42:28 +00:00
5d5f4862eb
Update test for 139243
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llvm-svn: 139244
2011-09-07 18:40:06 +00:00
cd5612d3a5
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
...
llvm-svn: 139240
2011-09-07 17:55:19 +00:00
b041e866b0
Port more encoding tests over to Thumb2 decoding tests.
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llvm-svn: 139171
2011-09-06 20:26:34 +00:00
2fa06a7226
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
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llvm-svn: 138840
2011-08-30 22:58:27 +00:00
2e282257ed
Port Thumb2 assembler tests over to disassembler tests.
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llvm-svn: 138822
2011-08-30 20:03:11 +00:00
b205c029a4
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
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llvm-svn: 138675
2011-08-26 23:32:08 +00:00
16d33f36d5
invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.
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llvm-svn: 138653
2011-08-26 20:43:14 +00:00
a01bcbfc80
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
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llvm-svn: 138635
2011-08-26 18:09:22 +00:00
f3b6507e26
Add a testcase for r138625.
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llvm-svn: 138626
2011-08-26 06:45:08 +00:00
5e30972cff
Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.
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llvm-svn: 138575
2011-08-25 18:30:18 +00:00
16fd0d96f2
Port over more encoding tests to decoding tests.
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llvm-svn: 138441
2011-08-24 17:08:34 +00:00
924bcfc92f
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.
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llvm-svn: 138341
2011-08-23 17:51:38 +00:00
041dba6dec
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
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llvm-svn: 138337
2011-08-23 17:37:32 +00:00
dcea63236e
Port more assemble tests over to disassembly tests.
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llvm-svn: 138336
2011-08-23 17:26:35 +00:00
1346d79b4b
t2SMLAD is a four-register instruction, not a three-register one.
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llvm-svn: 138301
2011-08-22 23:31:45 +00:00
f94b7b7d57
Correct operand naming of t2USAT16 to allow proper decoding.
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llvm-svn: 138300
2011-08-22 23:27:47 +00:00
5e9989a920
Match operand naming to allow correct decoding of t2LDRSH_POST.
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llvm-svn: 138298
2011-08-22 23:22:05 +00:00
a743409ec8
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
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llvm-svn: 138292
2011-08-22 23:10:16 +00:00
061738a680
Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing.
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llvm-svn: 138273
2011-08-22 21:34:00 +00:00
df698b032c
Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing.
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llvm-svn: 138269
2011-08-22 20:27:12 +00:00
721c3704da
Fix another batch of VLD/VST decoding crashes discovered by randomized testing.
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llvm-svn: 138255
2011-08-22 18:42:13 +00:00
ac92e77bb8
Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing.
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llvm-svn: 138251
2011-08-22 18:22:06 +00:00
fe29fe431d
Port another swathe of Thumb1 encoding tests over to decoding tests.
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llvm-svn: 138250
2011-08-22 18:05:49 +00:00
b49813206b
Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests.
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llvm-svn: 138246
2011-08-22 17:56:58 +00:00
96b7ad2e17
STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate.
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Found by randomized testing.
llvm-svn: 138003
2011-08-18 22:47:44 +00:00
192a760b54
Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset.
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llvm-svn: 138000
2011-08-18 22:31:17 +00:00
67d6f11974
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
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Fixes a large class of disassembler crashes found by randomized testing.
llvm-svn: 137995
2011-08-18 22:11:02 +00:00
90103ccc05
Thumb assembly parsing and encoding for LDM instruction.
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Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
llvm-svn: 137986
2011-08-18 21:50:53 +00:00
627021d7c0
More Thumb1 decoding tests.
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llvm-svn: 137974
2011-08-18 20:05:06 +00:00
9f9371ccb3
Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed.
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llvm-svn: 137960
2011-08-18 18:03:02 +00:00
ec3884c50a
Port over BL/BLX to disassembly tests.
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llvm-svn: 137954
2011-08-18 17:43:52 +00:00
a90896397b
Port new Thumb1 encoding tests over to decoding tests.
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llvm-svn: 137902
2011-08-17 23:37:33 +00:00
d40d838cc4
Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file.
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llvm-svn: 137840
2011-08-17 18:21:36 +00:00
a4043c4b32
Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment.
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Patch by James Molloy.
llvm-svn: 137830
2011-08-17 17:44:15 +00:00
53440984b3
Add a test file for Thumb2 NEON.
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llvm-svn: 137687
2011-08-15 23:42:20 +00:00
5286bd2d01
Add some more comprehensive VFP decoding tests.
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llvm-svn: 137657
2011-08-15 21:29:01 +00:00
1d5d2cac8c
Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.
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Patch by James Molloy.
llvm-svn: 137647
2011-08-15 20:51:32 +00:00
944f4923a4
Add a test for Thumb1 LDRSH decoding.
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llvm-svn: 137645
2011-08-15 20:15:43 +00:00
f746b0ec53
Add testcase for STRH. Patch by James Molloy.
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llvm-svn: 137644
2011-08-15 20:12:03 +00:00
61a3ece665
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
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llvm-svn: 137641
2011-08-15 20:08:25 +00:00
3157f2eebe
Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.
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llvm-svn: 137636
2011-08-15 19:00:06 +00:00
b9d82f411c
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
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llvm-svn: 137635
2011-08-15 18:44:44 +00:00
2d1d7a11f8
Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
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llvm-svn: 137502
2011-08-12 20:36:11 +00:00
ed6d3e813e
Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions.
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llvm-svn: 137495
2011-08-12 19:42:45 +00:00
3a850f28d0
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
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llvm-svn: 137347
2011-08-11 20:47:56 +00:00
887c0b1358
Improve operand validation for Thumb2 addressing modes.
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llvm-svn: 137344
2011-08-11 20:40:40 +00:00
6066340301
Continue to tighten decoding by performing more operand validation.
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llvm-svn: 137340
2011-08-11 20:21:46 +00:00
3477f2cea5
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
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llvm-svn: 137325
2011-08-11 19:00:18 +00:00
0e15b48f3c
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
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llvm-svn: 137323
2011-08-11 18:55:42 +00:00
e33c95d39b
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
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llvm-svn: 137322
2011-08-11 18:41:59 +00:00
ed25385227
Improve error checking in the new ARM disassembler. Patch by James Molloy.
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llvm-svn: 137320
2011-08-11 18:24:51 +00:00
c86a5bd219
Add initial support for decoding NEON instructions in Thumb2 mode.
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llvm-svn: 137236
2011-08-10 19:01:10 +00:00
8059f0cf8d
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
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llvm-svn: 137189
2011-08-10 00:03:03 +00:00
92b942b1b5
Tighten operand checking of register-shifted-register operands.
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llvm-svn: 137180
2011-08-09 23:33:27 +00:00
Mihai Popa