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127292 Commits

Author SHA1 Message Date
Brendon Cahoon 5edcf8822d Updated instruction table due to addded intrinsics. 
llvm-svn: 156644
 2012-05-11 21:10:16 +00:00
Akira Hatanaka c37eddf7a7 Fix handling of vector return types. 
A vector should be returned via the hidden pointer argument except if its size
is equal to or smaller than 16-bytes and the target ABI is N32 or N64.

llvm-svn: 156642
 2012-05-11 21:01:17 +00:00
Filipe Cabecinhas 1a96ef800b Make every Python API __len__() method return a PyIntObject. 
swig 2.0+ seems to default to using PyLongObjects, but the __len__()
method _must_ return a PyIntObject.

llvm-svn: 156639
 2012-05-11 20:39:42 +00:00
Filipe Cabecinhas 0bfed4bc7a Fix SBProcess::ReadMemory's typemap to handle PyLongObjects. 
llvm-svn: 156638
 2012-05-11 20:38:28 +00:00
Filipe Cabecinhas 0c543ea186 Make issue_11588/Test11588 work with a recent swig that converts ints to PyLongObjects 
llvm-svn: 156637
 2012-05-11 20:37:34 +00:00
Sirish Pande 95d0117bb3 Remove warnings from HexagonVLIWPacketizer. 
llvm-svn: 156636
 2012-05-11 20:00:34 +00:00
Duncan Sands 1367e49f6b Some release notes for dragonegg. 
llvm-svn: 156635
 2012-05-11 19:59:43 +00:00
Brendon Cahoon 31f8723ef3 Hexagon constant extender support. 
Patch by Jyotsna Verma.

llvm-svn: 156634
 2012-05-11 19:56:59 +00:00
Chad Rosier 06e34d9220 Typo. 
llvm-svn: 156633
 2012-05-11 19:43:29 +00:00
Chad Rosier 3268692aa8 [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Minor cleanup. 
llvm-svn: 156632
 2012-05-11 19:40:25 +00:00
Sirish Pande 83ccb6ce08 Hexagon V5 intrinsics support. 
llvm-svn: 156631
 2012-05-11 19:39:13 +00:00
Sirish Pande 84dce5d0c2 Hexagon V5 intrinsics support in clang. 
llvm-svn: 156630
 2012-05-11 19:39:08 +00:00
Jakob Stoklund Olesen 3f3eb18010 Defer computation of SuperRegs. 
Don't compute the SuperRegs list until the sub-register graph is
completely finished. This guarantees that the list of super-registers is
properly topologically ordered, and has no duplicates.

llvm-svn: 156629
 2012-05-11 19:01:01 +00:00
Chad Rosier 90f9afe659 [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg 
retval.  Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796

llvm-svn: 156628
 2012-05-11 18:51:55 +00:00
Jim Ingham 923886ce2c Don't try to use "OkayToDiscard" to mean BOTH this plan is a user plan or not AND unwind on error. 
rdar://problem/11419156

llvm-svn: 156627
 2012-05-11 18:43:38 +00:00
Greg Clayton 4ae4160974 Fixed an issue in the platform options where if no architecture was specified where the platform would fail to select itself with something like: 
(lldb) platfrom select remote-ios

llvm-svn: 156626
 2012-05-11 18:37:58 +00:00
Nuno Lopes e2cfd3ce95 objectsize: add a few more tests and fix a bug 
llvm-svn: 156625
 2012-05-11 18:25:29 +00:00
Jim Ingham db81e83c2e Add "echo" -> "script print". 
llvm-svn: 156624
 2012-05-11 18:01:15 +00:00
Chad Rosier 519b12f927 [fast-isel] Rather then assert (or segfault in a non-asserts build), fall back 
to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796

llvm-svn: 156622
 2012-05-11 17:41:06 +00:00
Chad Rosier 466d3d8faa The return type is an unsigned, not a bool. 
llvm-svn: 156621
 2012-05-11 16:41:38 +00:00
Manman Ren 0d5ec28ccc Add space before an open parenthesis in control flow statements. 
llvm-svn: 156620
 2012-05-11 15:36:46 +00:00
Kostya Serebryany 0e6705ec67 [tsan] run output tests in parallel 
llvm-svn: 156617
 2012-05-11 14:58:20 +00:00
Kostya Serebryany 07c4805175 [tsan] run more kinds of builds as presubmit test (and fix gcc debug build) 
llvm-svn: 156616
 2012-05-11 14:42:24 +00:00
Preston Gurd 09de6ae399 Added X86 Atom latencies to X86InstrMMX.td. 
llvm-svn: 156615
 2012-05-11 14:27:12 +00:00
Kostya Serebryany 1136764ab0 [tsan] a bit more lint 
llvm-svn: 156614
 2012-05-11 13:49:53 +00:00
Stepan Dyatkovskiy 05b46b3745 PR1255: ConstantRangesSet and CRSBuilder classes moved from include/llvm to include/llvm/Support. 
llvm-svn: 156613
 2012-05-11 10:34:23 +00:00
Hans Wennborg addad7388d Fix test/CodeGen/X86/tls-pie.ll. 
llvm-svn: 156612
 2012-05-11 10:19:54 +00:00
Hans Wennborg f9d0e44b82 Implement initial-exec TLS model for 32-bit PIC x86 
This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).

llvm-svn: 156611
 2012-05-11 10:11:01 +00:00
Silviu Baranga ddc67a7655 Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. 
llvm-svn: 156609
 2012-05-11 09:28:27 +00:00
Silviu Baranga 5a719f9b9a Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. 
llvm-svn: 156608
 2012-05-11 09:10:54 +00:00
Richard Smith 10ff50d7d8 PR11857: When the wrong number of arguments are provided for a function 
which expects exactly one argument, include the name of the argument in
the diagnostic text. Patch by Terry Long!

llvm-svn: 156607
 2012-05-11 05:16:41 +00:00
Rafael Espindola 5f4b32f9d7 Fix a use after free when the streamer is destroyed. Fixes pr12622. 
llvm-svn: 156606
 2012-05-11 03:42:13 +00:00
Greg Clayton 341039faca More fixes to "malloc_history". 
llvm-svn: 156605
 2012-05-11 02:42:36 +00:00
Argyrios Kyrtzidis 74d7f15aed Add a test case for going through typedefs until we reach "BOOL", that NSAPI::isObjCTypedef() is doing. 
llvm-svn: 156604
 2012-05-11 01:53:27 +00:00
Akira Hatanaka e37614438f Fix a misleading comment. 
llvm-svn: 156603
 2012-05-11 01:45:15 +00:00
Jim Grosbach dc1e36e9f5 Tidy up. Trailing whitespace. 
llvm-svn: 156602
 2012-05-11 01:41:30 +00:00
Jim Grosbach 3658412afc Tidy up. Trailing whitespace. 
llvm-svn: 156601
 2012-05-11 01:39:13 +00:00
Eli Friedman e0a64d83fc Fix a minor logic mistake transforming compares in instcombine. PR12514. 
llvm-svn: 156600
 2012-05-11 01:32:59 +00:00
Manman Ren dc8ad0058f ARM: peephole optimization to remove cmp instruction 
This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411
llvm-svn: 156599
 2012-05-11 01:30:47 +00:00
Rafael Espindola 92d49459ab Fix a recent regression with the merging of format attributes. 
llvm-svn: 156597
 2012-05-11 00:36:07 +00:00
Greg Clayton 60bb58f669 Modified the symbolication.Image object to store its uuid as a uuid.UUID object and made an accessor for getting a normalized UUID value out of the image object. 
Modified the crashlog darwin module to always create a uuid.UUID object when making the symbolication.Image objects. Also modified it to handle some more types of crash log files and improved the register reading for thread registers of crashed threads.

llvm-svn: 156596
 2012-05-11 00:30:14 +00:00
Greg Clayton c0debe8566 Don't intercept the quit command and override what is was doing. This was causing the "lldb" command line to deadlock when the quit command was executed sometimes. 
llvm-svn: 156595
 2012-05-11 00:27:51 +00:00
Dan Gohman dfab443ae8 Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(), 
but it generates int3 on x86 instead of ud2.

llvm-svn: 156593
 2012-05-11 00:19:32 +00:00
Eric Christopher f6a6346d67 For final output files create them with mode 0664 to match other 
compilers and expected defaults.

Part of rdar://11325849

llvm-svn: 156592
 2012-05-11 00:10:07 +00:00
Eric Christopher b6148ed72c Allow unique_file to take a mode for file permissions, but default 
to user only read/write.

Part of rdar://11325849

llvm-svn: 156591
 2012-05-11 00:07:44 +00:00
Chad Rosier 8244b1dc7e Fix intendation. 
llvm-svn: 156589
 2012-05-10 23:38:07 +00:00
Greg Clayton 7200ed1b94 "--stack-history" now works if you have MallocStackLogggingNoCompact defined in your app's environment. 
llvm-svn: 156588
 2012-05-10 23:37:52 +00:00
Jakob Stoklund Olesen c08df9e5fd Compute secondary sub-registers. 
The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:

  Q0_Q1 = [Q0, Q1],  Q0 = [D0, D1], Q1 = [D2, D3]

But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.

This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.

This will eventually enable the coalescer to handle copies of skewed
sub-registers.

llvm-svn: 156587
 2012-05-10 23:27:10 +00:00
Greg Clayton 370f5fd20a Fixed a build error. 
llvm-svn: 156586
 2012-05-10 23:20:50 +00:00
Nuno Lopes f573030391 objectsize: add support for GEPs with non-constant indexes 
add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag

llvm-svn: 156585
 2012-05-10 23:17:35 +00:00