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24 Commits

Author SHA1 Message Date
Krzysztof Parzyszek 1d52a850b3 [Hexagon] Remove leftover assert 
llvm-svn: 324352
 2018-02-06 15:15:13 +00:00
Krzysztof Parzyszek 88f11003a0 [Hexagon] Split HVX operations on vector pairs 
Vector pairs are legal types, but not every operation can work on pairs.
For those operations that are legal for single vectors, generate a concat
of their results on pair halves.

llvm-svn: 324350
 2018-02-06 14:24:57 +00:00
Krzysztof Parzyszek 7b52cf1d7f [Hexagon] Add helper functions to identify single/pair vector types, NFC 
llvm-svn: 324349
 2018-02-06 14:21:31 +00:00
Krzysztof Parzyszek 69f1d7e370 [Hexagon] Handle lowering of SETCC via setCondCodeAction 
It was expanded directly into instructions earlier. That was to avoid
loads from a constant pool for a vector negation: "xor x, splat(i1 -1)".
Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of
all true and all false values, and handle setcc with negations through
selection patterns.

llvm-svn: 324348
 2018-02-06 14:16:52 +00:00
Krzysztof Parzyszek 02947b7112 [Hexagon] Use V6_vmpyih for halfword multiplication 
Unlike V6_vmpyhv, it produces the result in the exact form that is
expected without the need for a shuffle.

llvm-svn: 324241
 2018-02-05 15:40:06 +00:00
Krzysztof Parzyszek 15efa98f63 [Hexagon] Rename HexagonISelLowering::getNode to getInstr, NFC 
llvm-svn: 323916
 2018-01-31 21:17:03 +00:00
Krzysztof Parzyszek 1108ee2496 [Hexagon] Implement HVX codegen for vector shifts 
llvm-svn: 323914
 2018-01-31 20:49:24 +00:00
Krzysztof Parzyszek b843f75179 [Hexagon] Handle SETCC on vector pairs in lowering 
llvm-svn: 323911
 2018-01-31 20:46:55 +00:00
Krzysztof Parzyszek 82a83391d3 [Hexagon] Handle BUILD_VECTOR from undef values in buildHvxVectorReg 
llvm-svn: 323889
 2018-01-31 16:52:15 +00:00
Krzysztof Parzyszek 90ca4e8b0c [Hexagon] Generate constant splats instead of loads from constant pool 
llvm-svn: 323568
 2018-01-26 21:54:56 +00:00
Hiroshi Inoue 0909ca132f [NFC] fix trivial typos in comments and documents 
"in in" -> "in", "on on" -> "on" etc.

llvm-svn: 323508
 2018-01-26 08:15:29 +00:00
Eric Christopher a8bdf5328d Remove set but unused variable IsUndef. 
llvm-svn: 323295
 2018-01-24 01:51:57 +00:00
Krzysztof Parzyszek ae3e934bd6 [Hexagon] Fix unused variable warning in release build 
llvm-svn: 323233
 2018-01-23 18:16:52 +00:00
Krzysztof Parzyszek 3780a0e1fa [Hexagon] Implement basic vector operations on vectors vNi1 
In addition to that, make sure that there are no boolean vector types that
are associated with multiple register classes. Specifically, remove v32i1
and v64i1 from integer register classes. These types will correspond to
results of vector comparisons, and as such should belong to the vector
predicate class. Having them in scalar registers as well makes legalization
ambiguous.

llvm-svn: 323229
 2018-01-23 17:53:59 +00:00
Krzysztof Parzyszek 7fb738ab71 [Hexagon] Implement signed and unsigned multiply-high for vectors 
llvm-svn: 322499
 2018-01-15 18:43:55 +00:00
Krzysztof Parzyszek 0f5d976aa0 [Hexagon] Add a bitcast to required type in LowerHvxMul 
llvm-svn: 321893
 2018-01-05 20:45:34 +00:00
Krzysztof Parzyszek e4ce92cabf [Hexagon] Allow construction of HVX vector predicates 
Handle BUILD_VECTOR of boolean values.

llvm-svn: 321220
 2017-12-20 20:49:43 +00:00
Krzysztof Parzyszek 6b589e593d [Hexagon] Generate HVX code for vector sign-, zero- and any-extends 
Implement any-extend as zero-extend.

llvm-svn: 321004
 2017-12-18 18:32:27 +00:00
Krzysztof Parzyszek 470760533a [Hexagon] Generate HVX code for comparisons and selects 
llvm-svn: 320744
 2017-12-14 21:28:48 +00:00
Krzysztof Parzyszek 708c9f5947 [Hexagon] Remove vectors of i64 from valid HVX types 
HVX does not support operations on 64-bit integers.

llvm-svn: 320722
 2017-12-14 18:35:24 +00:00
Krzysztof Parzyszek 152414595b [Hexagon] Crash in instruction selection for insert_vector_elt for HVX 
A wrong type was passed to insertVector, causing an out-of-bounds value
to be added an an operand to HexagonISD::INSERT. This later failed in
instruction selection.

llvm-svn: 320369
 2017-12-11 14:46:06 +00:00
Krzysztof Parzyszek 039d4d9286 [Hexagon] Generate HVX code for basic arithmetic operations 
Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32.

llvm-svn: 320063
 2017-12-07 17:37:28 +00:00
Tim Shen 7654ed03e3 [Hexagon] Suppress warnings on unused variables defind for asserts. 
llvm-svn: 319940
 2017-12-06 19:22:19 +00:00
Krzysztof Parzyszek 7d37dd8902 [Hexagon] Generate HVX code for vector construction and access 
Support for:
  - build vector,
  - extract vector element, subvector,
  - insert vector element, subvector,
  - shuffle.

llvm-svn: 319901
 2017-12-06 16:40:37 +00:00