6c61451011
Add more assembly opcodes for SSE compare instructions
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llvm-svn: 107823
2010-07-07 22:24:03 +00:00
1c349f18f8
Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.
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llvm-svn: 107820
2010-07-07 22:15:37 +00:00
32a600b494
Print undefined/unknown debug value as "undef".
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llvm-svn: 107818
2010-07-07 21:52:21 +00:00
e4ba2aa0c4
grammar and trailing whitespace
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llvm-svn: 107811
2010-07-07 21:06:51 +00:00
ddaf0099a5
Allow copies between GR8_ABCD_L and GR8_ABCD_H.
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This fixes PR7540.
llvm-svn: 107809
2010-07-07 20:33:27 +00:00
e7ccc51cc1
Implement bottom-up fast-isel. This has the advantage of not requiring
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a separate DCE pass over MachineInstrs.
llvm-svn: 107804
2010-07-07 19:20:32 +00:00
2d4d01d0de
Add X86FastISel support for return statements. This entails refactoring
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a bunch of stuff, to allow the target-independent calling convention
logic to be employed.
llvm-svn: 107800
2010-07-07 18:32:53 +00:00
fd8060335b
Add AVX AES instructions
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llvm-svn: 107798
2010-07-07 18:24:20 +00:00
ffe64b1ee5
Give FunctionLoweringInfo an MBB member, avoiding the need to pass it
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around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.
llvm-svn: 107791
2010-07-07 16:47:08 +00:00
87fb4e8fcd
Simplify FastISel's constructor by giving it a FunctionLoweringInfo
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instance, rather than pointers to all of FunctionLoweringInfo's
members.
This eliminates an NDEBUG ABI sensitivity.
llvm-svn: 107789
2010-07-07 16:29:44 +00:00
fe7532a308
Split the SDValue out of OutputArg so that SelectionDAG-independent
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code can do calling-convention queries. This obviates OutputArgReg.
llvm-svn: 107786
2010-07-07 15:54:55 +00:00
6d122aef97
Add AVX SSE4.2 instructions
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llvm-svn: 107752
2010-07-07 03:39:29 +00:00
3df55b2d6f
Use only one multiclass to pinsrq instructions
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llvm-svn: 107750
2010-07-07 01:43:01 +00:00
fd6c808154
Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes
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llvm-svn: 107749
2010-07-07 01:33:38 +00:00
8f5472a8e8
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
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llvm-svn: 107747
2010-07-07 01:14:56 +00:00
6430c7350d
Add AVX SSE4.1 extractps and pinsr instructions
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llvm-svn: 107746
2010-07-07 01:01:13 +00:00
5bc8a79e7f
Also use REG_SEQUENCE for VTBX instructions.
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llvm-svn: 107743
2010-07-07 00:08:54 +00:00
3198483851
Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where
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they've been tested to work.
llvm-svn: 107742
2010-07-07 00:07:57 +00:00
f3116ebe96
Add AVX SSE4.1 Extract Integer instructions
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llvm-svn: 107740
2010-07-07 00:07:24 +00:00
dc0a0659be
By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather
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than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.
llvm-svn: 107734
2010-07-06 23:44:52 +00:00
3ed511bc6b
Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
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allocated to consecutive registers.
llvm-svn: 107730
2010-07-06 23:36:25 +00:00
ce65663330
Accept RIP-relative symbols with 'i' constraint, and
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print the (%rip) only if the 'a' modifier is present.
PR 7528.
llvm-svn: 107727
2010-07-06 23:27:00 +00:00
48deb12593
Track defs for all aliases in NEONMoveFix.
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This means that an instruction defining an S register will affect the domain of
the parent D register.
llvm-svn: 107725
2010-07-06 23:26:23 +00:00
1f9ad516c6
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
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llvm-svn: 107723
2010-07-06 23:15:17 +00:00
35702d27c4
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
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llvm-svn: 107720
2010-07-06 23:01:41 +00:00
13f0260e76
Fix comment from previous patch
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llvm-svn: 107717
2010-07-06 22:38:32 +00:00
e2bd058d32
Add AVX vblendvpd, vblendvps and vpblendvb instructions
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Update VEX encoding to support those new instructions
llvm-svn: 107715
2010-07-06 22:36:24 +00:00
ee0cb70381
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
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SelectBasicBlock doesn't needs its BasicBlock argument.
llvm-svn: 107712
2010-07-06 22:19:37 +00:00
a3ca21b228
Propagate debug loc.
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llvm-svn: 107710
2010-07-06 22:08:15 +00:00
4c1ca29039
Represent NEON load/store alignments in bytes, not bits.
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llvm-svn: 107701
2010-07-06 21:26:18 +00:00
3439629239
Reapply r107655 with fixes; insert the pseudo instruction into
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the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
llvm-svn: 107691
2010-07-06 20:24:04 +00:00
23a7593534
Fix PR7545 crash.
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llvm-svn: 107678
2010-07-06 18:18:32 +00:00
7c510aa7bc
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
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if profitable.
llvm-svn: 107673
2010-07-06 16:24:34 +00:00
f4f04107ef
Revert r107655.
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llvm-svn: 107668
2010-07-06 15:49:48 +00:00
2b2a1c3c86
Make getMinimalPhysRegClass' comment mention what makes it different
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from getPhysicalRegisterRegClass.
llvm-svn: 107660
2010-07-06 15:31:55 +00:00
12205645a6
Fix a bunch of custom-inserter functions to handle the case where
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the pseudo instruction is not at the end of the block.
llvm-svn: 107655
2010-07-06 15:18:19 +00:00
2ad0c779c3
Fix up -fstack-protector on linux to use the segment
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registers. Split out testcases per architecture and os
now.
Patch from Nelson Elhage.
llvm-svn: 107640
2010-07-06 05:18:56 +00:00
d429846eca
Have the X86 backend use Triple instead of a string and some enums.
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llvm-svn: 107625
2010-07-05 19:26:33 +00:00
d5ac287140
Remove some unused/redundant code.
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llvm-svn: 107622
2010-07-05 18:40:09 +00:00
c4a7073db3
more tidying.
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llvm-svn: 107615
2010-07-05 05:53:14 +00:00
7b909ac785
some notes about suboptimal insertps's
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llvm-svn: 107613
2010-07-05 05:48:41 +00:00
6d60a14251
rip out even more sporadic v2f32 support.
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llvm-svn: 107610
2010-07-05 04:38:33 +00:00
feb2467bf4
rip out the various v2f32 "mmx" handling logic, now that
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v2f32 is illegal on x86.
llvm-svn: 107609
2010-07-05 04:36:27 +00:00
45cc4d74a3
Just rip v2f32 support completely out of the X86 backend. In
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the example in the testcase, we now generate:
_test1: ## @test1
movss 4(%esp), %xmm0
addss 8(%esp), %xmm0
movl 12(%esp), %eax
movss %xmm0, (%eax)
ret
instead of:
_test1: ## @test1
subl $20, %esp
movl 24(%esp), %eax
movq %mm0, (%esp)
movq %mm0, 8(%esp)
movss (%esp), %xmm0
addss 12(%esp), %xmm0
movss %xmm0, (%eax)
addl $20, %esp
ret
v2f32 support did not work reliably because most of the X86
backend didn't know it was legal. It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode. If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32. However,
we generally don't try very hard to be abi compatible on gcc
extended vectors.
llvm-svn: 107601
2010-07-04 23:07:25 +00:00
681b926d54
fix PR7518 - terrible codegen of <2 x float>, by only marking
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v2f32 as legal in 32-bit mode. It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.
llvm-svn: 107600
2010-07-04 22:57:10 +00:00
cb948d3329
indentation
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llvm-svn: 107599
2010-07-04 22:56:10 +00:00
199cacf179
Revert r107583. I no longer think that this is the way to solve the problem.
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llvm-svn: 107585
2010-07-04 09:16:57 +00:00
701aa053b9
Mark sse_load_f32 and sse_load_f64 as having memory operands
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(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.
llvm-svn: 107583
2010-07-04 08:59:55 +00:00
c8f595212f
Minor amendment to switch-lowering improvement.
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llvm-svn: 107569
2010-07-03 08:43:32 +00:00
836fdbc85b
Note switch-lowering inefficiency.
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llvm-svn: 107565
2010-07-03 07:38:12 +00:00
Bruno Cardoso Lopes