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27041 Commits

Author SHA1 Message Date
Jim Laskey e7d2c24a7d Make it simplier to dump DAGs while in DAGCombiner. Remove a nasty optimization. 
llvm-svn: 31009
 2006-10-17 19:33:52 +00:00
Rafael Espindola 2d7d14262a remove extra [] in stores 
llvm-svn: 31008
 2006-10-17 18:29:14 +00:00
Chris Lattner bca3e297fe Enable deleting branches to successor blocks. With the previous patches, 
branch folding can now compile stuff like this:

void foo(int W, int X, int Y, int Z) {
  if (W & 1) {
    for (; X;--X) bar();
  } else if (W & 2) {
    for (; Y;--Y) bar();
  } else if (W & 4) {
    for (; Z;--Z) bar();
  } else if (W & 8) {
    for (; W;--W) bar();
  }

  if (W) {
    bar();
  }
}

contrived testcase where loops exits all end up merging together.  To have
the loop merges be:

...
        cmplw cr0, r30, r27
        bne cr0, LBB1_14        ;bb38
LBB1_16:        ;cond_next48.loopexit
        mr r27, r29
LBB1_20:        ;cond_next48
        cmplwi cr0, r27, 0
        beq cr0, LBB1_22        ;UnifiedReturnBlock
...

instead of:


...
        cmplw cr0, r30, r27
        bne cr0, LBB1_14        ;bb38
LBB1_16:        ;cond_next48.loopexit
        mr r27, r29
        b LBB1_20       ;cond_next48
LBB1_17:        ;cond_next48.loopexit1
        b LBB1_20       ;cond_next48
LBB1_18:        ;cond_next48.loopexit2
        b LBB1_20       ;cond_next48
LBB1_19:        ;cond_next48.loopexit3
LBB1_20:        ;cond_next48
        cmplwi cr0, r27, 0
        beq cr0, LBB1_22        ;UnifiedReturnBlock
...


This is CodeGen/PowerPC/branch-opt.ll

llvm-svn: 31006
 2006-10-17 18:16:40 +00:00
Chris Lattner b7f67a23e0 new testcase 
llvm-svn: 31005
 2006-10-17 18:14:39 +00:00
Chris Lattner a61f0105bd add support for inserting an uncond branch 
llvm-svn: 31003
 2006-10-17 18:06:55 +00:00
Rafael Espindola 19398ec86e initial implementation of addressing mode 5 
llvm-svn: 31002
 2006-10-17 18:04:53 +00:00
Jim Laskey d24b913a61 Clean up interface to getGlobalLinkName. 
llvm-svn: 31001
 2006-10-17 17:17:24 +00:00
Chris Lattner 56c9d2597e Reenable this pass, fixing the bugs in it. 
It now correctly deletes unreachable blocks and blocks that are empty.

llvm-svn: 31000
 2006-10-17 17:13:52 +00:00
Evan Cheng 1e3a39cd08 Make sure operand does have size and element type operands. 
llvm-svn: 30999
 2006-10-17 17:06:35 +00:00
Rafael Espindola feb50708eb add the immediate to the Offset in eliminateFrameIndex 
llvm-svn: 30998
 2006-10-17 14:34:02 +00:00
Jim Laskey 7126254a0e Basic support for getGlobalLinkName. 
llvm-svn: 30997
 2006-10-17 13:41:07 +00:00
Rafael Espindola 418c8e69bb add FSTD and FSTS 
llvm-svn: 30996
 2006-10-17 13:36:07 +00:00
Rafael Espindola c31ee94920 add FCPYS and FCPYD 
llvm-svn: 30995
 2006-10-17 13:13:23 +00:00
Jim Laskey 2794184191 Use S_debug for dwarf info. 
llvm-svn: 30994
 2006-10-17 11:30:57 +00:00
Evan Cheng a3e1ad7a61 Proper fix. 
llvm-svn: 30993
 2006-10-17 00:24:49 +00:00
Evan Cheng ed60d16ac7 One more try. 
llvm-svn: 30992
 2006-10-16 23:44:08 +00:00
Reid Spencer 3c514959dd Undo Chris' last patch, it caused a regression. 
llvm-svn: 30991
 2006-10-16 23:08:08 +00:00
Evan Cheng 1367ff084d Unbreak x86-64 build. 
llvm-svn: 30990
 2006-10-16 22:53:28 +00:00
Evan Cheng f3ae00a64a Be careful when looking through a vbit_convert. Optimizing this: 
(vector_shuffle
  (vbitconvert (vbuildvector (copyfromreg v4f32), 1, v4f32), 4, f32),
  (undef, undef, undef, undef), (0, 0, 0, 0), 4, f32)
to the
  vbitconvert
is a very bad idea.

llvm-svn: 30989
 2006-10-16 22:49:37 +00:00
Rafael Espindola afdd47ace4 add fdivs e fdivd 
llvm-svn: 30988
 2006-10-16 21:50:04 +00:00
Rafael Espindola f719c5f43d expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS 
llvm-svn: 30987
 2006-10-16 21:10:32 +00:00
Evan Cheng afb610468b Added a X86CompilationCallback variant which saves XMM argument registers for targets with SSE. 
llvm-svn: 30986
 2006-10-16 21:01:55 +00:00
Evan Cheng a8b4aeace0 Proper fix for rdar://problem/4770604 Thanks to Stuart Hastings! 
llvm-svn: 30985
 2006-10-16 21:00:37 +00:00
Jim Laskey dcb2b83886 Pass AliasAnalysis thru to DAGCombiner. 
llvm-svn: 30984
 2006-10-16 20:52:31 +00:00
Chris Lattner e7d49862a5 add a ReplaceMBBInJumpTables method 
llvm-svn: 30983
 2006-10-16 20:41:42 +00:00
Jim Laskey 9db3a08864 Global name regression. 
llvm-svn: 30982
 2006-10-16 19:38:41 +00:00
Rafael Espindola e341d60f53 define the DFPBinOp class 
llvm-svn: 30981
 2006-10-16 18:39:22 +00:00
Rafael Espindola f63752f94b add the FPBinOp class 
llvm-svn: 30980
 2006-10-16 18:32:36 +00:00
Rafael Espindola b23dc14135 define the Addr1BinOp class 
llvm-svn: 30979
 2006-10-16 18:18:14 +00:00
Rafael Espindola 203922d083 define the IntBinOp class and use it to implement the multiply instructions 
llvm-svn: 30978
 2006-10-16 17:57:20 +00:00
Rafael Espindola c4abf8dc5b fix assembly syntax 
llvm-svn: 30977
 2006-10-16 17:38:12 +00:00
Rafael Espindola 677ee8390d implement LDRB, LDRSB, LDRH and LDRSH 
llvm-svn: 30976
 2006-10-16 17:17:22 +00:00
Rafael Espindola 595dc4c884 implement smull and umull 
llvm-svn: 30975
 2006-10-16 16:33:29 +00:00
Evan Cheng 949bcc94ea Avoid getting into an infinite loop when -disable-x86-shuffle-opti is specified. 
llvm-svn: 30974
 2006-10-16 06:36:00 +00:00
Evan Cheng ff1a712794 SelectScalarSSELoad should call CanBeFoldedBy as well. 
llvm-svn: 30973
 2006-10-16 06:34:55 +00:00
Evan Cheng a74965f15a Passing isel root and use operands to ComplexPattern functions, these should do the usual load folding checks as well. 
llvm-svn: 30972
 2006-10-16 06:33:44 +00:00
Chris Lattner ff20ba3f51 regenerate 
llvm-svn: 30971
 2006-10-15 23:27:25 +00:00
Chris Lattner aad30b7804 Produce a useful error message for Regression/Verifier/2006-10-15-AddrLabel.ll 
llvm-svn: 30970
 2006-10-15 23:26:46 +00:00
Chris Lattner 7fce911edd testcase that causes the asmparser to assert 
llvm-svn: 30969
 2006-10-15 23:26:28 +00:00
Chris Lattner 04e71c6e4d label* is not a valid type, add an assertion. 
llvm-svn: 30968
 2006-10-15 23:21:12 +00:00
Chris Lattner 9a1c7dd27a fix a buggy check that accidentally disabled this xform 
llvm-svn: 30967
 2006-10-15 22:42:15 +00:00
Chris Lattner c1fb4264f5 clarify 
llvm-svn: 30966
 2006-10-15 20:05:59 +00:00
Reid Spencer 775168dac1 Document the VAArg, and vector instruction opcodes. 
llvm-svn: 30965
 2006-10-15 00:11:05 +00:00
Anton Korobeynikov 34e051d537 Align stack size to DWORD boundary 
llvm-svn: 30964
 2006-10-14 20:53:35 +00:00
Rafael Espindola 2b7f635951 expand ISD::BRCOND 
llvm-svn: 30963
 2006-10-14 17:59:54 +00:00
Rafael Espindola 4c1baf1528 fix some fp condition codes 
use non trapping comparison instructions

llvm-svn: 30962
 2006-10-14 13:42:53 +00:00
Jim Laskey 3bf4f3bd60 Tidy up after truncstore changes. 
llvm-svn: 30961
 2006-10-14 12:14:27 +00:00
Evan Cheng 5384fc9676 One cyclic dag a day is good for ya... 
llvm-svn: 30960
 2006-10-14 08:35:02 +00:00
Evan Cheng 47fbeda5ce Debug tweak. 
llvm-svn: 30959
 2006-10-14 08:34:06 +00:00
Evan Cheng b86375cfd0 Corrected load folding check. We need to start from the root of the sub-dag 
being matched and ensure there isn't a non-direct path to the load (i.e. a
path that goes out of the sub-dag.)

llvm-svn: 30958
 2006-10-14 08:33:25 +00:00