43b9ca6f42
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
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llvm-svn: 80404
2009-08-28 23:18:09 +00:00
af29ea6d57
eliminate the last DOUTs from the targets.
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llvm-svn: 79833
2009-08-23 06:49:22 +00:00
a6f074fb3a
remove various std::ostream version of printing methods from
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MachineInstr and MachineOperand. This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)
llvm-svn: 79813
2009-08-23 03:41:05 +00:00
0939595711
Record variable debug info at ISel time directly.
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llvm-svn: 79742
2009-08-22 17:12:53 +00:00
55f1c09e31
Push LLVMContexts through the IntegerType APIs.
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llvm-svn: 78948
2009-08-13 21:58:54 +00:00
f24f9d9cb6
Whitespace cleanup. Remove trailing whitespace.
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llvm-svn: 78666
2009-08-11 15:33:49 +00:00
c28b306423
llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:".
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llvm-svn: 77971
2009-08-03 13:33:33 +00:00
0dd5e1ed39
More migration to raw_ostream, the water has dried up around the iostream hole.
...
- Some clients which used DOUT have moved to DEBUG. We are deprecating the
"magic" DOUT behavior which avoided calling printing functions when the
statement was disabled. In addition to being unnecessary magic, it had the
downside of leaving code in -Asserts builds, and of hiding potentially
unnecessary computations.
llvm-svn: 77019
2009-07-25 00:23:56 +00:00
f297256136
ARM code emitter can't handle Thumb2 instructions yet. So don't even try.
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llvm-svn: 77018
2009-07-25 00:13:11 +00:00
2e1d66847c
Get rid one of the getRegisterNumbering. Also add D16 - D31.
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llvm-svn: 76725
2009-07-22 05:55:18 +00:00
15d54b9504
r76102 added the MachineCodeEmitter::processDebugLoc call and called it from
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the X86 Emitter. This patch extends that to the rest of the targets that can
write to a MachineCodeEmitter: ARM, Alpha, and PPC.
llvm-svn: 76211
2009-07-17 18:49:39 +00:00
fbcc663cbf
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
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This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
llvm-svn: 75640
2009-07-14 16:55:14 +00:00
69208f0f9e
Remove extra \n from LLVM_UNREACHABLE calls.
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llvm-svn: 75416
2009-07-12 07:15:17 +00:00
e3a53c448b
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
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llvm-svn: 75048
2009-07-08 21:03:57 +00:00
fb8d6d5b58
Implement changes from Chris's feedback.
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Finish converting lib/Target.
llvm-svn: 75043
2009-07-08 20:53:28 +00:00
6dd2730024
Start converting to new error handling API.
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cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)
llvm-svn: 75018
2009-07-08 18:01:40 +00:00
b61e3a83ee
Add a todo.
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llvm-svn: 74976
2009-07-08 00:05:05 +00:00
2cff076cfe
Statically encode bit 25 to indicate immediate form of data processing instructions. Patch by Sean Callanan.
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llvm-svn: 74972
2009-07-07 23:40:25 +00:00
40398233b7
Add bfc to armv6t2.
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llvm-svn: 74868
2009-07-06 22:23:46 +00:00
5661ea68e7
Add the Object Code Emitter class. Original patch by Aaron Gray, I did some
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cleanup, removed some #includes and moved Object Code Emitter out-of-line.
llvm-svn: 74813
2009-07-06 05:09:34 +00:00
28d6d87244
Improve Thumb-2 jump table support.
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llvm-svn: 74549
2009-06-30 19:50:22 +00:00
99152f3a2c
Split thumb-related stuff into separate classes.
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Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo
llvm-svn: 74329
2009-06-26 21:28:53 +00:00
1283c6a066
Part 1.
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- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
llvm-svn: 73381
2009-06-15 08:28:29 +00:00
9fd794bebf
Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray
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llvm-svn: 72697
2009-06-01 19:57:37 +00:00
a194c3a69e
First patch in the direction of splitting MachineCodeEmitter in two subclasses:
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JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray
llvm-svn: 72631
2009-05-30 20:51:52 +00:00
0b77319742
Fix MachineCodeEmitter to use uintptr_t instead of intptr_t. This avoids some overflow issues. Patch by Thomas Jablin.
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llvm-svn: 60828
2008-12-10 02:32:19 +00:00
5f23e9fe73
Fix a thinko. MO is getOperand(i-1) so we don't have to adjust e.
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llvm-svn: 59696
2008-11-20 02:25:51 +00:00
59213d64e5
Eliminate a compile time warning.
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llvm-svn: 59678
2008-11-19 23:21:33 +00:00
30f6f8fdad
Fix MOVrx, MOVsrl_flag, and MOVsra_flag encodings.
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llvm-svn: 59314
2008-11-14 20:09:11 +00:00
fabdcce677
Handle the rest of pseudo instructions.
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llvm-svn: 59275
2008-11-13 23:36:57 +00:00
935963de81
Don't forget to emit stubs for function GV's emitted in CONSTPOOL_ENTRY's.
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llvm-svn: 59258
2008-11-13 19:22:28 +00:00
4af89f7e7d
Missed a break statement.
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llvm-svn: 59231
2008-11-13 07:46:59 +00:00
2666f59322
Fix pre- and post-indexed load / store encoding bugs.
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llvm-svn: 59230
2008-11-13 07:34:59 +00:00
45d030a05a
Address mode immediate offset has already been divided by 4.
...
llvm-svn: 59117
2008-11-12 08:21:12 +00:00
052f20d3b1
Fix a VFP binary arithmetic instruction encoding bug.
...
llvm-svn: 59116
2008-11-12 08:14:21 +00:00
2836d91630
Fix address mode 3 immediate offset mode encoding.
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llvm-svn: 59109
2008-11-12 07:34:37 +00:00
af644b50b4
Consolidate formats; fix FCMPED etc. encodings.
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llvm-svn: 59107
2008-11-12 07:18:38 +00:00
4b6c7efbde
Fix VFP conversion instruction encodings.
...
llvm-svn: 59104
2008-11-12 06:41:41 +00:00
a0e2f26320
Fix encoding of single-precision VFP registers.
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llvm-svn: 59102
2008-11-12 02:19:38 +00:00
bfcee5b863
VFP fld / fst immediate field is multiplied by 4.
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llvm-svn: 59100
2008-11-12 01:02:24 +00:00
97ccab888a
Fix FMDRR encoding.
...
llvm-svn: 59088
2008-11-11 22:46:12 +00:00
ad519bbe54
Handle floating point constpool_entry's.
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llvm-svn: 59087
2008-11-11 22:19:31 +00:00
8cbbcb1f2f
Encode VFP load / store instructions.
...
llvm-svn: 59084
2008-11-11 21:48:44 +00:00
38c9a14a88
Encode VFP conversion instructions.
...
llvm-svn: 59074
2008-11-11 19:40:26 +00:00
ac2af2fdb2
Encode VFP arithmetic instructions.
...
llvm-svn: 59016
2008-11-11 02:11:05 +00:00
9f3058f3be
Rename isGVNonLazyPtr to isIndirectSym to reflect how it will be used.
...
llvm-svn: 58949
2008-11-10 01:08:07 +00:00
98161f5f34
Tell ARMJITInfo if codegen relocation is PIC. It changes how function stubs are generated.
...
llvm-svn: 58896
2008-11-08 07:38:22 +00:00
bb373c4637
Fix relocation for calls to external symbols.
...
llvm-svn: 58893
2008-11-08 07:22:33 +00:00
077c8f8832
Skip over two-address use operands.
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llvm-svn: 58883
2008-11-08 01:44:13 +00:00
ffdd91e3b8
Handle ARM machine constantpool entry with non-lazy ptr.
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llvm-svn: 58882
2008-11-08 01:31:27 +00:00
ef4d78ba67
More code clean up.
...
llvm-svn: 58872
2008-11-07 22:57:53 +00:00
8467e2459a
Get PIC jump table working.
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llvm-svn: 58869
2008-11-07 22:30:53 +00:00
7095cd2af2
Jump table JIT support. Work in progress.
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llvm-svn: 58836
2008-11-07 09:06:08 +00:00
98dc53e926
Encode misc arithmetic instructions.
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llvm-svn: 58828
2008-11-07 01:41:35 +00:00
49d665218c
Encode extend instructions; more clean up.
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llvm-svn: 58818
2008-11-06 22:15:19 +00:00
aa03cd3336
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
...
- Consolidate instruction formats.
- Other clean up.
llvm-svn: 58808
2008-11-06 17:48:05 +00:00
47b546d75f
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
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llvm-svn: 58800
2008-11-06 08:47:38 +00:00
b870fd8874
Fix so_imm encoding bug; add support for MOVi2pieces.
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llvm-svn: 58790
2008-11-06 02:25:39 +00:00
2686c8fb34
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
...
llvm-svn: 58789
2008-11-06 01:21:28 +00:00
fd2adbfa28
Encode pic load / store instructions; fix some encoding bugs.
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llvm-svn: 58780
2008-11-05 23:22:34 +00:00
81889d010c
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
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llvm-svn: 58764
2008-11-05 18:35:52 +00:00
4eaff40147
Debug output tweak.
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llvm-svn: 58708
2008-11-04 17:58:53 +00:00
6dd08b6604
Handle ARM machine constantpool entries.
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llvm-svn: 58671
2008-11-04 00:50:32 +00:00
4d0549e3be
Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
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llvm-svn: 58626
2008-11-03 18:38:31 +00:00
20dbb3bcad
Use better data structure for ConstPoolId2AddrMap.
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llvm-svn: 58532
2008-10-31 19:55:13 +00:00
44994e0c77
Actually make debug output understandable.
...
llvm-svn: 58529
2008-10-31 19:15:52 +00:00
467e6e8093
Encode PICADD; some code clean up.
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llvm-svn: 58526
2008-10-31 19:10:44 +00:00
c696ef9b11
I think we got non-machine specific constpool entries covered.
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llvm-svn: 58474
2008-10-30 23:43:36 +00:00
19d64ba8bf
Correct way to handle CONSTPOOL_ENTRY instructions.
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llvm-svn: 58409
2008-10-29 23:55:43 +00:00
ff2b4948ce
Support for constant islands in the ARM JIT.
...
Since the ARM constant pool handling supercedes the standard LLVM constant
pool entirely, the JIT emitter does not allocate space for the constants,
nor initialize the memory. The constant pool is considered part of the
instruction stream.
Likewise, when resolving relocations into the constant pool, a hook into
the target back end is used to resolve from the constant ID# to the
address where the constant is stored.
For now, the support in the ARM emitter is limited to 32-bit integer. Future
patches will expand this to the full range of constants necessary.
llvm-svn: 58338
2008-10-28 18:25:49 +00:00
c084e84028
Encode the conditional execution predicate when JITing.
...
llvm-svn: 57258
2008-10-07 19:05:35 +00:00
2fb5c3938b
Clarify naming and correct conditional so that CMP and CMN instructions get the Rn operand encoded properly
...
llvm-svn: 57252
2008-10-07 17:42:09 +00:00
332ad5e016
Indexing off by one resulted in errant encoding of source register for
...
reg->reg moves.
llvm-svn: 57011
2008-10-03 15:53:56 +00:00
af929abc01
NeedStub/DoesntNeedStub logic was reversed, leading to not using a stub
...
for global relocations that do need them (libc calls, for example).
llvm-svn: 57010
2008-10-03 15:52:42 +00:00
0d1e9a8e04
Switch the MachineOperand accessors back to the short names like
...
isReg, etc., from isRegister, etc.
llvm-svn: 57006
2008-10-03 15:45:36 +00:00
3dc0a3bce3
Fix typo s/ther/there/
...
llvm-svn: 56924
2008-10-01 18:16:49 +00:00
933b392f65
Duh. Default to ARMCC::AL (always).
...
llvm-svn: 56301
2008-09-18 07:28:19 +00:00
7848cfcd77
Fix addrmode1 instruction encodings; fix bx_ret encoding.
...
llvm-svn: 56277
2008-09-17 07:53:38 +00:00
a5804effed
Fix random abort.
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llvm-svn: 56184
2008-09-13 01:55:59 +00:00
380482ac46
Typo.
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llvm-svn: 56182
2008-09-13 01:44:01 +00:00
ba28161103
Rely on instruction format to determine so_reg operand for now.
...
llvm-svn: 56181
2008-09-13 01:38:29 +00:00
12134701ec
Revert 56176. All those instruction formats are still needed.
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llvm-svn: 56180
2008-09-13 01:35:33 +00:00
db6571a2c7
Accidentially flipped the condition.
...
llvm-svn: 56179
2008-09-13 01:29:57 +00:00
25a39094f8
Add debug dumps.
...
llvm-svn: 56178
2008-09-13 01:15:21 +00:00
c5c74f36fd
Eliminate unnecessary instruction formats.
...
llvm-svn: 56176
2008-09-12 23:15:39 +00:00
d1424c4eca
Addrmode 1 S bit can be dynamically set. Look for CPSR def.
...
llvm-svn: 56172
2008-09-12 22:45:55 +00:00
33fa89c6fb
Rewrite address mode 1 code emission routines.
...
llvm-svn: 56171
2008-09-12 22:01:15 +00:00
a79db30d28
Tidy up several unbeseeming casts from pointer to intptr_t.
...
llvm-svn: 55779
2008-09-04 17:05:41 +00:00
3be5b728b1
Revamp ARM JIT.
...
llvm-svn: 55624
2008-09-02 06:52:38 +00:00
40d67c59d5
Remove bunch of gcc 4.3-related warnings from Target
...
llvm-svn: 47369
2008-02-20 11:22:39 +00:00
3a4be0fdef
Rename MRegisterInfo to TargetRegisterInfo.
...
llvm-svn: 46930
2008-02-10 18:45:23 +00:00
03ad885039
rename TargetInstrDescriptor -> TargetInstrDesc.
...
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
llvm-svn: 45695
2008-01-07 07:27:27 +00:00
a98c679de0
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
...
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
llvm-svn: 45674
2008-01-07 01:56:04 +00:00
a5bb370aa4
Add new shorter predicates for testing machine operands for various types:
...
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
llvm-svn: 45464
2007-12-30 23:10:15 +00:00
5c4637816e
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
...
llvm-svn: 45453
2007-12-30 20:49:49 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
...
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
1457b2b3b1
Comments added. It now generates V5TE multiply instructions. However, it is still necessary to model PUWLSH bits more clearly.
...
llvm-svn: 41627
2007-08-30 23:29:26 +00:00
f7c6effc44
Initial JIT support for ARM by Raul Fernandes Herbster.
...
llvm-svn: 40887
2007-08-07 01:37:15 +00:00
396156e00b
no email addrs in file headers
...
llvm-svn: 39962
2007-07-17 05:56:43 +00:00
9546a5c7de
Initial ARM JIT support by Raul Fernandes Herbster.
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llvm-svn: 37926
2007-07-05 21:15:40 +00:00
Evan Cheng