94629eb861
[Sparc] Use correct instruction pattern for CMPri.
...
llvm-svn: 191180
2013-09-22 18:54:54 +00:00
51270837aa
[Sparc] Make SPARC instructions' encoding well defined such that TableGen can automatically generate code emitter.
...
llvm-svn: 191168
2013-09-22 09:54:42 +00:00
709d154d69
[Sparc] Clean up MOVcc instructions so that TableGen can encode them correctly. No functionality change intended.
...
llvm-svn: 191167
2013-09-22 09:18:26 +00:00
2fb440fbad
[Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended.
...
llvm-svn: 191166
2013-09-22 08:51:55 +00:00
31d093c705
ISelDAG: spot chain cycles involving MachineNodes
...
Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.
Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.
This should fix PR15840.
llvm-svn: 191165
2013-09-22 08:21:56 +00:00
cb1dca602c
[Sparc] Add support for TLS in sparc.
...
llvm-svn: 191164
2013-09-22 06:48:52 +00:00
7e7eb8ce69
[SPARC] Make functions with GLOBAL_OFFSET_TABLE access as non-leaf functions.
...
llvm-svn: 191160
2013-09-22 01:40:24 +00:00
e9ef51222b
[Sparc] Emit .register directive to declare the use of global registers %g2, %g4, %g6 and %g7.
...
llvm-svn: 191158
2013-09-22 00:42:30 +00:00
829aec5900
[Sparc] Fix lowering FABS on fp128 (long double) on pre-v9 targets.
...
llvm-svn: 191154
2013-09-21 23:51:08 +00:00
55ecb10e99
[Sparc] Correctly handle call to functions with ReturnsTwice attribute.
...
In sparc, setjmp stores only the registers %fp, %sp, %i7 and %o7. longjmp restores
the stack, and the callee-saved registers (all local/in registers: %i0-%i7, %l0-%l7)
using the stored %fp and register windows. However, this does not guarantee that the longjmp
will restore the registers, as they were when the setjmp was called. This is because these
registers may be clobbered after returning from setjmp, but before calling longjmp.
This patch prevents the registers %i0-%i5, %l0-l7 to live across the setjmp call using the register mask.
llvm-svn: 190033
2013-09-05 05:32:16 +00:00
b803cec00e
[Sparc] Fix an assertion failure while lowering fcmp on long double.
...
This assertion is triggered because an integer constant is created with wrong
type.
llvm-svn: 189948
2013-09-04 15:15:20 +00:00
59039dc1bf
[Sparc] Add support for soft long double (fp128).
...
llvm-svn: 189780
2013-09-03 04:11:59 +00:00
01cb19f93c
[Sparc] Implement spill and load for long double(f128) registers.
...
llvm-svn: 189768
2013-09-02 18:32:45 +00:00
35e0c382d5
[Sparc] Add long double (f128) instructions to sparc backend.
...
llvm-svn: 189198
2013-08-25 18:30:06 +00:00
12d8089b8e
[Sparc] Added V9's extra floating point registers and their aliases.
...
llvm-svn: 189195
2013-08-25 17:03:02 +00:00
0c00704f27
Use register masks on SPARC call instructions.
...
llvm-svn: 189085
2013-08-23 02:33:47 +00:00
a8960a1f7c
Add an OtherPreserved field to the CalleeSaved TableGen class.
...
This field specifies registers that are preserved across function calls,
but that should not be included in the generates SaveList array.
This can be used ot generate regmasks for architectures that save
registers through other means, like SPARC's register windows.
llvm-svn: 189084
2013-08-23 02:25:47 +00:00
f625773bca
[Sparc] Use HWEncoding instead of unused Num field in Sparc register definitions. Also, correct the definitions of RETL and RET instructions.
...
llvm-svn: 188738
2013-08-20 01:26:14 +00:00
b50bf5a0e3
[Sparc] Enable xword directive in sparcv9.
...
llvm-svn: 188141
2013-08-10 20:13:20 +00:00
aaf66c7357
Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for each corresponding CodeGen.
...
Without explicit dependencies, both per-file action and in-CommonTableGen action could run in parallel.
It races to emit *.inc files simultaneously.
llvm-svn: 187780
2013-08-06 06:38:37 +00:00
fee76fac2f
[Sparc] Rewrite MBB's live-in registers for leaf functions. Also, add
...
register i7 as a live-in if current function's return address is taken.
This revision fixes PR16269.
llvm-svn: 187433
2013-07-30 19:53:10 +00:00
fdcc498a25
[Sparc] Use call's debugloc for the unimp instruction.
...
llvm-svn: 187402
2013-07-30 02:26:29 +00:00
b94011fd28
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
...
llvm-svn: 186274
2013-07-14 04:42:23 +00:00
6f0b450530
[Sparc]: Add memory operands for the frame references in the storeRegToStackSlot
...
and loadRegFromStackSlot.
llvm-svn: 184935
2013-06-26 12:40:16 +00:00
295bd43adb
The getRegForInlineAsmConstraint function should only accept MVT value types.
...
llvm-svn: 184642
2013-06-22 18:37:38 +00:00
a3cd350249
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
...
llvm-svn: 184360
2013-06-19 21:36:55 +00:00
b735b4d6db
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
...
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.
llvm-svn: 184067
2013-06-16 20:34:27 +00:00
7dae9ce021
[Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc backend.
...
llvm-svn: 183613
2013-06-08 15:32:59 +00:00
fdc9d0a991
Remember the anyext patterns.
...
llvm-svn: 183589
2013-06-07 22:59:29 +00:00
9f812b97ba
Add missing zextloadi1 to i64 patterns. PR16721.
...
llvm-svn: 183587
2013-06-07 22:55:05 +00:00
6235c06ff8
Don't cache the instruction and register info from the TargetMachine, because
...
the internals of TargetMachine could change.
No functionality change intended.
llvm-svn: 183565
2013-06-07 20:35:25 +00:00
158d8069ad
Fix a typo in asm string of BP* family of instructions. With this fix
...
I am able to compile/assemble/link/run /bin/echo from FreeBSD.
llvm-svn: 183537
2013-06-07 17:46:57 +00:00
dc82ac0dcc
[Sparc]: Use cmp instruction instead of subcc to compare integers.
...
llvm-svn: 183463
2013-06-07 00:03:36 +00:00
f77190855d
Cache the TargetLowering info object as a pointer.
...
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.
llvm-svn: 183361
2013-06-06 00:43:09 +00:00
a54533ed78
Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,
...
llvm-svn: 183243
2013-06-04 18:33:25 +00:00
f80d72f149
Sparc: Add support for indirect branch and blockaddress in Sparc backend.
...
llvm-svn: 183094
2013-06-03 05:58:33 +00:00
774fe2e29a
Sparc: When storing 0, use %g0 directly in the store instruction instead of
...
using two instructions (sethi and store).
llvm-svn: 183090
2013-06-03 00:21:54 +00:00
0bbe1b210e
Sparc: Combine add/or/sethi instruction with restore if possible.
...
llvm-svn: 183088
2013-06-02 21:48:17 +00:00
3e8c7d98be
Sparc: Perform leaf procedure optimization by default
...
llvm-svn: 183083
2013-06-02 02:24:27 +00:00
28e2cd0e7e
Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics as non-leaf functions.
...
llvm-svn: 183079
2013-06-01 20:42:48 +00:00
3521dcdcc4
[Sparc] Generate correct code for leaf functions with stack objects
...
llvm-svn: 183067
2013-06-01 04:51:18 +00:00
b1a4d9da3b
Make SubRegIndex size mandatory, following r183020.
...
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.
llvm-svn: 183061
2013-05-31 23:45:26 +00:00
ad6d08ac6f
Order CALLSEQ_START and CALLSEQ_END nodes.
...
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
llvm-svn: 182885
2013-05-29 22:03:55 +00:00
dbd3bbe126
SparcFrameLowering.cpp: Mark verifyLeafProcRegUse() as UNUSED. [-Wunused-function]
...
llvm-svn: 182850
2013-05-29 12:10:42 +00:00
ca0fe2f57e
[Sparc] Add support for leaf functions in sparc backend.
...
llvm-svn: 182822
2013-05-29 04:46:31 +00:00
ef9de2a739
Track IR ordering of SelectionDAG nodes 2/4.
...
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
llvm-svn: 182703
2013-05-25 02:42:55 +00:00
f927800325
Also expand 64-bit bitcasts.
...
llvm-svn: 182229
2013-05-20 01:01:43 +00:00
c7bc5fbc5c
Implement spill and fill of I64Regs.
...
llvm-svn: 182228
2013-05-20 00:53:25 +00:00
751e9b8407
Mark i64 SETCC as expand so it is turned into a SELECT_CC.
...
llvm-svn: 182227
2013-05-20 00:28:36 +00:00
86c5469d26
Don't use %g0 to materialize 0 directly.
...
The wired physreg doesn't work on tied operands like on MOVXCC.
Add a README note to fix this later.
llvm-svn: 182225
2013-05-19 21:47:13 +00:00
Venkatraman Govindaraju