Commit Graph

292498 Commits

Author SHA1 Message Date
Reid Kleckner 5c25346912 Avoid including intrin.h from MathExtras.h
This is repeatably worth 0.3s compile time on MathExtras.cpp. This is a
very popular header, and it basically pulls all Intel intrinsics into
every LLVM TU. Let's not do that.

llvm-svn: 335406
2018-06-23 01:19:49 +00:00
Fangrui Song 4ef42a83f9 [ELF] Change isSectionData to exclude SHF_EXECINSTR
Summary:
This affects what sections are displayed as "DATA" in llvm-objdump.
The other user llvm-size is unaffected.

Before, a "TEXT" section is also "DATA", which seems weird.
The sh_flags condition matches that of bfd's SEC_DATA but the sh_type
condition uses (== SHF_PROGBITS) instead of bfd's (!= SHT_NOBITS).
bfd's SEC_DATA is not appealing as so many sections will be shown as DATA.

Reviewers: jyknight, Bigcheese

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D48472

llvm-svn: 335405
2018-06-23 00:15:33 +00:00
Fangrui Song e737e75491 [ELF] Change llvm-objdump output for D48472: TEXT DATA -> TEXT
Reviewers: jyknight, Bigcheese, espindola

Subscribers: emaste, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D48473

llvm-svn: 335404
2018-06-23 00:15:23 +00:00
Craig Topper abdbb2c67a [X86][AsmParser] Rework that allows (%dx) to be used in place of %dx with in/out instructions.
Previously, to support (%dx) we left a wide open hole in our 16-bit memory address checking. This let this address value be used with any instruction without error in the parser. It would later fail in the encoder with an assertion failure on debug builds and who knows what on release builds.

This patch passes the mnemonic down to the memory operand parsing function so we can allow the (%dx) form only on specific instructions.

llvm-svn: 335403
2018-06-23 00:03:20 +00:00
Reid Kleckner 330f65b3e8 [RuntimeDyld] Implement the ELF PIC large code model relocations
Prerequisite for https://reviews.llvm.org/D47211 which improves our ELF
large PIC codegen.

llvm-svn: 335402
2018-06-22 23:53:22 +00:00
Greg Clayton ef115de629 Update cmdtemplate.py to use best pratices.
Fixes include:
- fix all lint errors
- add code that will automatically register and LLDB command classes by detecting the classes and any classes that have a "register_lldb_command" function
  - automatically fill in the correct module name when registering commands
  - automatically fill in the class name when registering command

llvm-svn: 335401
2018-06-22 23:34:24 +00:00
Eli Friedman 203eaaf5ba [LoopReroll] Rewrite induction variable rewriting.
This gets rid of a bunch of weird special cases; instead, just use SCEV
rewriting for everything.  In addition to being simpler, this fixes a
bug where we would use the wrong stride in certain edge cases.

The one bit I'm not quite sure about is the trip count handling,
specifically the FIXME about overflow.  In general, I think we need to
widen the exit condition, but that's probably not profitable if the new
type isn't legal, so we probably need a check somewhere.  That said, I
don't think I'm making the existing problem any worse.

As a followup to this, a bunch of IV-related code in root-finding could
be cleaned up; with SCEV-based rewriting, there isn't any reason to
assume a loop will have exactly one or two PHI nodes.

Differential Revision: https://reviews.llvm.org/D45191

llvm-svn: 335400
2018-06-22 22:58:55 +00:00
George Burgess IV 2cbf9730b0 [MSSA] Remove incorrect comment + `auto`ify dyn_cast results; NFC
llvm-svn: 335399
2018-06-22 22:34:07 +00:00
Craig Topper 10e2f73793 [X86][AsmParser] Keep track of whether an explicit scale was specified while parsing an address in Intel syntax. Use it for improved error checking.
This allows us to check these:
-16-bit addressing doesn't support scale so we should error if we find one there.
-Multiplying ESP/RSP by a scale even if the scale is 1 should be an error because ESP/RSP can't be an index.

llvm-svn: 335398
2018-06-22 22:28:39 +00:00
Fangrui Song 1e2d5cb06c [llvm-size] Make global variables static
llvm-svn: 335397
2018-06-22 22:20:10 +00:00
Sanjay Patel 80b85a46db [x86] add more tests for bit hacking opportunities with setcc; NFC
Missed cases where the input and output are the same size in rL335391.

llvm-svn: 335396
2018-06-22 22:07:26 +00:00
Sanjay Patel 0fe8ea568b [PowerPC] add more tests for bit hacking opportunities with setcc; NFC
Missed cases where the input and output are the same size in rL335390.

llvm-svn: 335395
2018-06-22 22:06:33 +00:00
Craig Topper 1d707539e4 [X86][AsmParser] In Intel syntax make sure we support ESP/RSP being the second register in memory expressions like [EAX+ESP].
By default, the second register gets assigned to the index register slot. But ESP can't be an index register so we need to swap it with the other register.

There's still a slight bug that we allow [EAX+ESP*1]. The existence of the multiply even though its with 1 should force ESP to the index register and trigger an error, but it doesn't currently.

llvm-svn: 335394
2018-06-22 21:57:24 +00:00
JF Bastien ec7d7f312e [Sema] -Wformat-pedantic only for NSInteger/NSUInteger %zu/%zi on Darwin
Summary:
Pick D42933 back up, and make NSInteger/NSUInteger with %zu/%zi specifiers on Darwin warn only in pedantic mode. The default -Wformat recently started warning for the following code because of the added support for analysis for the '%zi' specifier.

     NSInteger i = NSIntegerMax;
     NSLog(@"max NSInteger = %zi", i);

The problem is that on armv7 %zi is 'long', and NSInteger is typedefed to 'int' in Foundation. We should avoid this warning as it's inconvenient to our users: it's target specific (happens only on armv7 and not arm64), and breaks their existing code. We should also silence the warning for the '%zu' specifier to ensure consistency. This is acceptable because Darwin guarantees that, despite the unfortunate choice of typedef, sizeof(size_t) == sizeof(NS[U]Integer), the warning is therefore noisy for pedantic reasons. Once this is in I'll update public documentation.

Related discussion on cfe-dev:
http://lists.llvm.org/pipermail/cfe-dev/2018-May/058050.html

<rdar://36874921&40501559>

Reviewers: ahatanak, vsapsai, alexshap, aaron.ballman, javed.absar, jfb, rjmccall

Subscribers: kristof.beyls, aheejin, cfe-commits

Differential Revision: https://reviews.llvm.org/D47290

llvm-svn: 335393
2018-06-22 21:54:40 +00:00
Matt Davis eb7488e799 [llvm-mca] Remove unnecessary include and forward decl in RCU. NFC.
The DispatchUnit is no longer a dependency of RCU, so this patch removes a
stale include and forward decl.  This patch also cleans up some comments.

llvm-svn: 335392
2018-06-22 21:35:26 +00:00
Sanjay Patel 705cde3ac8 [x86] add tests for bit hacking opportunities with setcc; NFC
We likely gave up on folding some select-of-constants patterns in 
IR with rL331486, and we need to recover those in the DAG.

The tests without select are based on our current DAGCombiner 
optimizations for select-of-constants.

llvm-svn: 335391
2018-06-22 21:16:54 +00:00
Sanjay Patel 6e505e4388 [PowerPC] add tests for bit hacking opportunities with setcc; NFC
We likely gave up on folding some select-of-constants patterns in 
IR with rL331486, and we need to recover those in the DAG.

The tests without select are based on our current DAGCombiner 
optimizations for select-of-constants.

llvm-svn: 335390
2018-06-22 21:16:29 +00:00
Craig Topper a55cc4a2e9 [X86] Add test cases showing missed select simplifcation for MCU when icmp is in a slightly different form.
These test cases show that the "(select (and (x , 0x1) == 0), y, (z ^ y) ) -> (-(and (x , 0x1)) & z ) ^ y" doesn't work if the select condition is changed to (and (x, 0x1) != 1)

llvm-svn: 335389
2018-06-22 21:09:31 +00:00
Aditya Nandakumar e2a7f31064 [GISel]: Add G_ADDRSPACE_CAST Opcode
Added IRTranslator support for addrspacecast.

https://reviews.llvm.org/D48469

reviewed by: volkan

llvm-svn: 335388
2018-06-22 20:58:51 +00:00
Fangrui Song f2b547f85f [gdb] Use Latin-1 to decode StringRef
llvm-svn: 335387
2018-06-22 20:29:42 +00:00
Adrian Prantl 56a196c020 Mark this test as no debuginfo
llvm-svn: 335386
2018-06-22 20:26:53 +00:00
Tobias Edler von Koch 7609cb83e6 Re-land "[LTO] Enable module summary emission by default for regular LTO"
Since we are now producing a summary also for regular LTO builds, we
need to run the NameAnonGlobals pass in those cases as well (the
summary cannot handle anonymous globals).

See https://reviews.llvm.org/D34156 for details on the original change.

This reverts commit 6c9ee4a4a438a8059aacc809b2dd57128fccd6b3.

llvm-svn: 335385
2018-06-22 20:23:21 +00:00
Craig Topper 9bc2c059c3 [X86] Don't accept (%si,%bp) 16-bit address expressions.
The second register is the index register and should only be %si or %di if used with a base register. And in that case the base register should be %bp or %bx.

This makes us compatible with gas.

We do still need to support both orders with Intel syntax which uses [bp+si] and [si+bp]

llvm-svn: 335384
2018-06-22 20:20:38 +00:00
Vedant Kumar c835306ac5 [ubsan] Fix __ubsan_on_report interface definition
Speculative fix for the interface definition of __ubsan_on_report for
the Windows bots:

  http://lab.llvm.org:8011/builders/sanitizer-windows/builds/30528
  lib\ubsan\ubsan_interface.inc(55): error C2065: '__ubsan_on_report':
  undeclared identifier

INTERCEPT_SANITIZER_WEAK_FUNCTION was the wrong macro to use to begin
with because __ubsan_on_report isn't weak. Reading through that macro,
it's still not clear to me why there is an undefined reference, though,
because it appears to define a dummy __ubsan_on_report shim.

llvm-svn: 335383
2018-06-22 20:15:33 +00:00
Benjamin Kramer 9508af351a Reinstate quotes around the path to python that I accidentaly removed in r335330
This broke users with spaces in the path, like C:\Program Files\Python

llvm-svn: 335382
2018-06-22 20:03:32 +00:00
Richard Smith 69bc9aa22f Restore pre-r335182 behavior for naming inherited constructors as
members of dependent contexts.

This permits cases where the names before and after the '::' in a
dependent inherited constructor using-declaration do not match, but
where we can nonetheless tell when parsing the template that a
constructor is being named. Under (open) core language DR 2070, such
cases will probably be ill-formed, but r335182 does not quite give
that result and didn't intend to change this, so restore the old
behavior for now.

llvm-svn: 335381
2018-06-22 19:50:19 +00:00
Sam Clegg 5421b37893 Fix BUILD_SHARED_LIBS=1 build of libclangHandleLLVM
Differential Revision: https://reviews.llvm.org/D48503

llvm-svn: 335380
2018-06-22 19:44:48 +00:00
Craig Topper c26c62e0e5 [X86][AsmParser] Allow (%bp,%si) and (%bp,%di) to be encoded without using a zero displacement.
(%bp) can't be encoded without a displacement. The encoding is instead used for displacement alone. So a 1 byte displacement of 0 must be used. But if there is an index register we can encode without a displacement.

llvm-svn: 335379
2018-06-22 19:42:21 +00:00
Konstantin Zhuravlyov dd6b05c34c AMDHSA: Put old assembler docs back
Until we switch to code object v3 by default.
Follow up for https://reviews.llvm.org/D47736.

Differential Revision: https://reviews.llvm.org/D48497

llvm-svn: 335378
2018-06-22 19:23:18 +00:00
Alexey Bataev 12c62908b5 [OPENMP, NVPTX] Fix reduction of the big data types/structures.
If the shuffle is required for the reduced structures/big data type,
current code may cause compiler crash because of the loading of the
aggregate values. Patch fixes this problem.

llvm-svn: 335377
2018-06-22 19:10:38 +00:00
Simon Pilgrim 938dbe664b [X86][SSE] Add sdiv by (nonuniform) minus one tests (PR37119)
Test cases from D45806

llvm-svn: 335376
2018-06-22 18:31:57 +00:00
Bruno Cardoso Lopes a9c51fe089 Re-apply: Warning for framework headers using double quote includes
Introduce -Wquoted-include-in-framework-header, which should fire a warning
whenever a quote include appears in a framework header and suggest a fix-it.
For instance, for header A.h added in the tests, this is how the warning looks
like:

./A.framework/Headers/A.h:2:10: warning: double-quoted include "A0.h" in framework header, expected angle-bracketed instead [-Wquoted-include-in-framework-header]
#include "A0.h"
         ^~~~~~
         <A/A0.h>
./A.framework/Headers/A.h:3:10: warning: double-quoted include "B.h" in framework header, expected angle-bracketed instead [-Wquoted-include-in-framework-header]
#include "B.h"
         ^~~~~
         <B.h>

This helps users to prevent frameworks from using local headers when in fact
they should be targetting system level ones.

The warning is off by default.

Differential Revision: https://reviews.llvm.org/D47157

rdar://problem/37077034

llvm-svn: 335375
2018-06-22 18:05:17 +00:00
Emmett Neyman e5f4a9ff76 Implemented proto to LLVM conversion and LLVM fuzz target
Differential Revision: https://reviews.llvm.org/D48106

llvm-svn: 335374
2018-06-22 18:05:00 +00:00
Craig Topper cd18bb523c [X86][AsmParser] Check for invalid 16-bit base register in Intel syntax.
llvm-svn: 335373
2018-06-22 17:50:40 +00:00
Erich Keane 87cfcfd009 [NFC] Fix AttributeList allocated_size for ParsedType.
This if/elseif structure seems to be missing this case.
Previously, this would report a size of 1 pointer too small. 
This didn't really change anything besides failing to reclaim
a very small amount of memory.

llvm-svn: 335372
2018-06-22 17:34:44 +00:00
Vedant Kumar 059d20360a [ubsan] Add support for reporting diagnostics to a monitor process
Add support to the ubsan runtime for reporting diagnostics to a monitor
process (e.g a debugger).

The Xcode IDE uses this by setting a breakpoint on __ubsan_on_report and
collecting diagnostic information via __ubsan_get_current_report_data,
which it then surfaces to users in the editor UI.

Testing for this functionality already exists in upstream lldb, here:
lldb/packages/Python/lldbsuite/test/functionalities/ubsan

Apart from that, this is `ninja check-{a,ub}san` clean.

Differential Revision: https://reviews.llvm.org/D48446

llvm-svn: 335371
2018-06-22 17:21:17 +00:00
Craig Topper 22d1db122a [X86] Don't allow ESP/RSP to be used as an index register in assembly.
Fixes PR37892

llvm-svn: 335370
2018-06-22 17:15:58 +00:00
Alina Sbirlea bee50036d3 [LoopUnswitch]Fix comparison for DomTree updates.
Summary:
In LoopUnswitch when replacing a branch Parent -> Succ with a conditional
branch Parent -> True & Parent->False, the DomTree updates should insert an edge for
each of True/False if True/False are different than Succ, and delete Parent->Succ edge
if both are different. The comparison with Succ appears to be incorect,
it's comparing with Parent instead.
There is no test failing either before or after this change, but it seems to me this is
the right way to do the update.

Reviewers: chandlerc, kuhar

Subscribers: sanjoy, jlebar, llvm-commits

Differential Revision: https://reviews.llvm.org/D48457

llvm-svn: 335369
2018-06-22 17:14:35 +00:00
Andrea Di Biagio 1fa58109f9 [llvm-mca] Remove redundant call. NFC
llvm-svn: 335368
2018-06-22 17:03:40 +00:00
Easwaran Raman f997233890 [X86] Add a test to show missed opportunity to generate vfnmadd
llvm-svn: 335367
2018-06-22 17:01:13 +00:00
Steven Wu b3684db431 Add const qualifier on FieldChainInfoComparator::operator()
libcxx has user defined warning to check for non const call operator.
Silence the warning by adding the const on operator().

llvm-svn: 335366
2018-06-22 16:51:17 +00:00
Krzysztof Parzyszek 358a916aa8 Initialize LiveRegs once in BranchFolder::mergeCommonTails
llvm-svn: 335365
2018-06-22 16:38:38 +00:00
Simon Pilgrim 9d3ef8ee2b [SLPVectorizer] Support alternate opcodes in tryToVectorizeList
Enable tryToVectorizeList to support InstructionsState alternate opcode patterns at a root (build vector etc.) as well as further down the vectorization tree.

NOTE: This patch reduces some of the debug reporting if there are opcode mismatches - I can try to add it back if it proves a problem. But it could get rather messy trying to provide equivalent verbose debug strings via getSameOpcode etc.

Differential Revision: https://reviews.llvm.org/D48488

llvm-svn: 335364
2018-06-22 16:37:34 +00:00
Andrea Di Biagio 21f0fdb219 [llvm-mca] Set the operand ID for implicit register reads/writes. NFC
Also, move the definition of InstRef at the end of Instruction.h to avoid a
forward declaration.

llvm-svn: 335363
2018-06-22 16:37:05 +00:00
Anastasia Stulova 7f785bb458 [OpenCL] Fixed parsing of address spaces for C++.
Added address space tokens to C++ parsing code to be able
to parse declarations that start from an address space keyword.

llvm-svn: 335362
2018-06-22 16:20:21 +00:00
Matt Davis 43de6db2f4 [llvm-mca] Introduce a sequential container of Stages
Summary:
Remove explicit stages and introduce a list of stages.

A pipeline should be composed of an arbitrary list of stages, and not any
 predefined list of stages in the Backend.  The Backend should not know of any
 particular stage, rather it should only be concerned that it has a list of
 stages, and that those stages will fulfill the contract of what it means to be
 a Stage (namely pre/post/execute a given instruction).

For now, we leave the original set of stages defined in the Backend ctor;
however, I imagine these will be moved out at a later time.

This patch makes an adjustment to the semantics of Stage::isReady.
Specifically, what the Backend really needs to know is if a Stage has
unfinished work.  With that said, it is more appropriately renamed
Stage::hasWorkToComplete().  This change will clean up the check in
Backend::run(), allowing us to query each stage to see if there is unfinished
work, regardless of what subclass a stage might be.  I feel that this change
simplifies the semantics too, but that's a subjective statement.

Given how RetireStage and ExecuteStage handle data in their preExecute(), I've
had to change the order of Retire and Execute in our stage list.  Retire must
complete any of its preExecute actions before ExecuteStage's preExecute can
take control.  This is mainly because both stages utilize the RCU.  In the
meantime, I want to see if I can adjust that or remove that coupling.

Reviewers: andreadb, RKSimon, courbet

Reviewed By: andreadb

Subscribers: tschuett, gbedwell, llvm-commits

Differential Revision: https://reviews.llvm.org/D46907

llvm-svn: 335361
2018-06-22 16:17:26 +00:00
Sam McCall a68951e37e [clangd] More precise representation of symbol names/labels in the index.
Summary:
Previously, the strings matched LSP completion pretty closely.
The completion label was a single string, for instance. This made
implementing completion itself easy but makes it hard to use the names
in other way, e.g. pretty-printed name in synthesized
documentation/hover.

It also limits our introspection into completion items, which can only
be as precise as the indexed symbols. This change is a prerequisite to
improvements to overload bundling which need to inspect e.g. signature
structure.

Reviewers: ioeric

Subscribers: ilya-biryukov, MaskRay, jkorous, cfe-commits

Differential Revision: https://reviews.llvm.org/D48475

llvm-svn: 335360
2018-06-22 16:11:35 +00:00
Simon Pilgrim 213cb1b82d [SLPVectorizer] reorderAltShuffleOperands should just take InstructionsState. NFCI.
All calls were extracting the InstructionsState Opcode/AltOpcode values so we might as well pass it directly

llvm-svn: 335359
2018-06-22 16:10:26 +00:00
Anastasia Stulova bf549bf402 [Sema] Updated note for address spaces to print the type.
This allows to reuse the same diagnostic for OpenCL or CUDA.

llvm-svn: 335358
2018-06-22 15:45:08 +00:00
George Rimar 0cde82ade5 [ELF] - ICF: test we do not merge sections which relocations differs only in addend.
This is to test the following `return false` line which
was uncovered by our tests earlier:

https://github.com/llvm-mirror/lld/blob/master/ELF/ICF.cpp#L255

llvm-svn: 335357
2018-06-22 15:21:38 +00:00