0d8b0cf3b8
Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.
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llvm-svn: 76520
2009-07-21 00:31:12 +00:00
a2b8c3f98f
Forgot this test earlier.
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llvm-svn: 76485
2009-07-20 21:46:42 +00:00
55452c2bea
fix an arm codegen bug (the same as PR4482 on ppc) where available_externally
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symbols were not getting stubs. While I'm at it, add a big testcase for
stub generation to make sure I don't break anything.
llvm-svn: 75737
2009-07-15 04:12:33 +00:00
223ac25930
Remove a bogus assertion.
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llvm-svn: 75206
2009-07-10 00:23:48 +00:00
9ce44e2521
Handle 'a' modifier on inline assembly operands.
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This is part of the fix for pr4521.
llvm-svn: 75201
2009-07-09 23:54:51 +00:00
dab7b06de9
Improved tracking of value number kills. VN kills are now represented
...
as an (index,bool) pair. The bool flag records whether the kill is a
PHI kill or not. This code will be used to enable splitting of live
intervals containing PHI-kills.
A slight change to live interval weights introduced an extra spill
into lsr-code-insertion (outside the critical sections). The test
condition has been updated to reflect this.
llvm-svn: 75097
2009-07-09 03:57:02 +00:00
1d298fd75b
Implement NEON vst1 instruction.
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llvm-svn: 75037
2009-07-08 20:32:02 +00:00
f731a2df6b
Implement NEON vld1 instructions.
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llvm-svn: 75019
2009-07-08 18:11:30 +00:00
dc84b31d94
Change these tests to use [fi]cmp+sext instead of v[fi]cmp. No
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functionality change.
llvm-svn: 74979
2009-07-08 00:46:57 +00:00
40398233b7
Add bfc to armv6t2.
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llvm-svn: 74868
2009-07-06 22:23:46 +00:00
e63b0e6f79
Added ARM::mls for armv6t2.
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llvm-svn: 74866
2009-07-06 22:05:45 +00:00
0e8bde5910
Add thumb2 sign / zero extend with rotate instructions.
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llvm-svn: 74755
2009-07-03 01:43:10 +00:00
04f72fc955
CommuteChangesDestination() should check if to-be-commuted instruction defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp).
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llvm-svn: 74602
2009-07-01 08:29:08 +00:00
2a5efe14a7
Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def.
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Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.
llvm-svn: 74601
2009-07-01 08:19:36 +00:00
d379e896ff
Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
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llvm-svn: 74580
2009-07-01 01:59:31 +00:00
dcf1f59305
Temporarily restore the scavenger implicit_def checking code. MachineOperand isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.).
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llvm-svn: 74519
2009-06-30 09:19:42 +00:00
0dc101b897
Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
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The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.
This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.
llvm-svn: 74518
2009-06-30 08:49:04 +00:00
b23b50d54d
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
34f7ede9e7
ORN and BIC tests.
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llvm-svn: 74289
2009-06-26 16:20:06 +00:00
7779156b39
Fix tests: Count -> count.
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llvm-svn: 74282
2009-06-26 07:05:57 +00:00
34c8c7414f
Fix a CodeGenDAGPatterns bug. Check if top level predicates match when it's looking for duplicates.
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llvm-svn: 74276
2009-06-26 05:59:16 +00:00
97727a61f9
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
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llvm-svn: 74228
2009-06-25 23:34:10 +00:00
c7ea8df67e
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
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llvm-svn: 74200
2009-06-25 20:59:23 +00:00
d76d0aa68a
Move thumb and thumb2 tests into separate directories.
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llvm-svn: 74068
2009-06-24 06:36:07 +00:00
4983e4550e
Proper patterns for thumb2 shift and rotate instructions.
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llvm-svn: 73987
2009-06-23 19:39:13 +00:00
2e076c4e02
Add support for ARM's Advanced SIMD (NEON) instruction set.
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This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00
16ee19738c
It's coalescer, not coaleser.
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llvm-svn: 73902
2009-06-22 21:09:17 +00:00
4582530a2c
For Darwin on ARMv6 and newer, make register r9 available for use as a
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caller-saved register.
llvm-svn: 73901
2009-06-22 21:01:46 +00:00
8cbbc7944d
Fix another register coalescer crash: forgot to check if the instruction being updated has already been coalesced.
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llvm-svn: 73898
2009-06-22 20:49:32 +00:00
3d75d6af57
hasFP should return true if frame address is taken.
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llvm-svn: 73893
2009-06-22 18:38:48 +00:00
c6a8d0dbe9
Fix PR4419: handle defs of partial uses.
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llvm-svn: 73816
2009-06-20 04:34:51 +00:00
b4b20bbb7d
Enable arm pre-allocation load / store multiple optimization pass.
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llvm-svn: 73791
2009-06-19 23:17:27 +00:00
d984158320
Mark a few Thumb instructions commutable; just happened to spot this
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while experimenting. I'm reasonably sure this is correct, but please
tell me if these instructions have some strange property which makes this
change unsafe.
llvm-svn: 73746
2009-06-19 01:43:08 +00:00
02bb33c58d
Initial support for some Thumb2 instructions.
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Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
llvm-svn: 73622
2009-06-17 18:13:58 +00:00
469e8217d4
Make the test target-neutral
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llvm-svn: 73547
2009-06-16 20:25:25 +00:00
5d28cb204f
GNU as refuses to assemble "pop {}" instruction. Do not emit such
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(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).
llvm-svn: 73529
2009-06-16 18:49:08 +00:00
cc21a5415a
If a val# is defined by an implicit_def and it is being removed, all of the copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead.
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TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block.
llvm-svn: 73478
2009-06-16 07:12:58 +00:00
b9bff5880a
ifcvt should ignore cfg where true and false successors are the same.
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llvm-svn: 73423
2009-06-15 21:24:34 +00:00
1283c6a066
Part 1.
...
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
llvm-svn: 73381
2009-06-15 08:28:29 +00:00
185c9ef0a2
Add a ARM specific pre-allocation pass that re-schedule loads / stores from
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consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.
This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.
llvm-svn: 73291
2009-06-13 09:12:55 +00:00
b6cf8dbb96
If killed register is defined by implicit_def, do not clear it since it's live range may overlap another def of same register.
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llvm-svn: 73255
2009-06-12 21:34:26 +00:00
d93b5b672f
Mark some pattern-less instructions as neverHasSideEffects.
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llvm-svn: 73252
2009-06-12 20:46:18 +00:00
c745132865
Add testcase for register scanveger assertion fix in r72755
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(double def due to livevars)
llvm-svn: 73096
2009-06-08 22:54:15 +00:00
3158790e32
Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
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llvm-svn: 72955
2009-06-05 19:08:58 +00:00
a5b9645c4b
Split the Add, Sub, and Mul instruction opcodes into separate
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integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.
For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.
This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt
llvm-svn: 72897
2009-06-04 22:49:04 +00:00
60fdf787a7
A value defined by an implicit_def can be liven to a use BB. This is unfortunate. But register allocator still has to add it to the live-in set of the use BB.
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llvm-svn: 72888
2009-06-04 20:25:48 +00:00
7f5976e11b
Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
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llvm-svn: 72826
2009-06-04 01:15:28 +00:00
ab0c710fae
Temporarily revert 72756 for now.
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llvm-svn: 72757
2009-06-03 07:40:47 +00:00
dfe6e689fd
Fold preceding / trailing base inc / dec into the single load / store as well.
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llvm-svn: 72756
2009-06-03 06:14:58 +00:00
e666cc5206
Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 and
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the stack. Patch by Sandeep Patel.
llvm-svn: 72106
2009-05-19 10:02:36 +00:00
a2c462bbe9
Fix pr4091: Add support for "m" constraint in ARM inline assembly.
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llvm-svn: 72105
2009-05-19 05:53:42 +00:00
b81dd48fd2
Add nounwind to a few tests.
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llvm-svn: 72002
2009-05-18 15:16:49 +00:00
9e3d48f10d
Fix pr4195: When iterating through predecessor blocks, break out of the loop
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after finding the (unique) layout predecessor. Sometimes a block may be listed
more than once, and processing it more than once in this loop can lead to
inconsistent values for FtTBB/FtFBB, since the AnalyzeBranch method does not
clear these values. There's no point in continuing the loop regardless.
The testcase for this is reduced from the 2003-05-02-DependentPHI SingleSource
test.
llvm-svn: 71536
2009-05-12 03:48:10 +00:00
e20be4183c
Fix pr4100. Do not remove no-op copies when they are dead. The register
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scavenger gets confused about register liveness if it doesn't see them.
I'm not thrilled with this solution, but it only comes up when there are dead
copies in the code, which is something that hopefully doesn't happen much.
Here is what happens in pr4100: As shown in the following excerpt from the
debug output of llc, the source of a move gets reloaded from the stack,
inserting a new load instruction before the move. Since that source operand
is a kill, the physical register is free to be reused for the destination
of the move. The move ends up being a no-op, copying R3 to R3, so it is
deleted. But, it leaves behind the load to reload %reg1028 into R3, and
that load is not updated to show that it's destination operand (R3) is dead.
The scavenger gets confused by that load because it thinks that R3 is live.
Starting RegAlloc of: %reg1025<def,dead> = MOVr %reg1028<kill>, 14, %reg0, %reg0
Regs have values:
Reloading %reg1028 into R3
Last use of R3[%reg1028], removing it from live set
Assigning R3 to %reg1025
Register R3 [%reg1025] is never used, removing it from live set
Alternative solutions might be either marking the load as dead, or zapping
the load along with the no-op copy. I couldn't see an easy way to do
either of those, though.
llvm-svn: 71196
2009-05-07 23:47:03 +00:00
cfc0513080
Do not use register as base ptr of pre- and post- inc/dec load / store nodes.
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llvm-svn: 71098
2009-05-06 18:25:01 +00:00
ff08995589
Previously, RecursivelyDeleteDeadInstructions provided an option
...
of returning a list of pointers to Values that are deleted. This was
unsafe, because the pointers in the list are, by nature of what
RecursivelyDeleteDeadInstructions does, always dangling. Replace this
with a simple callback mechanism. This may eventually be removed if
all clients can reasonably be expected to use CallbackVH.
Use this to factor out the dead-phi-cycle-elimination code from LSR
utility function, and generalize it to use the
RecursivelyDeleteTriviallyDeadInstructions utility function.
This makes LSR more aggressive about eliminating dead PHI cycles;
adjust tests to either be less trivial or to simply expect fewer
instructions.
llvm-svn: 70636
2009-05-02 18:29:22 +00:00
9c1ec76084
Rename file to have the correct suffix.
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llvm-svn: 69380
2009-04-17 20:40:20 +00:00
a4c2290e5f
Use CallConvLower.h and TableGen descriptions of the calling conventions
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for ARM. Patch by Sandeep Patel.
llvm-svn: 69371
2009-04-17 19:07:39 +00:00
0a40ad93a9
Expand GEPs in ScalarEvolution expressions. SCEV expressions can now
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have pointer types, though in contrast to C pointer types, SCEV
addition is never implicitly scaled. This not only eliminates the
need for special code like IndVars' EliminatePointerRecurrence
and LSR's own GEP expansion code, it also does a better job because
it lets the normal optimizations handle pointer expressions just
like integer expressions.
Also, since LLVM IR GEPs can't directly index into multi-dimensional
VLAs, moving the GEP analysis out of client code and into the SCEV
framework makes it easier for clients to handle multi-dimensional
VLAs the same way as other arrays.
Some existing regression tests show improved optimization.
test/CodeGen/ARM/2007-03-13-InstrSched.ll in particular improved to
the point where if-conversion started kicking in; I turned it off
for this test to preserve the intent of the test.
llvm-svn: 69258
2009-04-16 03:18:22 +00:00
b866ce73b2
Use the output of the asm so the optimizer won't
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delete it.
llvm-svn: 69018
2009-04-14 01:51:40 +00:00
4d59f88e60
move a target-specific test into its directory so it isn't run if you
...
don't configure the ARM target in.
llvm-svn: 68843
2009-04-10 23:58:38 +00:00
51856173c8
Fix pr3954. The register scavenger asserts for inline assembly with
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register destinations that are tied to source operands. The
TargetInstrDescr::findTiedToSrcOperand method silently fails for inline
assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very
close to doing what is needed, so this revision makes a few changes to
that method and also renames it to isRegTiedToUseOperand (for consistency
with the very similar isRegTiedToDefOperand and because it handles both
two-address instructions and inline assembly with tied registers).
llvm-svn: 68714
2009-04-09 17:16:43 +00:00
8462791237
Add testcase for PR3795.
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llvm-svn: 68620
2009-04-08 18:00:55 +00:00
5a82613db0
Soft float support for FREM.
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llvm-svn: 68614
2009-04-08 16:20:57 +00:00
fb438caac6
Soft float support for undef. Reported by Xerxes Rånby.
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llvm-svn: 68607
2009-04-08 13:33:37 +00:00
0669f6d295
Handle 'a' modifier in ARM inline assembly.
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Patch by Richard Pennington.
llvm-svn: 68464
2009-04-06 21:46:51 +00:00
cf1ec2cc68
Fix PR3862: Recognize some ARM-specific constraints for immediates in inline
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assembly.
llvm-svn: 68218
2009-04-01 17:58:54 +00:00
a774a99245
Do not emit comments unless -asm-verbose.
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llvm-svn: 67580
2009-03-24 00:17:40 +00:00
7b87e542dc
add no-unwind, remove duplicate run line.
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llvm-svn: 66775
2009-03-12 05:56:37 +00:00
ce5dfb692a
ARM isLegalAddressImmediate should check if type is a simple type now that optimizer can create values of funky scalar types.
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llvm-svn: 66429
2009-03-09 19:15:00 +00:00
ec415efb44
Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly.
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llvm-svn: 66365
2009-03-08 04:02:49 +00:00
de22116f39
If a MI uses the same register more than once, only mark one of them as 'kill'.
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llvm-svn: 66363
2009-03-08 03:58:35 +00:00
398dee1c4a
Last commit accidentially deleted this code.
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llvm-svn: 65679
2009-02-28 06:02:14 +00:00
ca2d65467b
The last commit was overly conservative. It's ok to reuse value that's already marked livein.
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llvm-svn: 65498
2009-02-26 03:02:21 +00:00
e779595af0
If a use operand is marked isKill, don't forget to add kill to its live interval as well.
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llvm-svn: 65279
2009-02-22 08:35:56 +00:00
f505cd5ebb
A couple of places where reused use operands should be marked kill. This is exposed by recent availability fallthrough changes.
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llvm-svn: 64745
2009-02-17 06:41:03 +00:00
3a14efacb6
Replace one of burr scheduling heuristic with something more sensible. Now calcMaxScratches simply compute the number of true data dependencies. This actually improve a couple of tests in dejagnu suite as many tests in llvm nightly test suite.
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llvm-svn: 64369
2009-02-12 08:59:45 +00:00
ce3bbe515b
Fix PR3457: Ignore control successors when looking for closest scheduled successor. A control successor doesn't read result(s) produced by the scheduling unit being evaluated.
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llvm-svn: 64210
2009-02-10 08:30:11 +00:00
f736bd9c79
Re-enable machine sinking pass now that the coalescer bugs and the AnalyzeBrnach bug are fixed.
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llvm-svn: 64126
2009-02-09 08:45:39 +00:00
5469ec1072
Revert r63999. It was breaking self-hosting builds.
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llvm-svn: 64062
2009-02-08 00:58:05 +00:00
9571621665
Enable machine sinking pass in non-fast mode.
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llvm-svn: 63999
2009-02-07 01:57:46 +00:00
409c25f78d
Turn on machine LICM in non-fast mode.
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llvm-svn: 63855
2009-02-05 08:46:33 +00:00
6de96a1b5d
Add the private linkage.
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llvm-svn: 62279
2009-01-15 20:18:42 +00:00
ab85feb91c
Clean up some ARM GV asm printing out; minor fixes to match what gcc does.
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llvm-svn: 60621
2008-12-06 02:00:55 +00:00
c22215a090
- Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction.
...
- When scavenging a register, in addition to the spill, insert a restore before the first use.
- Abort if client is looking to scavenge a register even when a previously scavenged register is still live.
llvm-svn: 59697
2008-11-20 02:32:35 +00:00
3095c32c89
Register scavenger should process early clobber defs first. A dead early clobber def should not interfere with a normal def which happens one slot later.
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llvm-svn: 59559
2008-11-18 22:28:38 +00:00
e3827d9061
Actually ARM / Mac OS X does have UINTTOFP_I64_F{64|32} libcalls.
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llvm-svn: 58725
2008-11-04 22:19:55 +00:00
297b32a367
Custom lower bit_convert i64 -> f64 into FMDRR. This is now happening with legalizetypes.
...
llvm-svn: 58714
2008-11-04 19:57:48 +00:00
9eb525d4f9
Implement function notes as function attributes.
...
llvm-svn: 56716
2008-09-26 23:51:19 +00:00
f3fcd7a464
Unallocatable registers do not have live intervals.
...
llvm-svn: 56287
2008-09-17 18:36:25 +00:00
3c7b9ba547
Re-enable SelectionDAG CSE for calls. It matters in the case of
...
libcalls, as in this testcase on ARM.
llvm-svn: 56226
2008-09-15 19:46:03 +00:00
02acc35abd
Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#.
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llvm-svn: 56199
2008-09-15 06:28:41 +00:00
f4e5de4583
Legalizer was missing code that expand fpow to a libcall.
...
llvm-svn: 56028
2008-09-09 23:02:14 +00:00
655fa0fec4
It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool.
...
llvm-svn: 54519
2008-08-08 06:56:16 +00:00
9dbbd75068
Print section flags ok on platforms, which use '@' as comment string. Fix test.
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llvm-svn: 54460
2008-08-07 09:55:06 +00:00
04c047ddca
This check is unnecessary, and getting rid of it removes a use of -disable-correct-folding.
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llvm-svn: 54355
2008-08-05 17:52:54 +00:00
252fa16db1
Remove the need for -disable-correct-folding from this test.
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llvm-svn: 54354
2008-08-05 17:49:52 +00:00
5018bd032a
Update these tests to work by disabling the new correct CFG generation. This flag should ONLY be used to for tests like these.
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llvm-svn: 54334
2008-08-04 23:55:29 +00:00
c90a11256e
Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589.
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llvm-svn: 54004
2008-07-25 00:55:17 +00:00
6b418e750d
Softfloat support for FDIV. Patch by
...
Richard Pennington.
llvm-svn: 53773
2008-07-18 21:18:48 +00:00
1e427c3264
sabre brings to my attention that the 'tr' suffix is also obsolete
...
llvm-svn: 51349
2008-05-20 21:00:03 +00:00
f45ff35bfe
Rename the last test with .llx extension to .ll, resolve duplicate test by renaming to isnan2. Now that no test has llx ending there is no need to search for them from dg.exp too.
...
llvm-svn: 51328
2008-05-20 19:52:04 +00:00
0609ab646b
More local spiller complexity!
...
If local spiller optimization turns some instruction into an identity copy, it will be removed. If the output register happens to be dead (and source is obviously killed), transfer the kill / dead information to last use / def in the same MBB.
llvm-svn: 51306
2008-05-20 08:13:21 +00:00
c8b028daa4
Don't spill dead def.
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llvm-svn: 51305
2008-05-20 08:10:37 +00:00
33281864c1
If a PHI node has a single implicit_def source, replace it with an implicit_def instead of a copy.
...
llvm-svn: 49543
2008-04-11 17:54:45 +00:00
b53d560150
New test.
...
llvm-svn: 49514
2008-04-10 23:49:09 +00:00
b5fdc923d3
1. IMPLICIT_DEF can *re-define* any register.
...
2. Coalescer can now create an interesting situation where a register def can
reaches itself without being killed.
llvm-svn: 49246
2008-04-05 01:27:09 +00:00
0bd72c5ccd
More soft fp fixes.
...
llvm-svn: 49016
2008-04-01 02:18:22 +00:00
86e476b7cb
Unbreak ARM / Thumb soft FP support.
...
llvm-svn: 49012
2008-04-01 01:50:16 +00:00
39a3221e27
Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI.
...
llvm-svn: 48024
2008-03-07 20:12:54 +00:00
a3cb090446
Constant fold SIGN_EXTEND_INREG with ashr not lshr.
...
llvm-svn: 47992
2008-03-06 08:20:51 +00:00
16f1e0be3d
DCE'ed this testcase.
...
llvm-svn: 47760
2008-02-29 19:28:11 +00:00
811153a551
If we reload a virtual register that's already been assigned, we want to mark
...
that instruction as its "last use". This fixes PR1925.
llvm-svn: 47758
2008-02-29 18:52:01 +00:00
f697c03883
Remove llvm-upgrade.
...
llvm-svn: 47238
2008-02-17 20:02:20 +00:00
127b41500c
It's PR1925, not PR1609.
...
llvm-svn: 46825
2008-02-06 22:07:17 +00:00
1ec748c784
Fix a number of local register allocator issues: PR1609.
...
llvm-svn: 46821
2008-02-06 19:16:53 +00:00
34d6b6a319
Update this test. Due to dag combiner improvements, we now compile
...
f7/f11 to:
_f7:
eor r0, r0, #2 , 2 @ -2147483648
bx lr
_f11:
bic r0, r0, #2 , 2 @ -2147483648
bx lr
instead of:
_f7:
fmsr s0, r0
fnegs s0, s0
fmrs r0, s0
bx lr
_f11:
fmsr s0, r0
fabss s0, s0
fmrs r0, s0
bx lr
llvm-svn: 46423
2008-01-27 23:26:37 +00:00
ddc9af11f0
Remove xfail. This is fixed.
...
llvm-svn: 45254
2007-12-20 02:25:21 +00:00
8393dc7378
Turning simple splitting on. Start testing new coalescer heuristics as new llcbeta.
...
llvm-svn: 44660
2007-12-06 08:54:31 +00:00
7fc1d98353
Fix for PR1831: if all defs of an interval are re-materializable, then it's a preferred spill candiate.
...
llvm-svn: 44644
2007-12-06 00:01:56 +00:00
37ed3e6320
Update tests.
...
llvm-svn: 44435
2007-11-29 10:03:54 +00:00
e04dc1fa4d
update this test after the fmrrd fix
...
llvm-svn: 44393
2007-11-28 05:27:07 +00:00
8f342f8ef3
Fix bug in regression tests that ignored stderr output in RUN lines. Updated tests and fixed broken run lines.
...
XFAILed 3 arm regressions (will file bugs)
llvm-svn: 44389
2007-11-28 04:57:00 +00:00
f247e27666
commit testcase I forgot to svn add.
...
llvm-svn: 44383
2007-11-27 22:43:37 +00:00
f6a67bf700
[ARM] Implement __builtin_thread_pointer.
...
llvm-svn: 43892
2007-11-08 17:20:05 +00:00
1a30c18e88
[ARM] Fix code generation for:
...
static __thread struct {
int a;
int b;
} teste = {0, 0};
llvm-svn: 43722
2007-11-05 18:33:37 +00:00
1f2dd35898
Fix memcpy lowering when addresses are 4-byte aligned but size is not multiple of 4.
...
llvm-svn: 43234
2007-10-22 22:11:27 +00:00
2ce649ebea
new testcase
...
llvm-svn: 42953
2007-10-13 06:56:18 +00:00
723dab1005
Disable if-conversion for this test.
...
llvm-svn: 42170
2007-09-20 18:06:22 +00:00
77d4771405
-enable-arm-if-conversion is gone.
...
llvm-svn: 42169
2007-09-20 18:03:23 +00:00
6480cc6f8c
Change all floating constants that are not exactly
...
representable to use hex format.
llvm-svn: 41722
2007-09-05 17:50:36 +00:00
6820abe101
Testcases for PR1628.
...
llvm-svn: 41719
2007-09-05 11:53:04 +00:00
a392cd2fde
Implement FPOWI ExpandOp.
...
Fix PR1287.
llvm-svn: 41112
2007-08-15 22:13:27 +00:00
2047077272
Test case for PR1609.
...
llvm-svn: 41110
2007-08-15 20:30:10 +00:00
413a23d257
This test used "wc | grep ..."; convert it to use the count script.
...
llvm-svn: 41101
2007-08-15 13:55:47 +00:00
ada7205b76
Convert tests using "grep -c ... | grep ..." to use the count script.
...
llvm-svn: 41100
2007-08-15 13:49:33 +00:00
f9dd170e36
Convert tests using "| wc -l | grep ..." to use the count script.
...
llvm-svn: 41097
2007-08-15 13:36:28 +00:00
7fe896120e
New test.
...
llvm-svn: 41087
2007-08-14 23:34:50 +00:00
0db4418a5f
Expand unaligned loads/stores when the target doesn't support them. (PR1548)
...
llvm-svn: 40682
2007-08-01 19:34:21 +00:00
314e1cb7ee
For PR1553:
...
Change the keywords for the zext and sext parameter attributes to be
zeroext and signext so they don't conflict with the keywords for the
instructions of the same name. This gets around the ambiguity.
llvm-svn: 40069
2007-07-19 23:13:04 +00:00
5740239998
Add explicit triples to these tests so that llc behaves as expected on
...
non-Apple hosts.
llvm-svn: 38455
2007-07-09 13:42:32 +00:00
2660cef6d7
Convert .cvsignore files
...
llvm-svn: 37801
2007-06-29 16:35:07 +00:00
0de7694de6
Fix an assertion failure in legalizing bitcast operators on targets where
...
vectors are split down to single elements as part of legalization.
llvm-svn: 37785
2007-06-29 00:09:08 +00:00
e15ea75168
Fix tests.
...
llvm-svn: 37693
2007-06-21 18:22:42 +00:00
5fcb5a5c74
New tests.
...
llvm-svn: 37686
2007-06-21 07:40:00 +00:00
85010166a6
Added some if-conversion tests.
...
llvm-svn: 37672
2007-06-20 18:26:15 +00:00
5a3e6fe365
Add a test for PR1424.
...
llvm-svn: 37372
2007-05-31 18:36:07 +00:00
b58bf97603
Add a new test case.
...
llvm-svn: 37317
2007-05-24 02:31:15 +00:00
a7120dde08
new testcases for -enable-tail-merge default handling
...
llvm-svn: 37287
2007-05-22 17:19:23 +00:00
c5900bd25b
testcase that crashes llc
...
llvm-svn: 37059
2007-05-15 01:13:42 +00:00
4c28ec187e
Test for PR1406.
...
llvm-svn: 37051
2007-05-14 21:12:43 +00:00
3551928a2b
Enable aliases on arm-linux.
...
llvm-svn: 37042
2007-05-14 18:32:56 +00:00
b42c11265c
Another test for tail mergeing
...
llvm-svn: 36967
2007-05-10 01:04:28 +00:00
db214c77b4
Can't fold bit_convert into truncating store.
...
llvm-svn: 36963
2007-05-09 21:54:34 +00:00
882a6019af
testcase for CodeGenPrepare bug fixed yesterday
...
llvm-svn: 36940
2007-05-08 17:44:36 +00:00
4ef41c1054
move this out of Codegen/Generic, because it requires the ARM backend to be
...
linked into llc
llvm-svn: 36919
2007-05-08 02:19:56 +00:00
ef409e2780
Fix tests.
...
llvm-svn: 36913
2007-05-07 21:50:07 +00:00
2d828d2e3c
Add some tests for (conv (load x)) -> (load (conv*)x) xform.
...
llvm-svn: 36912
2007-05-07 21:49:35 +00:00
34b2735f20
Fix PR1390.
...
Don't spill extra register to align the stack.
llvm-svn: 36814
2007-05-05 23:44:41 +00:00
1c0af142a9
remove xfailed testcase (attached to pr)
...
llvm-svn: 36797
2007-05-05 21:57:34 +00:00
726e66f734
Test load global in static mode.
...
llvm-svn: 36719
2007-05-04 00:29:34 +00:00
579abf45bb
New test case.
...
llvm-svn: 36717
2007-05-03 23:53:36 +00:00
89200ce0f0
Evan's patch to avoid FPreg->intreg copy for cvt; store to mem
...
llvm-svn: 36693
2007-05-03 20:54:42 +00:00
483dc2bf08
match a reassociated form of fnmul
...
llvm-svn: 36659
2007-05-03 00:31:40 +00:00
8a16201953
Test a dag combiner crasher.
...
llvm-svn: 36605
2007-05-01 00:40:38 +00:00
e7449654d1
For PR1370:
...
Rearrange some tests so that if PowerPC is not being built we don't try to
run PowerPC specific tests.
llvm-svn: 36587
2007-04-30 05:11:58 +00:00
193d2f09f0
update syntax
...
llvm-svn: 36531
2007-04-28 06:03:12 +00:00
940b083a63
fix the test tls1.
...
llvm-svn: 36517
2007-04-27 21:23:17 +00:00
04750a18be
add TLS tests.
...
llvm-svn: 36516
2007-04-27 21:08:48 +00:00
62f65468bc
In Thumb mode, the frame register must be R7.
...
llvm-svn: 36512
2007-04-27 17:58:03 +00:00
4ae9425bb6
remember to emit weak reference in one more case.
...
llvm-svn: 36438
2007-04-25 14:50:40 +00:00
ee2d164f0f
Implement PIC for arm-linux.
...
llvm-svn: 36324
2007-04-22 00:04:12 +00:00
225b2732a4
Use the llvm_supports_target function to prevent running of tests for
...
targets that LLVM is not configured to support.
llvm-svn: 36315
2007-04-21 20:41:27 +00:00
0c8add06f1
Fix test.
...
llvm-svn: 36150
2007-04-16 18:55:46 +00:00
6e87ec4351
For PR1319:
...
Remove && from the end of the lines to prevent tests from throwing run
lines into the background. Also, clean up places where the same command
is run multiple times by using a temporary file.
llvm-svn: 36142
2007-04-16 17:36:08 +00:00
675732ad38
Fix hello.ll test.
...
llvm-svn: 36141
2007-04-16 17:08:00 +00:00
b1d58a5281
Fix align test.
...
llvm-svn: 36140
2007-04-16 16:57:47 +00:00
86f337eeda
For PR1319:
...
Fix test syntax per new rules.
llvm-svn: 36133
2007-04-16 15:15:52 +00:00
6584cf60f2
For PR1336:
...
XFAIL tests covered by the PR. These will be un-XFAILed as they are fixed.
llvm-svn: 36093
2007-04-15 23:00:46 +00:00
ff8169f5cb
For PR1319: Upgrade to new test harness.
...
llvm-svn: 36086
2007-04-15 20:48:50 +00:00
b5dc70c270
For PR1319: Upgrade to use new test harness
...
llvm-svn: 36076
2007-04-15 19:11:47 +00:00
c8ff09ffaa
fix test for linux hosts.
...
llvm-svn: 36026
2007-04-14 23:04:30 +00:00
d0b3e7b0b4
xfail this for now
...
llvm-svn: 35973
2007-04-13 22:20:27 +00:00
03bf40e70e
new lsr testcase
...
llvm-svn: 35971
2007-04-13 20:38:14 +00:00
d029c7e666
Make the llvm-runtest function much more amenable by eliminating all the
...
global variables that needed to be passed in. This makes it possible to
add new global variables with only a couple changes (Makefile and llvm-dg.exp)
instead of touching every single dg.exp file.
llvm-svn: 35918
2007-04-11 19:56:59 +00:00
2feb7abbd5
this got better
...
llvm-svn: 35908
2007-04-11 16:12:27 +00:00
9f780e339e
new testcases for integer abs function
...
llvm-svn: 35880
2007-04-11 05:02:57 +00:00
8f61b79d60
Better still.
...
llvm-svn: 35663
2007-04-04 08:49:40 +00:00
06df995e9f
Fix test case.
...
llvm-svn: 35662
2007-04-04 07:41:33 +00:00
ee06655d6b
These got better.
...
llvm-svn: 35661
2007-04-04 07:41:15 +00:00
07d353c9d7
New asm test case.
...
llvm-svn: 35641
2007-04-04 00:15:17 +00:00
10a25d43fa
New test case.
...
llvm-svn: 35636
2007-04-03 23:40:54 +00:00
2c2ec5f138
New test case.
...
llvm-svn: 35628
2007-04-03 21:38:03 +00:00
67f99e955b
new testcase, where we should use a negative stride
...
llvm-svn: 35608
2007-04-03 00:13:16 +00:00
f7f8e349d6
New test case.
...
llvm-svn: 35599
2007-04-02 18:47:13 +00:00
be96c646dc
new testcase.
...
llvm-svn: 35591
2007-04-02 06:33:10 +00:00
6be85337b0
- Divides the comparisons in two types: comparisons that only use N and Z
...
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
llvm-svn: 35573
2007-04-02 01:30:03 +00:00
67a49736af
Missing '&&'
...
llvm-svn: 35519
2007-03-30 22:03:49 +00:00
9ca63d605c
Test case for PR1279 (part 2).
...
llvm-svn: 35511
2007-03-30 20:15:22 +00:00
44259a29c0
Remove use of implementation keyword.
...
llvm-svn: 35412
2007-03-28 02:38:26 +00:00
1f4acbfea9
Added a test case for PR1279.
...
llvm-svn: 35398
2007-03-28 01:32:57 +00:00
44a7f3a65d
Test case for PR1266.
...
llvm-svn: 35367
2007-03-26 22:58:35 +00:00
9a95c6e7db
Another test case.
...
llvm-svn: 35255
2007-03-22 01:55:16 +00:00
51ace3b1f6
Test case for PR1257
...
llvm-svn: 35253
2007-03-22 01:52:57 +00:00
a7f81f29ce
New test case.
...
llvm-svn: 35240
2007-03-21 20:14:56 +00:00
a88c4a74f3
bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
...
mov lr, pc
bx lr
So, the function was not called.
llvm-svn: 35218
2007-03-20 17:57:23 +00:00
7953b683fc
For PR1258:
...
Revise numeric value references to accommodate collapsed type planes.
llvm-svn: 35170
2007-03-19 18:27:35 +00:00
bbe11722e2
GEP index sink test case.
...
llvm-svn: 35131
2007-03-17 03:18:32 +00:00
70e16d5e17
ARM isel should match ldr x +/- x * (2^n) to ldr [x, +/- x, lsl #log2(n)].
...
llvm-svn: 35114
2007-03-14 23:26:40 +00:00
b59d60da40
New test.
...
llvm-svn: 35091
2007-03-13 23:31:47 +00:00
fe7b8a7c68
Test inline asm modifier 'c'.
...
llvm-svn: 35036
2007-03-08 22:45:31 +00:00
f4d1ee7ff2
Fix test case.
...
llvm-svn: 35029
2007-03-08 19:27:32 +00:00
a5c7f5d622
New test case.
...
llvm-svn: 35006
2007-03-07 08:12:39 +00:00
bd88f2ebde
New test case.
...
llvm-svn: 34991
2007-03-07 00:13:48 +00:00
f10769dda7
Use init_array/fini_array sections for static contructors/destructors when the ABI is AAPCS.
...
Fix SingleSource/Regression/C/ConstructorDestructorAttributes test on arm-linux-gnueabi.
llvm-svn: 34931
2007-03-05 17:59:58 +00:00
add648e3e5
Fix test case.
...
llvm-svn: 34710
2007-02-28 00:36:33 +00:00
0eb70ebbe5
bugfix: SP wasn't updated for varargs when frame pointer was eliminated.
...
llvm-svn: 34537
2007-02-23 21:53:48 +00:00
3e906c48d3
Fix stack alignment in functions with varargs.
...
llvm-svn: 34532
2007-02-23 20:32:57 +00:00
fa6532a3b9
-march=arm -enable-thumb => -march=thumb
...
llvm-svn: 34522
2007-02-23 03:15:39 +00:00
048e16ff8f
Add ABI information to ARM subtarget.
...
llvm-svn: 34245
2007-02-13 19:52:28 +00:00
603f201cba
According to ARM EABI, 8-bytes function arguments must be 8-bytes aligned.
...
llvm-svn: 34241
2007-02-13 14:07:13 +00:00
815c25d191
i64 setcc tests.
...
llvm-svn: 34067
2007-02-08 22:27:55 +00:00
08dfee58d9
New test case.
...
llvm-svn: 34001
2007-02-07 09:24:03 +00:00
5a165de53c
Add a DYNAMIC_STACKALLOC test case.
...
llvm-svn: 33959
2007-02-06 07:18:27 +00:00
809cbf527f
Fix unord test.
...
llvm-svn: 33910
2007-02-05 16:33:56 +00:00
9d851fca1e
Add a test case.
...
llvm-svn: 33833
2007-02-03 09:14:10 +00:00
bcc6db26e1
__builtin_isunordered test case.
...
llvm-svn: 33808
2007-02-03 00:50:45 +00:00
1a0ae50528
Improves alloca test. Verifies SP restoration.
...
llvm-svn: 33802
2007-02-03 00:16:21 +00:00
2341c22ec7
Changes to support making the shift instructions be true BinaryOperators.
...
This feature is needed in order to support shifts of more than 255 bits
on large integer types. This changes the syntax for llvm assembly to
make shl, ashr and lshr instructions look like a binary operator:
shl i32 %X, 1
instead of
shl i32 %X, i8 1
Additionally, this should help a few passes perform additional optimizations.
llvm-svn: 33776
2007-02-02 02:16:23 +00:00
26cc265311
My mistake, my environment wasn't up to date. This passes now.
...
llvm-svn: 33769
2007-02-01 22:26:42 +00:00
a5dc052682
XFAIL this on x86 linux as it continues to fail.
...
llvm-svn: 33768
2007-02-01 22:10:46 +00:00
210cbc43a8
Add a test case.
...
llvm-svn: 33742
2007-02-01 02:27:24 +00:00
c79b96b00d
Added a thumb vararg test.
...
llvm-svn: 33740
2007-02-01 01:56:43 +00:00
b7a08adae6
Fix test case.
...
llvm-svn: 33730
2007-01-31 23:51:35 +00:00
53ac41cd54
Fix test cases.
...
llvm-svn: 33725
2007-01-31 22:27:07 +00:00
7ae4f5599e
ARM fix: Miscompilation when frame pointer can't be eliminated. Uninitialized frame pointer register is used.
...
llvm-svn: 33703
2007-01-31 13:12:46 +00:00
421fdb2a7e
Combine two tests.
...
llvm-svn: 33668
2007-01-30 23:06:22 +00:00
af6a408117
For PR411:
...
Update these tests to not use the same name even though the type of the
value differs. After PR411 hits, type planes will be gone and it will be
illegal for a name to be used twice, regardless of type.
llvm-svn: 33660
2007-01-30 16:16:01 +00:00
fcb9b8b0b7
Add / merge tests.
...
llvm-svn: 33654
2007-01-30 03:06:19 +00:00
9f82ccb01f
Thumb tests.
...
llvm-svn: 33561
2007-01-27 00:05:14 +00:00
df446c6f72
Merge tests.
...
llvm-svn: 33560
2007-01-27 00:04:57 +00:00
ce380568b5
For PR761:
...
Remove "target endian/pointersize" or add "target datalayout" to make
the test parse properly or set the datalayout because defaults changes.
For PR645:
Make global names use the @ prefix.
For llvm-upgrade changes:
Fix test cases or completely remove use of llvm-upgrade for test cases
that cannot survive the new renaming or upgrade capabilities.
llvm-svn: 33533
2007-01-26 08:25:06 +00:00
b5c595c568
fix fcopysign test
...
llvm-svn: 33503
2007-01-25 22:11:02 +00:00
dda311a784
Added some load from stack frames test cases.
...
llvm-svn: 33473
2007-01-24 02:27:03 +00:00
029a72b9fa
Thumb test cases.
...
llvm-svn: 33471
2007-01-23 23:28:50 +00:00
36b74471c8
Thumb test cases.
...
llvm-svn: 33468
2007-01-23 22:47:58 +00:00
76231aad45
Make it work for both Linux and Mac OS.
...
llvm-svn: 33451
2007-01-22 23:18:10 +00:00
136cf76a27
Pasto
...
llvm-svn: 33444
2007-01-22 23:01:22 +00:00
527faab942
Fix test case.
...
llvm-svn: 33432
2007-01-22 18:57:39 +00:00
fec133d2d1
Add test case extracted from lencod. Spiller was infinite looping in GetRegForReload().
...
llvm-svn: 33383
2007-01-19 22:43:14 +00:00
Evan Cheng