637ca93fc4
doxygenify
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llvm-svn: 76750
2009-07-22 16:53:56 +00:00
c0647b31ee
Add newline at end of file.
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llvm-svn: 76736
2009-07-22 13:20:41 +00:00
4f7f19a7c0
Thread local globals don't require special handling by the linker and so can
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be placed in the standard data / bss sections.
llvm-svn: 76735
2009-07-22 11:01:00 +00:00
0cf7f5d6d2
Revert commit 76707, it was breaking the llvm-gcc build
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on linux platforms. The binutils assembler does not
recognize the "s" flag, see for example
http://sourceware.org/binutils/docs/as/Section.html
llvm-svn: 76733
2009-07-22 10:35:05 +00:00
315596c39c
Don't give a massive inlining cost bonus to available_externally
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functions with a single use; eliminating the single use may eliminate
the function from the current module, but usually doesn't eliminate
it from the final program.
llvm-svn: 76730
2009-07-22 08:12:59 +00:00
4b02b2f79c
Don't forget D16 - D31 are clobbered by calls and sjlj eh.
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llvm-svn: 76729
2009-07-22 06:46:53 +00:00
6253a19651
Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions.
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llvm-svn: 76728
2009-07-22 06:37:28 +00:00
eadb6681cf
Fix a obvious copy-n-paste bug.
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llvm-svn: 76727
2009-07-22 06:12:40 +00:00
2e1d66847c
Get rid one of the getRegisterNumbering. Also add D16 - D31.
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llvm-svn: 76725
2009-07-22 05:55:18 +00:00
caccc0081a
Add support for MMX VSETCC.
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llvm-svn: 76713
2009-07-22 01:06:52 +00:00
5e4755943e
Added the unconditional JMP with an 8-bit relocation for the
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assembler / disassembler.
llvm-svn: 76712
2009-07-22 01:05:20 +00:00
c7a243dfdd
Add an entry.
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llvm-svn: 76711
2009-07-22 00:58:27 +00:00
fd164b863f
inline the two MergeableConstSection implementations into their
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only caller.
llvm-svn: 76710
2009-07-22 00:47:11 +00:00
8ebaec6b27
set the ELF "small" flag on objects that end up in .rodata.cst4 consistently,
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updating a mips testcase to expect it.
llvm-svn: 76707
2009-07-22 00:41:56 +00:00
fab2059d0e
don't set the small flag yet.
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llvm-svn: 76706
2009-07-22 00:30:39 +00:00
b300a4f988
remove the SelectSectionForMachineConst hook, replacing it with
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a new getSectionForMergableConstant hook. This removes one dependence
of TAI on Type, and provides the hook with enough info to make the
right decision based on whether the global has relocations etc.
llvm-svn: 76705
2009-07-22 00:28:43 +00:00
4dc848f3e8
Let each target determines whether a machine instruction is dead. If true, that allows late codeine passes to delete it.
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This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround.
llvm-svn: 76703
2009-07-22 00:25:27 +00:00
47db941fd3
Get rid of the Pass+Context magic.
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llvm-svn: 76702
2009-07-22 00:24:57 +00:00
4565ef5b65
reimplement Constant::ContainsRelocations as
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Constant::getRelocationInfo(), which has a much simpler
to use API. It still should not be part of libvmcore, but
is better than it was. Also teach it to be smart about
hidden visibility.
llvm-svn: 76700
2009-07-22 00:05:44 +00:00
87aaa194f9
Fixing cp island pass. Step 1: Determine whether the constant pool offset can be
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negative on an individual bases rather than basing on whether it's in thumb
mode.
llvm-svn: 76698
2009-07-21 23:56:01 +00:00
f206d925a5
Fix comment.
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llvm-svn: 76693
2009-07-21 23:54:22 +00:00
aa17ab0669
simplify code now that it is inlined.
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llvm-svn: 76689
2009-07-21 23:49:55 +00:00
aa037759b2
Exposed PHIElimination pass within CodeGen.
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llvm-svn: 76688
2009-07-21 23:47:33 +00:00
e61aff6df1
Now that RelocBehaviour() is never overloaded, it doesn't need to be
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virtual. Just inline it into its two current call sites in preparation
for simplifying the code.
llvm-svn: 76686
2009-07-21 23:47:11 +00:00
bc2482a0a4
this doesn't break any of the 4 ia64 tests.
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llvm-svn: 76683
2009-07-21 23:42:24 +00:00
e41745f837
alpha doesn't need to redefine this: it only supports PIC codegen anyway.
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llvm-svn: 76682
2009-07-21 23:41:35 +00:00
3424275325
Add some support for iterative coalescers to calculate a joined live
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range's weight properly. This is turned off right now in the sense that
you'll get an assert if you get into a situation that can only be caused
by an iterative coalescer. All other code paths operate exactly as
before so there is no functional change with this patch. The asserts
should be disabled if/when an iterative coalescer gets added to trunk.
llvm-svn: 76680
2009-07-21 23:36:14 +00:00
9bd736e2f7
no really, I can spell!
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llvm-svn: 76679
2009-07-21 23:36:01 +00:00
cfb01e26bc
add an API so target-independent codegen can determine if a constant
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pool entry will require relocations against it. I implemented this
conservatively for ARM, someone who is knowledgable about it should
see if this can be improved.
llvm-svn: 76678
2009-07-21 23:34:23 +00:00
3666c34db8
Convert instcombine from using using getAnalysis<TargetData> to
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getAnalysisIfAvailable<TargetData>.
llvm-svn: 76676
2009-07-21 23:21:54 +00:00
9413de19b1
Permit the IntPtrTy argument to isEliminableCastPair to be null,
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to help support use when TargetData is not available.
llvm-svn: 76675
2009-07-21 23:19:40 +00:00
40ca1f1c2e
Change ELFCodeEmitter logic to emit the constant pool and jump tables to
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their appropriate sections before the code itself. They need to be emitted
before the function because on some targets (x86 but not x86_64) the later
may reference a JT or CP entry address
llvm-svn: 76672
2009-07-21 23:13:26 +00:00
430f0cc544
Replace the original ad-hoc code for determining whether (v pred w) implies
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(x pred y) with more thorough code that does more complete canonicalization
before resorting to range checks. This helps it find more cases where
the canonicalized expressions match.
llvm-svn: 76671
2009-07-21 23:03:19 +00:00
0ecf7b6f4a
remove the last bits of SectionFlagsForGlobal. There is some flag here that
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depends on XS1A, but I think the ReadOnlySection is already set up for this
and there is no testcase that this breaks. If this is really needed, we can
add the appropriate parameterization to TargetAsmInfo in the future to support
this.
llvm-svn: 76667
2009-07-21 22:42:37 +00:00
bf4bc25236
don't mask out the small flag and then reapply it later.
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llvm-svn: 76666
2009-07-21 22:39:28 +00:00
684d5fe95d
if Xcore doesn't support TLS, it doesn't have to worry about thread local LLVM IR, it should be rejected by a front-end.
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llvm-svn: 76665
2009-07-21 22:37:38 +00:00
43893573f4
remove the Xcore implementation of SelectSectionForGlobal. While you have
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to twist your brain to see it, I believe it is the same as ELFTargetAsmInfo::SelectSectionForGlobal.
llvm-svn: 76664
2009-07-21 22:36:53 +00:00
83e6f9370d
simplify based on the fact that darwin always uses L/l.
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llvm-svn: 76662
2009-07-21 22:32:55 +00:00
5626b88047
make some stuff private.
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llvm-svn: 76661
2009-07-21 22:30:39 +00:00
aa30d25bb4
Remove the XCore custom implementation of MergeableConstSection, relying on
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the generic ELF version instead. This will result in its mergable constant
sections getting named ".rodata.cst4" instead of ".cp.const4", but the
linker looks at the section flags, not the name of the section AFAICT.
llvm-svn: 76659
2009-07-21 22:25:52 +00:00
4d5c3b2e86
inline a trivial method into its only call site and fix indentation of cases
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llvm-svn: 76654
2009-07-21 21:29:08 +00:00
fd047e11a1
Remove some overridden functions in XCoreTargetAsmInfo that are
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implemented exactly the same way as its ELFTargetAsmInfo subclass
has them.
llvm-svn: 76653
2009-07-21 21:26:32 +00:00
1eede6c635
revert r76602, 76603, and r76615, pending design discussions.
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llvm-svn: 76646
2009-07-21 21:12:58 +00:00
c21954dff6
minor cleanups.
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llvm-svn: 76645
2009-07-21 21:09:35 +00:00
3d34492c1f
Privatize the ConstantArray table.
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llvm-svn: 76639
2009-07-21 20:55:28 +00:00
1f74b1fdfd
Missed a piece of the commit to remove the shift flavor.
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llvm-svn: 76635
2009-07-21 20:15:24 +00:00
39ede7b8d1
Privatize the first of the value maps.
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llvm-svn: 76634
2009-07-21 20:13:12 +00:00
da9eda8ef6
Remove shift amount flavor. It isn't actually complete enough to
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be useful, and it's currently unused. (Some issues: it isn't actually
rich enough to capture the semantics on many architectures, and
semantics can vary depending on the type being shifted.)
llvm-svn: 76633
2009-07-21 20:12:16 +00:00
1e08ca7313
Remove a couple of already-implemented notes.
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llvm-svn: 76631
2009-07-21 20:05:43 +00:00
ef1f36d3c7
Prefix IR dumps with LiveInterval indices when possible. This turns
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this:
%ESI<def> = MOV32rr %EDI<kill>
ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
%reg1027<def> = MOVZX64rr32 %ESI
%reg1027<def> = ADD64ri8 %reg1027, 15, %EFLAGS<imp-def,dead>
%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
%RDI<def> = MOV64rr %RSP
%RDI<def> = SUB64rr %RDI, %reg1027<kill>, %EFLAGS<imp-def,dead>
%RSP<def> = MOV64rr %RDI
into this:
4 %reg1024<def> = MOV32rr %EDI<kill>
12 ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
20 %reg1025<def> = MOVZX64rr32 %reg1024
28 %reg1026<def> = MOV64rr %reg1025<kill>
36 %reg1026<def> = ADD64ri8 %reg1026, 15, %EFLAGS<imp-def,dead>
44 %reg1027<def> = MOV64rr %reg1026<kill>
52 %reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
60 %reg1028<def> = MOV64rr %RSP
68 %reg1029<def> = MOV64rr %reg1028<kill>
76 %reg1029<def> = SUB64rr %reg1029, %reg1027<kill>, %EFLAGS<imp-def,dead>
84 %RSP<def> = MOV64rr %reg1029
This helps greatly when debugging register allocation and coalescing
problems.
llvm-svn: 76615
2009-07-21 18:56:32 +00:00
Chris Lattner