399add01d4
Reformatting. No functionalogicality changes.
...
llvm-svn: 116625
2010-10-15 21:50:45 +00:00
a9b3901b47
Refactor ARM fast-isel reg + offset to be a base + offset.
...
llvm-svn: 116622
2010-10-15 21:32:12 +00:00
90f74fe16a
Encoding information for the various ARM saturating add/sub instructions.
...
llvm-svn: 116612
2010-10-15 19:49:46 +00:00
3ba051a4f6
llvmc: Add a test for the -c flag.
...
llvm-svn: 116611
2010-10-15 19:30:49 +00:00
00ce8deae6
ARM binary encoding information for RSB and RSC instructions.
...
llvm-svn: 116604
2010-10-15 18:42:41 +00:00
2d00b1b2e5
Don't mark argument value stores as immutable, as otherwise the post-RA
...
scheduler may reorder loads from them before the stores and other such
badness. PR8347. Patch by David Meyer
llvm-svn: 116602
2010-10-15 18:34:47 +00:00
f1b3681ed0
Use simple RegState::Define flag instead of getDefRegState(true).
...
llvm-svn: 116601
2010-10-15 18:25:59 +00:00
84378f0f53
Refactor alias handling to AliasedSymbol.
...
llvm-svn: 116600
2010-10-15 18:25:33 +00:00
c46e8cb258
KillTheDoctor: Fix 2008 build. I'm actually surprised 2010 defines all of these, many are non-standard posix/unix extensions.
...
llvm-svn: 116597
2010-10-15 18:13:02 +00:00
e4b3d6b379
Expand GEP handling for constant offsets.
...
llvm-svn: 116594
2010-10-15 18:02:07 +00:00
eba55822d7
Teach FileCheck to handle trailing CHECK-NOT patterns.
...
A CHECK-NOT pattern without a following CHECK pattern simply checks that the
pattern doesn't match before the end of the input file.
You can even have only CHECK-NOT patterns to check that strings appear nowhere
in the input file.
llvm-svn: 116592
2010-10-15 17:47:12 +00:00
d15723c22a
When expanding the MOVsr[la]_flag pseudos, the CPSR implicit def becomes
...
an explicit def. Make sure to capture that properly. rdar://8556556
llvm-svn: 116591
2010-10-15 17:35:17 +00:00
68a335e185
ARM mode encoding information for UBFX and SBFX instructions.
...
llvm-svn: 116588
2010-10-15 17:15:16 +00:00
f28cc03802
FileCheckize
...
llvm-svn: 116581
2010-10-15 16:06:42 +00:00
20d103e74e
Remove unused accessor.
...
llvm-svn: 116580
2010-10-15 16:06:40 +00:00
fbcf0db7ee
Refactor code a bit and avoid creating unnecessary entries in the string
...
map.
llvm-svn: 116579
2010-10-15 15:39:06 +00:00
3b1db392fc
Remove unused ARMISD::AND selection DAG node.
...
llvm-svn: 116566
2010-10-15 04:34:40 +00:00
59351844e1
ARM instructions that are both predicated and set the condition codes
...
have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
llvm-svn: 116563
2010-10-15 03:23:44 +00:00
118c4238ff
Encoding info for extension instructions.
...
llvm-svn: 116560
2010-10-15 02:29:58 +00:00
6f717ec1d7
Grammar.
...
llvm-svn: 116557
2010-10-15 01:44:59 +00:00
6db2837f7f
Don't pass --export-dynamic if TOOL_NO_EXPORTS is set.
...
llvm-svn: 116550
2010-10-15 00:58:12 +00:00
3f1f7b67e3
Eliminate curli from SplitEditor. Use the LiveRangeEdit reference instead.
...
llvm-svn: 116547
2010-10-15 00:34:01 +00:00
0f3e98ce2e
Move stack slot assignments into LiveRangeEdit.
...
All registers created during splitting or spilling are assigned to the same
stack slot as the parent register.
When splitting or rematting, we may not spill at all. In that case the stack
slot is still assigned, but it will be dead.
llvm-svn: 116546
2010-10-15 00:16:55 +00:00
72911e49fa
Create a new LiveRangeEdit class to keep track of the new registers created when
...
splitting or spillling, and to help with rematerialization.
Use LiveRangeEdit in InlineSpiller and SplitKit. This will eventually make it
possible to share remat code between InlineSpiller and SplitKit.
llvm-svn: 116543
2010-10-14 23:49:52 +00:00
0b5c743811
Simplify test file a bit.
...
llvm-svn: 116540
2010-10-14 23:32:44 +00:00
89efff3763
Add testcase for RRX and ASRS (which effectively tests MOVs, since those
...
are just forms of that instruction).
llvm-svn: 116538
2010-10-14 23:29:18 +00:00
19c6cb978b
Add missing Rd encoding for MOVs instruction.
...
llvm-svn: 116537
2010-10-14 23:28:31 +00:00
8b6a9c1574
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
...
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
llvm-svn: 116534
2010-10-14 22:57:13 +00:00
31a01ee3cb
Tolerate a null parent pointer.
...
llvm-svn: 116533
2010-10-14 22:55:57 +00:00
49f72b635e
Added basic support for CPack.
...
llvm-svn: 116516
2010-10-14 21:11:51 +00:00
062749cb25
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
...
pseudonym.
llvm-svn: 116512
2010-10-14 20:43:44 +00:00
a3037c3abd
Always use binary mode for output stream. This is important to prevent unwanted end of line conversion on Windows. Should not affect Unix where O_BINARY is not defined. This fix /clang/test/lexer/preamble.c XFAIL on WIN32.
...
llvm-svn: 116509
2010-10-14 20:30:58 +00:00
eafcb27ded
MOVi16 and MOVT ARM mode encodings.
...
llvm-svn: 116498
2010-10-14 18:54:27 +00:00
f11318018a
Only split around a loop if the live range has uses outside the loop periphery.
...
Before we would also split around a loop if any peripheral block had multiple
uses. This could cause repeated splitting when splitting a different live range
would insert uses into the periphery.
Now -spiller=inline passes the nightly test suite again.
llvm-svn: 116494
2010-10-14 18:26:45 +00:00
afb95571d0
Try again at implementing thread-safe lazy pass initialization, without depending on static local initialization
...
being threadsafe AND ensuring that initialization is complete by the time the initializeFooPass method returns.
llvm-svn: 116492
2010-10-14 17:59:03 +00:00
a1cc6ec3fb
Revert r116489. It included some changes I didn't intend to commit, and broke the buildbots.
...
llvm-svn: 116491
2010-10-14 17:36:50 +00:00
d65924f4a0
Apparently MSVC doesn't support thread-safe static local initialization. Roll our own solution instead.
...
llvm-svn: 116489
2010-10-14 17:26:06 +00:00
8229153629
Simplify encoding information and add 'dst' operand info for TAILJMP.
...
llvm-svn: 116488
2010-10-14 17:24:28 +00:00
bee6e9f8e0
Remove some code duplication.
...
llvm-svn: 116484
2010-10-14 16:34:44 +00:00
5816ccd4b5
Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It
...
creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON
llvm-svn: 116480
2010-10-14 15:54:46 +00:00
ffe32e1137
When building shared libraries, link to required system libraries.
...
PR 8375
llvm-svn: 116479
2010-10-14 15:54:41 +00:00
793d141b7d
Comments.
...
llvm-svn: 116476
2010-10-14 13:43:20 +00:00
11c9edb295
Forward -march correctly.
...
Also includes some cosmetic changes.
llvm-svn: 116475
2010-10-14 11:22:06 +00:00
21d0c173f4
Handle more complex GEP based loads and add a few TODOs to deal with
...
GEP + alloca.
llvm-svn: 116474
2010-10-14 09:29:41 +00:00
6f52f8a87d
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
...
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
llvm-svn: 116471
2010-10-14 02:33:26 +00:00
0441c6cba0
Add encoding for 'fmstat'.
...
llvm-svn: 116466
2010-10-14 01:19:34 +00:00
d62719c3fa
Register pressure and instruction latency aware machine LICM. Work in progress.
...
llvm-svn: 116465
2010-10-14 01:16:09 +00:00
0825f3e441
- Add encodings for multiply add/subtract instructions in all their glory.
...
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
llvm-svn: 116464
2010-10-14 01:02:08 +00:00
b9681ad442
fix a bug I introduced, no idea how this didn't repro right.
...
llvm-svn: 116462
2010-10-14 00:30:00 +00:00
c7bd5740eb
hack to unbreak buildbots
...
llvm-svn: 116461
2010-10-14 00:26:10 +00:00
1f2b4bdb22
Regenerate. No functional change, just cleanup.
...
llvm-svn: 116459
2010-10-14 00:15:18 +00:00
dba47755a0
Teach PerfectShuffle to not generate files with embedded tab characters.
...
llvm-svn: 116458
2010-10-14 00:12:49 +00:00
698661c741
add uadd_ov/usub_ov to apint, consolidate constant folding
...
logic to use the new APInt methods. Among other things this
implements rdar://8501501 - llvm.smul.with.overflow.i32 should constant fold
which comes from "clang -ftrapv", originally brought to my attention from PR8221.
llvm-svn: 116457
2010-10-14 00:05:07 +00:00
edf5e640fa
missed a line :(
...
llvm-svn: 116456
2010-10-13 23:57:00 +00:00
2c819b0358
constify these methods.
...
llvm-svn: 116455
2010-10-13 23:54:10 +00:00
d100ed858e
Detabify and clean up 80 column violations.
...
llvm-svn: 116454
2010-10-13 23:47:11 +00:00
79bdd88fa4
add a few operations for signed operations that also
...
return an overflow flag.
llvm-svn: 116452
2010-10-13 23:46:33 +00:00
340cd5174b
A few 80 column fixes.
...
llvm-svn: 116451
2010-10-13 23:34:31 +00:00
b9386558a7
trailing whitespace
...
llvm-svn: 116450
2010-10-13 23:12:26 +00:00
348013f829
Add a FIXME.
...
llvm-svn: 116449
2010-10-13 22:55:33 +00:00
0708e74a95
Add operand encoding bits for SMC and SVC in ARM mode.
...
llvm-svn: 116447
2010-10-13 22:38:23 +00:00
16db3287c0
More encoding cleanup. Also add register Rd operands for indirect branches.
...
llvm-svn: 116444
2010-10-13 22:09:34 +00:00
071cee0c81
CallGraphSCC passes implicity require CallGraph analysis.
...
llvm-svn: 116443
2010-10-13 22:00:45 +00:00
6bc4f49f89
Conversely, Analysis-implementations do NOT need to initialize the AnalysisGroup. It will only matter when
...
someone tries to require that AG, in which case it is the requester's responsibility to initialize it.
llvm-svn: 116442
2010-10-13 21:55:07 +00:00
c266a36625
Analysis groups need to initialize their default implementations.
...
llvm-svn: 116441
2010-10-13 21:49:58 +00:00
2a4d99ab62
Simplify some ARM encoding information.
...
llvm-svn: 116440
2010-10-13 21:48:54 +00:00
ef83e21b57
Update comment.
...
llvm-svn: 116438
2010-10-13 21:41:51 +00:00
9874b7de58
Add a FIXME. The ADR instruction is a bit odd.
...
llvm-svn: 116437
2010-10-13 21:32:30 +00:00
7e72ec6626
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
...
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
f106ecfa59
Add MC encodings for VCVT* instrunctions.
...
llvm-svn: 116431
2010-10-13 20:58:46 +00:00
fb07ef19cc
Add a FIXME.
...
llvm-svn: 116428
2010-10-13 20:38:04 +00:00
efc066829b
Make a few more bits of some simple instructions explicit. nop, yield, wfe,
...
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.
llvm-svn: 116427
2010-10-13 20:30:55 +00:00
d8d468f721
Take advantage of C++'s thread-safe static local initialization to simplify thread-safe pass initialization.
...
llvm-svn: 116426
2010-10-13 20:24:34 +00:00
d6c1f37f86
GetTargetTriple.cmake: detect MinGW 64 bits.
...
llvm-svn: 116424
2010-10-13 20:15:08 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
142e3cbb26
Fix encoding for compares. No Rd register.
...
llvm-svn: 116414
2010-10-13 18:05:25 +00:00
651dc7c9e9
Add ARM mode operand encoding information for ADDE/SUBE instructions.
...
llvm-svn: 116412
2010-10-13 18:00:52 +00:00
2216af3fa8
Fix another case where we were preferring instructions with large
...
immediates instead of 8 bits ones.
llvm-svn: 116410
2010-10-13 17:14:25 +00:00
c133c6ee1a
Remove noisy semicolon.
...
llvm-svn: 116407
2010-10-13 15:55:12 +00:00
8ea9b0eb32
Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
...
8 bit constants can be used.
llvm-svn: 116403
2010-10-13 13:31:20 +00:00
4b0986b6c1
Add Region::isTopLevelRegion().
...
llvm-svn: 116402
2010-10-13 11:02:44 +00:00
dd0821e7ff
Start handling more global variables.
...
llvm-svn: 116401
2010-10-13 09:11:46 +00:00
4c71c117d1
RegionInfo: Fix trivial error that slipped in last minute.
...
llvm-svn: 116400
2010-10-13 08:00:53 +00:00
fe92a9384e
RegionInfo: Update RegionInfo after a BB was split.
...
llvm-svn: 116398
2010-10-13 05:54:13 +00:00
a8677226ab
RegioInfo: Add getExpandedRegion().
...
getExpandedRegion() enables us to create non canonical regions. Those regions
can be used to define the largerst region, that fullfills a certain property.
llvm-svn: 116397
2010-10-13 05:54:11 +00:00
648594c920
RegionInfo: Allow to update exit and entry of a region.
...
llvm-svn: 116396
2010-10-13 05:54:10 +00:00
bf984fd78e
RegionInfo: Enhance addSubregion.
...
llvm-svn: 116395
2010-10-13 05:54:09 +00:00
8352ce5f8d
RegionInfo: Allow to set the parent region of a basic block.
...
llvm-svn: 116394
2010-10-13 05:54:07 +00:00
c2240adcc7
Fix PR8313 by changing ValueToValueMap use a TrackingVH.
...
llvm-svn: 116390
2010-10-13 02:08:17 +00:00
3912158997
Limit load / store issues (at least until we have a true multi-issue aware scheduler).
...
llvm-svn: 116389
2010-10-13 01:54:21 +00:00
229e38f0fe
Be more consistent in using ValueToValueMapTy.
...
llvm-svn: 116387
2010-10-13 01:36:30 +00:00
6e27b4f530
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
...
just yet.
llvm-svn: 116386
2010-10-13 01:17:33 +00:00
576fd0b110
Add encodings for VCVT instructions.
...
llvm-svn: 116385
2010-10-13 00:56:35 +00:00
8c519c0d4b
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
...
arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
da4ddf0fcf
Add VCMPZ and VABS.
...
llvm-svn: 116383
2010-10-13 00:38:07 +00:00
e910b9d9cd
RegionInfo: Free the RegionNodes in cache.
...
Contributed by: ether
llvm-svn: 116380
2010-10-13 00:07:59 +00:00
f9ca535495
Refactor VCMP instructions.
...
llvm-svn: 116379
2010-10-13 00:04:29 +00:00
efd5369749
Add the rest of the ARM so_reg encoding options (register shifted register)
...
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.
llvm-svn: 116377
2010-10-12 23:53:58 +00:00
a237bdbe52
FileCheckize this in a hope to quiet a valgrind warning on grep.
...
llvm-svn: 116376
2010-10-12 23:47:58 +00:00
7dd8c0b991
Add encodings for VNMUL[SD].
...
llvm-svn: 116375
2010-10-12 23:47:37 +00:00
a06aee826c
Add encodings for VDIV and VMUL.
...
llvm-svn: 116370
2010-10-12 23:22:27 +00:00
d565b44a98
Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.
...
llvm-svn: 116368
2010-10-12 23:19:28 +00:00
12e493ace4
Move the ARM so_imm encoding into a custom operand encoder and remove the
...
explicit handling of the instructions referencing it from the MC code
emitter.
llvm-svn: 116367
2010-10-12 23:18:08 +00:00
d5f8c3350d
Be nitpicky and line up the comments.
...
llvm-svn: 116365
2010-10-12 23:14:03 +00:00
42200bcaea
Refactor some of the encoding logic into a base class. This keeps us from having
...
to add 10+ lines to every instruction.
It may turn out that we can move this base class into it's parent class.
llvm-svn: 116362
2010-10-12 23:06:54 +00:00
d9d31dafda
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
...
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
llvm-svn: 116360
2010-10-12 23:00:24 +00:00
646a506724
Add encoding for VSUB and VCMP.
...
Fear not! I'm going to try a refactoring right now. :)
llvm-svn: 116359
2010-10-12 22:55:35 +00:00
9513a7e87f
Don't need to specify calling convention. Add 'readnone' to functions.
...
llvm-svn: 116354
2010-10-12 22:24:10 +00:00
51a12eb11d
Allow targets to optionally specify custom binary encoder functions for
...
operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.
llvm-svn: 116353
2010-10-12 22:21:57 +00:00
ac6cd00706
Encoding for VADDD. Plus a test for the VFP instructions.
...
llvm-svn: 116348
2010-10-12 22:08:41 +00:00
98c29d732d
Split out the "size" field from the encoding. The newer documentation has it as
...
a separate bit in the coding.
llvm-svn: 116347
2010-10-12 22:03:19 +00:00
22e051eef0
Fix thinko in arm fast isel alloca rewrite.
...
llvm-svn: 116339
2010-10-12 21:23:43 +00:00
576640f0e3
Encoding for ARM-mode VADD.F32 instruction.
...
llvm-svn: 116338
2010-10-12 21:22:40 +00:00
8ac477ffb5
Begin adding static dependence information to passes, which will allow us to
...
perform initialization without static constructors AND without explicit initialization
by the client. For the moment, passes are required to initialize both their
(potential) dependencies and any passes they preserve. I hope to be able to relax
the latter requirement in the future.
llvm-svn: 116334
2010-10-12 19:48:12 +00:00
604e142844
Combine these together - should probably have some text associated
...
that says what why what we just asserted is wrong.
llvm-svn: 116333
2010-10-12 19:44:17 +00:00
65c1c43c13
KillTheDoctor: Fix VS2008 build.
...
llvm-svn: 116330
2010-10-12 19:27:44 +00:00
eb7b91d417
Mark variable 'NoImplicitFloatOps' used only in an assert as used.
...
llvm-svn: 116323
2010-10-12 18:18:03 +00:00
503142624c
Comment grammar tweakage.
...
llvm-svn: 116322
2010-10-12 18:11:41 +00:00
0e57a9f7a9
Add MOVi ARM encoding.
...
llvm-svn: 116321
2010-10-12 18:09:12 +00:00
395a898b2b
Initial va_arg support for x86-64. Patch by David Meyer!
...
llvm-svn: 116319
2010-10-12 18:00:49 +00:00
feeae27ad9
Nuke unused wrapper function.
...
llvm-svn: 116318
2010-10-12 17:53:25 +00:00
aec745326a
Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.
...
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.
The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.
llvm-svn: 116314
2010-10-12 17:15:00 +00:00
6fead930af
Add encoding information for the remainder of the generic arithmetic
...
ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
dd6eb5b5a1
PR8359: The ARM backend may end up allocating registers D16 to D31 when
...
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!
llvm-svn: 116310
2010-10-12 16:22:47 +00:00
7cd5cda6bb
Rework alloca handling so that we can load or store from casted
...
address that we've looked through.
Fixes compilation problems in tramp3d from earlier patch.
llvm-svn: 116296
2010-10-12 05:39:06 +00:00
ef917741e2
Fix the last two commits to configure - configure is a generated file.
...
Made necessary edits to configure.ac and regenerated.
llvm-svn: 116291
2010-10-12 02:42:05 +00:00
db3bcc9910
Handle a wider arrangement of loads.
...
llvm-svn: 116284
2010-10-12 00:43:21 +00:00
a48349f596
Fix spelling error.
...
llvm-svn: 116282
2010-10-12 00:21:05 +00:00
cb85497ddf
Delete a redundant check.
...
llvm-svn: 116280
2010-10-12 00:19:24 +00:00
060d5ba248
More SmallVectorImpls.
...
llvm-svn: 116279
2010-10-12 00:15:27 +00:00
c450d2caa5
Shrink a SmallVector with a known maximum size.
...
llvm-svn: 116278
2010-10-12 00:13:43 +00:00
c8da21b04c
Constify.
...
llvm-svn: 116277
2010-10-12 00:12:29 +00:00
7224bcef8f
Use SmallVectorImpl in a bunch of places.
...
llvm-svn: 116276
2010-10-12 00:11:18 +00:00
c56f5b93c5
Disable warning C4267 for MSVC. Otherwise it generate literally thousands of warnings when targeting x64. The warning occurs because int is 32 bit but size_t is 64 bit on Win64.
...
llvm-svn: 116274
2010-10-12 00:01:36 +00:00
65eb03ed6b
Add a simple testcase for tbaa.
...
llvm-svn: 116272
2010-10-11 23:54:13 +00:00
e790afcbe1
More ARM scheduling itinerary fixes.
...
llvm-svn: 116266
2010-10-11 23:41:41 +00:00
a8d3a7f93d
Support AA chaining.
...
llvm-svn: 116264
2010-10-11 23:39:34 +00:00
844dd0ad00
Fix the pass manager's search order for immutable passes, and make it
...
stop searching when it has found a match.
llvm-svn: 116262
2010-10-11 23:19:01 +00:00
b7c2962d20
MC machine encoding for simple aritmetic instructions that use a shifted
...
register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
109ff296c8
Second set of ARM/MC/ELF changes.
...
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)
llvm-svn: 116257
2010-10-11 23:01:44 +00:00
84117119ff
Clang's #include handling apparently doesn't work for libstdc++'s
...
fenv.h. See PR6907 for details. Work around this in FEnv.h to fix
the seflhost build.
llvm-svn: 116256
2010-10-11 22:30:59 +00:00
b28ce01e34
Unit Tests: Missed this error. MSVC and clang didn't complain.
...
llvm-svn: 116252
2010-10-11 22:04:38 +00:00
94ad008beb
Proper VST scheduling itineraries.
...
llvm-svn: 116251
2010-10-11 22:03:18 +00:00
d42340ecfd
Use a sane mechanism for that assert.
...
llvm-svn: 116249
2010-10-11 22:01:22 +00:00
ded95b79f2
System: Add SwapByteOrder and update Support/MathExtras.h to use it.
...
This time correctly.
llvm-svn: 116247
2010-10-11 21:56:16 +00:00
57feeed92f
Replace FindLiveRangeContaining() with getVNInfoAt() in LiveIntervalAnalysis.
...
This helps hiding the LiveRange class which really should be private.
llvm-svn: 116244
2010-10-11 21:45:03 +00:00
e61de930bc
The assert() should reference to machine instr operand number, too.
...
llvm-svn: 116243
2010-10-11 21:41:31 +00:00
43e92d1162
Revert "System: Add SwapByteOrder and update Support/MathExtras.h to use it."
...
This reverts commit 116234.
It compiled just fine with MSVC and clang...
llvm-svn: 116242
2010-10-11 21:39:24 +00:00
72b91c1765
We're not going to handle dynamic allocas anywhere else.
...
llvm-svn: 116240
2010-10-11 21:37:35 +00:00
fe2a89683a
Change explicit search Apple specific code to only reference __eprintf on x86.
...
llvm-svn: 116239
2010-10-11 21:34:24 +00:00
11ced671be
Make sure to use the machine instruction operand number. It doesn't always
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map one-to-one with the CodeGenInstruction operand number.
llvm-svn: 116238
2010-10-11 21:31:22 +00:00
8827889d89
Reduce dpendencies for SupportTests.
...
llvm-svn: 116235
2010-10-11 21:22:34 +00:00
ae0c34e127
System: Add SwapByteOrder and update Support/MathExtras.h to use it.
...
llvm-svn: 116234
2010-10-11 21:22:22 +00:00
71ef1af66b
Make sure that the call stack adjustments have default operands. Also
...
leave custom lowerings for later.
Fixes some nightly tests.
llvm-svn: 116232
2010-10-11 21:20:02 +00:00
3e02306fed
PR8297
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llvm-svn: 116223
2010-10-11 21:08:42 +00:00
6c4353ecee
PowerPC varargs functions store live-in registers on the stack. Make sure we use
...
virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.
This fixes PR8357.
llvm-svn: 116222
2010-10-11 20:43:09 +00:00
e2a0b6841a
Found a bug turning this on by default. Disable again for now.
...
llvm-svn: 116220
2010-10-11 20:26:21 +00:00
6002b3b3e1
Remove now non-existent option.
...
llvm-svn: 116219
2010-10-11 20:21:21 +00:00
46cc854e5e
Fix help text.
...
llvm-svn: 116218
2010-10-11 20:15:02 +00:00
5501b7e805
Change flag from Enable to Disable since we're enabled by default.
...
Also don't use fast-isel on non-darwin since it's untested.
llvm-svn: 116217
2010-10-11 20:05:22 +00:00
279362dd5a
Add KillTheDoctor.
...
llvm-svn: 116216
2010-10-11 19:55:38 +00:00
806b139bbc
trailing whitespace cleanup
...
llvm-svn: 116215
2010-10-11 19:38:01 +00:00
e01c9001c9
Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand
...
llvm-svn: 116214
2010-10-11 19:02:04 +00:00
5476a274c8
More binary encoding stuff, taking advantage of the new "by name" operand
...
matching in tblgen to do the predicate operand.
llvm-svn: 116213
2010-10-11 18:51:51 +00:00
2276e87a65
Turn on arm fast isel by default.
...
llvm-svn: 116212
2010-10-11 18:48:18 +00:00
191ad7c473
When figuring out which operands match which encoding fields in an instruction,
...
try to match them by name first. If there is no by-name match, fall back to
assuming they are in order (this was the previous behavior).
llvm-svn: 116211
2010-10-11 18:25:51 +00:00
2f6531eb8c
Properly handle reloading and spilling around partial redefines in
...
LocalRewriter.
This is a bit of a hack that adds an implicit use operand to model the
read-modify-write nature of a partial redef. Uses and defs are rewritten in
separate passes, and a single operand would never be processed twice.
<rdar://problem/8518892>
llvm-svn: 116210
2010-10-11 18:10:36 +00:00
db3bc40ade
remove dead prototype, PR8351
...
llvm-svn: 116209
2010-10-11 17:44:22 +00:00
0f5bfd27a3
MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.
...
llvm-svn: 116201
2010-10-11 11:36:19 +00:00
e1bcb43bb9
Copy and pasteo.
...
llvm-svn: 116198
2010-10-11 08:40:05 +00:00
7ac602bc8e
Whitespace cleanup in ARM fast isel.
...
llvm-svn: 116197
2010-10-11 08:38:55 +00:00
eae1b38550
Add srem libcall support to ARM fast isel.
...
llvm-svn: 116196
2010-10-11 08:37:26 +00:00
e11017c19e
Add i8 sdiv support for ARM fast isel.
...
llvm-svn: 116195
2010-10-11 08:31:54 +00:00
511aa31965
Implement select handling for ARM fast-isel.
...
llvm-svn: 116194
2010-10-11 08:27:59 +00:00
53afec4904
tweak comment.
...
llvm-svn: 116192
2010-10-11 05:48:00 +00:00
1ef5e84c31
Per discussion with Sanjiv, remove the PIC16 target from mainline. When/if
...
it comes back, it will be largely a rewrite, so keeping the old codebase
in tree isn't helping anyone.
llvm-svn: 116190
2010-10-11 05:44:40 +00:00
8dedb62019
X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents.
...
llvm-svn: 116188
2010-10-11 05:29:15 +00:00
00765e5be0
X86: MinGW should always use libgcc on Windows.
...
llvm-svn: 116177
2010-10-10 23:11:06 +00:00
7a573a5e1f
X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).
...
llvm-svn: 116174
2010-10-10 22:04:34 +00:00
bee1f7f5ba
Fix Whitespace.
...
llvm-svn: 116173
2010-10-10 22:04:20 +00:00
f8f7537a77
force a triple, varargs isn't supported with the SVR4 ABI the buildbot tells me.
...
llvm-svn: 116170
2010-10-10 18:59:01 +00:00
eb313a46fc
fix the default va_arg expansion (in the realignment case) to not implicitly
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truncate the stack pointer to 32-bits on a 64-bit machine.
llvm-svn: 116169
2010-10-10 18:36:26 +00:00
d10babfd65
fix the expansion of va_arg instruction on PPC to know the arg
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alignment for PPC32/64, avoiding some masking operations.
llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.
llvm-svn: 116168
2010-10-10 18:34:00 +00:00
f11031a68c
clarify that zero sized vectors are illegal, PR8340
...
llvm-svn: 116167
2010-10-10 18:20:35 +00:00
b8d7efe785
Now using a variant of the existing inlining heuristics to decide whether to create a given specialization of a function in PartialSpecialization. If the total performance bonus across all callsites passing the same constant exceeds the specialization cost, we create the specialization.
...
llvm-svn: 116158
2010-10-09 22:06:36 +00:00
cf263b0cbd
Fix dead link.
...
llvm-svn: 116157
2010-10-09 21:12:29 +00:00
d84bb168cc
Silence compiler warning.
...
llvm-svn: 116156
2010-10-09 16:36:44 +00:00
a6a984bd96
MC-COFF: Fix .bss section size. Fixes PR8335. Patch by NAKAMUTA Takumi!
...
llvm-svn: 116155
2010-10-09 16:04:45 +00:00
b20b08f898
Don't test a removed function.
...
llvm-svn: 116154
2010-10-09 15:53:25 +00:00
9cc3fcc8ec
syntax-highlighting: Fix module asm keyword.
...
llvm-svn: 116152
2010-10-09 15:44:36 +00:00
86bbd71088
MC-COFF: Implement InitSections. Fixes PR8335.
...
llvm-svn: 116151
2010-10-09 15:44:27 +00:00
c8dbdfd4ba
MC-COFF: Add COFFAsmParser. Completes PR8343.
...
llvm-svn: 116150
2010-10-09 11:01:07 +00:00
530ce85b3e
Fix Whitespace.
...
llvm-svn: 116149
2010-10-09 11:00:50 +00:00
be52c62a6d
MC-COFF: Assert on non-coff sections.
...
llvm-svn: 116148
2010-10-09 11:00:37 +00:00
3431778a2b
Add Kate syntax highlighting files.
...
llvm-svn: 116146
2010-10-09 07:11:04 +00:00
d7a404d85f
Add VLD4 scheduling itineraries.
...
llvm-svn: 116143
2010-10-09 04:07:58 +00:00
3d89823102
MC: Move ParseDirectiveELFType into ELFAsmParser. COFF uses .type for something else.
...
llvm-svn: 116142
2010-10-09 03:47:55 +00:00
a762400bed
Finish vld3 and vld4.
...
llvm-svn: 116140
2010-10-09 01:45:34 +00:00
4187f4942e
Complete vld2 instruction itineries.
...
llvm-svn: 116136
2010-10-09 01:26:12 +00:00
1c7fa43e6f
Multiply instructions are issued on pipeline 0. They do not need to reserve pipeline 1.
...
llvm-svn: 116135
2010-10-09 01:15:04 +00:00
05f13e94bf
Correct some load / store instruction itinerary mistakes:
...
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
llvm-svn: 116134
2010-10-09 01:03:04 +00:00
748265b0da
Simplify test and move into a generic "crash" ll file.
...
llvm-svn: 116130
2010-10-09 00:29:04 +00:00
59ebe44049
Check to make sure that the iterator isn't at the beginning of the basic block
...
before decrementing. <rdar://problem/8529919>
llvm-svn: 116126
2010-10-09 00:03:48 +00:00
c951cfe6a0
add jit support for the new psuedo instructions I added for
...
the add/or xform. The JIT isn't mcized yet, boo.
This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.
llvm-svn: 116125
2010-10-08 23:59:27 +00:00
8eeb5013cd
machine a mutable machineinstr down into emitInstruction.
...
llvm-svn: 116124
2010-10-08 23:54:01 +00:00
548587c31c
Fix the store part of this as well. Fixes smg2000.
...
llvm-svn: 116123
2010-10-08 23:52:16 +00:00
959fcc6c63
Rename SplitEditor::rewrite to finish() and break it out into a couple of new
...
functions: computeRemainder and rewrite.
When the remainder breaks up into multiple components, remember to rewrite those
uses as well.
llvm-svn: 116121
2010-10-08 23:42:21 +00:00
df2aae0c5a
Avoid compiler warning: comparison between signed and unsigned integer.
...
llvm-svn: 116119
2010-10-08 23:01:57 +00:00
b1b0ef7d03
Extract method ProcessUses from LocalRewriter::RewriteMBB. Both parent and child
...
are still way too long, but it's a start.
No functional change intended.
llvm-svn: 116116
2010-10-08 22:14:41 +00:00
fc3642b205
Do not check that the bodies of two defs of same linkonce global are the same.
...
Such a check does not make any sense in presense of inlining and other compiler-dependent stuff.
This should fix bunch of warnings on mingw32.
llvm-svn: 116113
2010-10-08 21:50:04 +00:00
c43c930690
Implement a few more binary encoding bits. Still very early stage proof-of-
...
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
llvm-svn: 116112
2010-10-08 21:45:55 +00:00
2a14088b65
Allow << streaming of MCOperand.
...
llvm-svn: 116107
2010-10-08 21:36:13 +00:00
05cae8326d
Classify value numbers into connected components in linear time.
...
llvm-svn: 116105
2010-10-08 21:19:28 +00:00
af8b4871a8
Call InitSections in llc and clang so that the binaries produced by them
...
are easier to diff with those produced by llvm-mc.
llvm-svn: 116095
2010-10-08 19:37:38 +00:00
2fd85d7cd2
Filter out illegal formulae after updating offsets, not before, so that
...
formulae which become illegal as a result of the offset updating don't
escape.
This is for rdar://8529692. No testcase yet, because the given cases
hit use-list ordering differences.
llvm-svn: 116093
2010-10-08 19:33:26 +00:00
d57f9ecd4a
Recommit 116056, now with the missing file...
...
llvm-svn: 116083
2010-10-08 19:24:18 +00:00
4ac0d16c40
Don't waste time unfolding simple loads. The unfolded copy won't be hoisted.
...
llvm-svn: 116081
2010-10-08 18:59:19 +00:00
8c5e7e51bd
Fix operand latency computation in cases where the definition operand is
...
implicit. e.g.
%D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>
%Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...
The real definition indices are 0,1.
llvm-svn: 116080
2010-10-08 18:42:25 +00:00
cc0e18dd4a
CrashRecovery: Fix raise() override to actually send the right signal, *cough*.
...
llvm-svn: 116072
2010-10-08 18:31:34 +00:00
b75d0ca38e
A few 80 column cleanups
...
llvm-svn: 116069
2010-10-08 18:13:57 +00:00
2f0be8f404
trailing whitespace
...
llvm-svn: 116068
2010-10-08 18:09:59 +00:00
b770c00610
Reapply 116059, this time without the fatfingered pasto at the top.
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''const'ify getMachineOpValue() and associated helpers.'
llvm-svn: 116067
2010-10-08 17:45:54 +00:00
00351b7731
Reverting 116059. Bots are unhappy with it.
...
llvm-svn: 116064
2010-10-08 17:28:40 +00:00
cf97db2402
reverting 116056: win64_params.ll may need to be conditionalized?
...
llvm-svn: 116063
2010-10-08 17:22:42 +00:00
dd1c289a6a
Line number 0 indicates there is no source line/file name info available for this construct.
...
llvm-svn: 116061
2010-10-08 17:18:54 +00:00
e2d30cd4b5
'const'ify getMachineOpValue() and associated helpers.
...
llvm-svn: 116059
2010-10-08 16:52:44 +00:00
99463ca8cf
Start separating out code metrics into code size metrics and code performance metrics. Partial Specialization will apply the former to function specializations, and the latter to all callsites that can use a specialization, in order to decide whether to create a specialization
...
llvm-svn: 116057
2010-10-08 13:57:31 +00:00
a07b5c291d
Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.
...
llvm-svn: 116056
2010-10-08 10:31:30 +00:00
056b694de1
Change register allocation order for ARM VFP and NEON registers to put the
...
callee-saved registers at the end of the lists. Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases. Thanks to
Jakob for helping me realize the problem.
Most of this patch is fixing the testsuite. There are quite a few places
where we're checking for specific registers. I changed those to wildcards
in places where that doesn't weaken the tests. The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.
llvm-svn: 116055
2010-10-08 06:15:13 +00:00
3e210eb398
testcase that goes with r116053
...
llvm-svn: 116054
2010-10-08 05:12:30 +00:00
35e6ce479c
fix a subtle bug I introduced in my refactoring, where we stopped preferring
...
the i8 versions of instructions in some cases. In test6, we started
generating:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
## <MCInst #478 CMP64mi32
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
instead of:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
## <MCInst #479 CMP64mi8
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
Fix this and add some comments.
llvm-svn: 116053
2010-10-08 05:12:14 +00:00
8ed76f87cf
rename test
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llvm-svn: 116052
2010-10-08 05:05:06 +00:00
420cf26d99
merge tests
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llvm-svn: 116051
2010-10-08 05:04:58 +00:00
6a8a65cb43
filecheckize.
...
llvm-svn: 116050
2010-10-08 05:02:29 +00:00
dd77477690
reapply: Use the new TB_NOT_REVERSABLE flag instead of special
...
reapply: reimplement the second half of the or/add optimization. We should now
with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.
llvm-svn: 116040
2010-10-08 03:57:25 +00:00
626656a562
reapply the patch reverted in r116033:
...
"Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'"
With a critical fix: the add pseudos clobber EFLAGS.
llvm-svn: 116039
2010-10-08 03:54:52 +00:00
00ee155b25
Fix Formatting.
...
llvm-svn: 116038
2010-10-08 03:17:21 +00:00
8eb636e5de
MC-COFF: Fix Simple and Complex type. Fixes PR8320.
...
llvm-svn: 116037
2010-10-08 03:17:11 +00:00
9367aa0950
Fix Whitespace.
...
llvm-svn: 116036
2010-10-08 03:16:56 +00:00
d4e9c3b43a
Update CMake.
...
llvm-svn: 116034
2010-10-08 02:30:03 +00:00
8f21f9c1fb
Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into
...
'add'", which seems to have broken just about everything.
llvm-svn: 116033
2010-10-08 02:07:32 +00:00
5b2a411c77
Revert "Use the new TB_NOT_REVERSABLE flag instead of special ", which depends
...
on r116007, which I am about to revert.
llvm-svn: 116032
2010-10-08 02:07:29 +00:00
efdf08b5b8
Revert "reimplement the second half of the or/add optimization. We should now",
...
which depends on r116007, which I am about to revert.
llvm-svn: 116031
2010-10-08 02:07:26 +00:00
ba66a81017
Fix -Asserts warning.
...
llvm-svn: 116030
2010-10-08 02:07:22 +00:00
15bc2438d9
Move to thumb2 loads, fixes a problem with incoming registers
...
as thumb1.
Fixes lencod.
llvm-svn: 116027
2010-10-08 01:13:17 +00:00
134f415bf8
reimplement the second half of the or/add optimization. We should now
...
only end up emitting LEA instead of OR. If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.
Add some testcases that we emit "or" in cases where we used to produce
an "add".
llvm-svn: 116026
2010-10-08 01:05:10 +00:00
42a07e8545
Add test file for simple ARM binary encodings with MC
...
llvm-svn: 116024
2010-10-08 00:47:59 +00:00
0bb2f9afa9
Enable binary encoding of some simple instructions.
...
llvm-svn: 116022
2010-10-08 00:39:21 +00:00
a23825a4bb
Try to fix ocaml bindings.
...
llvm-svn: 116021
2010-10-08 00:36:21 +00:00
a7b6d58f45
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
...
llvm-svn: 116018
2010-10-08 00:21:28 +00:00
Bill Wendling