Commit Graph

205336 Commits

Author SHA1 Message Date
Eric Fiselier 5be45129a4 Implement n4169 - Add invoke function template
llvm-svn: 242195
2015-07-14 20:16:15 +00:00
Hans Wennborg 923860d8ca test-release.sh: Remove the InstallDir parameter from configure_llvmCore
After r242187, it's never set.

llvm-svn: 242194
2015-07-14 20:15:15 +00:00
Alexey Samsonov 41bcf0bca2 [Sanitizer] Fix fopencookie() interceptor to work with null hook functions.
llvm-svn: 242193
2015-07-14 20:13:42 +00:00
Krzysztof Parzyszek 2e82883620 Fix Windows build: replace __func__ with LLVM_FUNCTION_NAME
llvm-svn: 242192
2015-07-14 20:11:28 +00:00
Bruno Cardoso Lopes 9e6dea1df8 [MMX] Use the appropriate instructions for GR64 <-> VR64 copies.
MOVSDto64rr and MOV64toSDrr are defined to convert between FR64 (%xmm)
<-> GR64 registers, not VR64 (%mm) <-> GR64. This is wrong.

I found this by inspection and could not find a suitable testcase for it
since (1) we don't handle MMX bitcasts in Peephole optimizer as to
generate COPYs that (2) could be expanded back to the appropriate x86
instruction in ExpandPostRA.

Switch to use the appropriate instructions: MMX_MOVD64from64rr and
MMX_MOVD64to64rr here.

llvm-svn: 242191
2015-07-14 20:09:34 +00:00
David Majnemer 38a50c0a16 [Sema] Emit a better diagnostic when variable redeclarations disagree
We referred to all declaration in definitions in our diagnostic messages
which is can be inaccurate.  Instead, classify the declaration and emit
an appropriate diagnostic for the new declaration and an appropriate
note pointing to the old one.

This fixes PR24116.

llvm-svn: 242190
2015-07-14 20:08:49 +00:00
Marshall Clow f69606b117 Mark LWG2308 as complete; fix link. No code change necessary.
llvm-svn: 242189
2015-07-14 20:07:45 +00:00
Hal Finkel 8acae5276e [PowerPC] Fix the PPCInstrInfo::getInstrLatency implementation
PowerPC uses itineraries to describe processor pipelines (and dispatch-group
restrictions for P7/P8 cores). Unfortunately, the target-independent
implementation of TII.getInstrLatency calls ItinData->getStageLatency, and that
looks for the largest cycle count in the pipeline for any given instruction.
This, however, yields the wrong answer for the PPC itineraries, because we
don't encode the full pipeline. Because the functional units are fully
pipelined, we only model the initial stages (there are no relevant hazards in
the later stages to model), and so the technique employed by getStageLatency
does not really work. Instead, we should take the maximum output operand
latency, and that's what PPCInstrInfo::getInstrLatency now does.

This caused some test-case churn, including two unfortunate side effects.
First, the new arrangement of copies we get from function parameters now
sometimes blocks VSX FMA mutation (a FIXME has been added to the code and the
test cases), and we have one significant test-suite regression:

SingleSource/Benchmarks/BenchmarkGame/spectral-norm
	56.4185% +/- 18.9398%

In this benchmark we have a loop with a vectorized FP divide, and it with the
new scheduling both divides end up in the same dispatch group (which in this
case seems to cause a problem, although why is not exactly clear). The grouping
structure is hard to predict from the bottom of the loop, and there may not be
much we can do to fix this.

Very few other test-suite performance effects were really significant, but
almost all weakly favor this change. However, in light of the issues
highlighted above, I've left the old behavior available via a
command-line flag.

llvm-svn: 242188
2015-07-14 20:02:02 +00:00
Dan Liew 7fa38a5349 Fix several issues with the test-release.sh script
* Use the default install prefix (/usr/local) and use DESTDIR instead to
  set a temporary install location for tarballing. This is the correct
  way to package binary releases (otherwise the temporary install path
  ends up in files in the binary release).
* Remove ``-disable-clang`` option. It did not work correctly
  (tarballing assumed phase 3 was run) and when doing a release
  we should always be doing a three-phased build and test.

Note: Technically we should only be using DESTDIR for the third phase
and use --prefix for the first and second phase because we run the built
clang from phase 1 and 2 (and in general an application's behaviour
may depend on the install prefix). However in the case of clang it
seems to not care what the install prefix was so to simplify the script
we use DESTDIR for all three stages.

llvm-svn: 242187
2015-07-14 19:46:19 +00:00
Krzysztof Parzyszek 758744706a [Hexagon] Generate instructions for operations on predicate registers
Convert logical operations on general-purpose registers to the correspon-
ding operations on predicate registers.

llvm-svn: 242186
2015-07-14 19:30:21 +00:00
Keno Fischer aff703a2ca [CodeGen] Force emission of personality directive if explicitly specified
Summary:
Before this change, personality directives were not emitted
if there was no invoke left in the function (of course until
recently this also meant that we couldn't know what
the personality actually was). This patch forces personality directives
to still be emitted, unless it is known to be a noop in the absence of
invokes, or the user explicitly specified `nounwind` (and not
`uwtable`) on the function.

Reviewers: majnemer, rnk

Subscribers: rnk, llvm-commits

Differential Revision: http://reviews.llvm.org/D10884

llvm-svn: 242185
2015-07-14 19:22:51 +00:00
Jason Molenda fea7765219 Add comment explaning sanity check on packet size in the packet decompression method.
llvm-svn: 242184
2015-07-14 19:19:07 +00:00
Oleksiy Vyalov a3f245fff0 Use target.exec-search-paths setting when resolving executable path for remote target.
http://reviews.llvm.org/D11163

llvm-svn: 242183
2015-07-14 18:59:32 +00:00
Oleksiy Vyalov df62ed3f8b Fix temp port file path generation in lldb-platform.
http://reviews.llvm.org/D11152

llvm-svn: 242182
2015-07-14 18:54:52 +00:00
Artem Belevich b73313de20 Run cuda options test only with specific target.
For now it's only x86_64-linux-gnu.

llvm-svn: 242181
2015-07-14 18:49:17 +00:00
Richard Smith 3b6374133c [modules] Avoid repeatedly hashing the same name when looking it up in multiple module files.
llvm-svn: 242180
2015-07-14 18:42:41 +00:00
Richard Smith 86a6f56c82 Add support for on-disk hash table lookup with a known hash, for situations where the same key will be looked up in multiple tables.
llvm-svn: 242179
2015-07-14 18:40:59 +00:00
Yaron Keren 52511aa3c2 Teach config.guess that MSYS exists.
We might not want to upgrade config.guess to the current
version due to the license change from GPL2 to GPL3.

llvm-svn: 242178
2015-07-14 18:33:55 +00:00
Matt Arsenault 24692118ba AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
This can be done only with moves which theoretically
will optimize better later.

Although this transform increases the instruction count,
it should be code size / cycle count neutral in the worst
VALU case. It also seems to slightly improve a couple
of testcases due to other DAG combines this exposes.

This is probably slightly worse for the SALU case, so
it might be better to handle this during moveToVALU,
although then you lose some simplifications like
the load width reducing in the simple testcase.

llvm-svn: 242177
2015-07-14 18:20:33 +00:00
Reid Kleckner 5c6efed3f5 [clang-cl] Disable C++ exceptions a different way
Rather than making -fexceptions a core option that enables C++ EH in
clang-cl, users can use the '-Xclang -fexceptions -Xclang
-fcxx-exceptions' flag set. We weren't going to expose -fexceptions in
clang-cl in the long run, so this way we don't add and then remove a
flag.

llvm-svn: 242176
2015-07-14 18:16:48 +00:00
Sunil Srivastava 780e50187b Fixed 22941: Integer template parameter as immediate 'I' expectes an integer constant
Basically fixed premature testing of integer constraints during template parsing
Reviewed at http://reviews.llvm.org/D10452

llvm-svn: 242175
2015-07-14 18:08:50 +00:00
Matt Arsenault 84db5d97b0 AMDGPU/SI: Fix read2 merging into a super register.
If the read2 produced was supposed to be writing into a
super register, it would use the wrong subregister indices.
Fix this by inserting copies, so we only ever write to a vreg_64.
Run the register coalescer again to clean this up, although this
isn't ideal and often does result in an extra move.

Also remove the assert that offset1 > offset0.

There isn't a real reason to not allow this other than a minor
convenience in the compiler, and it doesn't seem worth the effort
of avoiding it.

llvm-svn: 242174
2015-07-14 17:57:36 +00:00
Matthias Braun 9912bb817c MachineRegisterInfo: Remove UsedPhysReg infrastructure
We have a detailed def/use lists for every physical register in
MachineRegisterInfo anyway, so there is little use in maintaining an
additional bitset of which ones are used.

Removing it frees us from extra book keeping. This simplifies
VirtRegMap.

Differential Revision: http://reviews.llvm.org/D10911

llvm-svn: 242173
2015-07-14 17:52:07 +00:00
Eric Fiselier 092c475e25 Fix PR24114 - std::atomic for non-Clang is not a literal type
Add _LIBCPP_CONSTEXPR to the implementation of __gcc_atomic_t.

llvm-svn: 242172
2015-07-14 17:50:27 +00:00
Nemanja Ivanovic 6c363ed67a Add missing builtins to altivec.h for ABI compliance (vol. 4)
This patch corresponds to review:
http://reviews.llvm.org/D11184

A number of new interfaces for altivec.h (as mandated by the ABI):
vector float vec_cpsgn(vector float, vector float)
vector double vec_cpsgn(vector double, vector double)
vector double vec_or(vector bool long long, vector double)
vector double vec_or(vector double, vector bool long long)
vector double vec_re(vector double)
vector signed char vec_cntlz(vector signed char)
vector unsigned char vec_cntlz(vector unsigned char)
vector short vec_cntlz(vector short)
vector unsigned short vec_cntlz(vector unsigned short)
vector int vec_cntlz(vector int)
vector unsigned int vec_cntlz(vector unsigned int)
vector signed long long vec_cntlz(vector signed long long)
vector unsigned long long vec_cntlz(vector unsigned long long)
vector signed char vec_nand(vector bool signed char, vector signed char)
vector signed char vec_nand(vector signed char, vector bool signed char)
vector signed char vec_nand(vector signed char, vector signed char)
vector unsigned char vec_nand(vector bool unsigned char, vector unsigned char)
vector unsigned char vec_nand(vector unsigned char, vector bool unsigned char)
vector unsigned char vec_nand(vector unsigned char, vector unsigned char)
vector short vec_nand(vector bool short, vector short)
vector short vec_nand(vector short, vector bool short)
vector short vec_nand(vector short, vector short)
vector unsigned short vec_nand(vector bool unsigned short, vector unsigned short)
vector unsigned short vec_nand(vector unsigned short, vector bool unsigned short)
vector unsigned short vec_nand(vector unsigned short, vector unsigned short)
vector int vec_nand(vector bool int, vector int)
vector int vec_nand(vector int, vector bool int)
vector int vec_nand(vector int, vector int)
vector unsigned int vec_nand(vector bool unsigned int, vector unsigned int)
vector unsigned int vec_nand(vector unsigned int, vector bool unsigned int)
vector unsigned int vec_nand(vector unsigned int, vector unsigned int)
vector signed long long vec_nand(vector bool long long, vector signed long long)
vector signed long long vec_nand(vector signed long long, vector bool long long)
vector signed long long vec_nand(vector signed long long, vector signed long long)
vector unsigned long long vec_nand(vector bool long long, vector unsigned long long)
vector unsigned long long vec_nand(vector unsigned long long, vector bool long long)
vector unsigned long long vec_nand(vector unsigned long long, vector unsigned long long)
vector signed char vec_orc(vector bool signed char, vector signed char)
vector signed char vec_orc(vector signed char, vector bool signed char)
vector signed char vec_orc(vector signed char, vector signed char)
vector unsigned char vec_orc(vector bool unsigned char, vector unsigned char)
vector unsigned char vec_orc(vector unsigned char, vector bool unsigned char)
vector unsigned char vec_orc(vector unsigned char, vector unsigned char)
vector short vec_orc(vector bool short, vector short)
vector short vec_orc(vector short, vector bool short)
vector short vec_orc(vector short, vector short)
vector unsigned short vec_orc(vector bool unsigned short, vector unsigned short)
vector unsigned short vec_orc(vector unsigned short, vector bool unsigned short)
vector unsigned short vec_orc(vector unsigned short, vector unsigned short)
vector int vec_orc(vector bool int, vector int)
vector int vec_orc(vector int, vector bool int)
vector int vec_orc(vector int, vector int)
vector unsigned int vec_orc(vector bool unsigned int, vector unsigned int)
vector unsigned int vec_orc(vector unsigned int, vector bool unsigned int)
vector unsigned int vec_orc(vector unsigned int, vector unsigned int)
vector signed long long vec_orc(vector bool long long, vector signed long long)
vector signed long long vec_orc(vector signed long long, vector bool long long)
vector signed long long vec_orc(vector signed long long, vector signed long long)
vector unsigned long long vec_orc(vector bool long long, vector unsigned long long)
vector unsigned long long vec_orc(vector unsigned long long, vector bool long long)
vector unsigned long long vec_orc(vector unsigned long long, vector unsigned long long)
vector signed char vec_div(vector signed char, vector signed char)
vector unsigned char vec_div(vector unsigned char, vector unsigned char)
vector signed short vec_div(vector signed short, vector signed short)
vector unsigned short vec_div(vector unsigned short, vector unsigned short)
vector signed int vec_div(vector signed int, vector signed int)
vector unsigned int vec_div(vector unsigned int, vector unsigned int)
vector signed long long vec_div(vector signed long long, vector signed long long)
vector unsigned long long vec_div(vector unsigned long long, vector unsigned long long)
vector unsigned char vec_mul(vector unsigned char, vector unsigned char)
vector unsigned int vec_mul(vector unsigned int, vector unsigned int)
vector unsigned long long vec_mul(vector unsigned long long, vector unsigned long long)
vector unsigned short vec_mul(vector unsigned short, vector unsigned short)
vector signed char vec_mul(vector signed char, vector signed char)
vector signed int vec_mul(vector signed int, vector signed int)
vector signed long long vec_mul(vector signed long long, vector signed long long)
vector signed short vec_mul(vector signed short, vector signed short)
vector signed long long vec_mergeh(vector signed long long, vector signed long long)
vector signed long long vec_mergeh(vector signed long long, vector bool long long)
vector signed long long vec_mergeh(vector bool long long, vector signed long long)
vector unsigned long long vec_mergeh(vector unsigned long long, vector unsigned long long)
vector unsigned long long vec_mergeh(vector unsigned long long, vector bool long long)
vector unsigned long long vec_mergeh(vector bool long long, vector unsigned long long)
vector double vec_mergeh(vector double, vector double)
vector double vec_mergeh(vector double, vector bool long long)
vector double vec_mergeh(vector bool long long, vector double)
vector signed long long vec_mergel(vector signed long long, vector signed long long)
vector signed long long vec_mergel(vector signed long long, vector bool long long)
vector signed long long vec_mergel(vector bool long long, vector signed long long)
vector unsigned long long vec_mergel(vector unsigned long long, vector unsigned long long)
vector unsigned long long vec_mergel(vector unsigned long long, vector bool long long)
vector unsigned long long vec_mergel(vector bool long long, vector unsigned long long)
vector double vec_mergel(vector double, vector double)
vector double vec_mergel(vector double, vector bool long long)
vector double vec_mergel(vector bool long long, vector double)
vector signed int vec_pack(vector signed long long, vector signed long long)
vector unsigned int vec_pack(vector unsigned long long, vector unsigned long long)
vector bool int vec_pack(vector bool long long, vector bool long long)

llvm-svn: 242171
2015-07-14 17:50:27 +00:00
David Blaikie 9f8ff9c473 Avoid MSVC-incompatible use of init list.
llvm-svn: 242170
2015-07-14 17:40:53 +00:00
Matthias Braun 953393a72c RAGreedy: Keep track of allocated PhysRegs internally
Do not use MachineRegisterInfo::setPhysRegUsed()/isPhysRegUsed()
anymore. This bitset changes function-global state and is set by the
VirtRegRewriter anyway.
Simply use a bitvector private to RAGreedy.

Differential Revision: http://reviews.llvm.org/D10910

llvm-svn: 242169
2015-07-14 17:38:17 +00:00
David Blaikie 4ba525b727 Rely on default zero-arg value for IRBuilder::CreateCall calls to zero-arg functions
Patch by servuswiegehtz at yahoo.de

llvm-svn: 242168
2015-07-14 17:27:39 +00:00
Nemanja Ivanovic 984a3613b3 Add missing builtins to the PPC back end for ABI compliance (vol. 4)
This patch corresponds to review:
http://reviews.llvm.org/D11183

Back end portion of the fourth round of additions to altivec.h.

llvm-svn: 242167
2015-07-14 17:25:20 +00:00
Tim Northover feabe2e21e ARM: add at least one real test for r242123.
The ones committed were orthogonal to the change and would have passed before
that revision. What it *did* do was prevent an assertion failure when
generating object files.

llvm-svn: 242166
2015-07-14 17:23:55 +00:00
Matthias Braun 0256486532 PrologEpilogInserter: Rewrite API to determine callee save regsiters.
This changes TargetFrameLowering::processFunctionBeforeCalleeSavedScan():

- Rename the function to determineCalleeSaves()
- Pass a bitset of callee saved registers by reference, thus avoiding
  the function-global PhysRegUsed bitset in MachineRegisterInfo.
- Without PhysRegUsed the implementation is fine tuned to not save
  physcial registers which are only read but never modified.

Related to rdar://21539507

Differential Revision: http://reviews.llvm.org/D10909

llvm-svn: 242165
2015-07-14 17:17:13 +00:00
Tim Northover c962d4f28b AArch64: add rev64 alias for 64-bit rev instruction.
It could be useful to assembly programmers and makes the permitted variants a
little more uniform.

llvm-svn: 242164
2015-07-14 17:07:29 +00:00
Krzysztof Parzyszek a0ecf07c0b [Hexagon] Generate "extract" instructions more aggressively
Generate extract instructions (via intrinsics) before the DAG combiner
folds shifts into unrecognizable forms.

llvm-svn: 242163
2015-07-14 17:07:24 +00:00
Rafael Espindola e549b8c259 llvm-ar: Don't try to extract from thin archives.
This matches the gnu ar behavior.

llvm-svn: 242162
2015-07-14 16:55:13 +00:00
Hans Wennborg b27f249601 AST Matchers: pass ast_type_traits::DynTypedNode by const-ref
(Broken out from http://reviews.llvm.org/D11168)

llvm-svn: 242161
2015-07-14 16:50:14 +00:00
Hans Wennborg 61f9efe73b ARMAsmParser: Take MCInst param by const-ref
(Broken out from http://reviews.llvm.org/D11167)

llvm-svn: 242160
2015-07-14 16:39:01 +00:00
David Blaikie c28708bcb0 Add default value for Args parameter of IRBuilder::CreateCall
Convenient for calls to zero-argument functions.

Patch by servuswiegehtz at yahoo.de

llvm-svn: 242159
2015-07-14 16:38:30 +00:00
Rafael Espindola 4ae784396c Sleep for 2.1 seconds to see if that makes the test stable on windows.
Might fix pr24106.

llvm-svn: 242158
2015-07-14 16:34:23 +00:00
Hans Wennborg a6a15b8f2e Allocate the IntervalMap in ELF.h on the heap to work around MSVC alignment bug (PR24113)
llvm-svn: 242157
2015-07-14 16:27:16 +00:00
Rafael Espindola c3eec458ab llvm-ar: print an error when the requested member is not found.
llvm-svn: 242156
2015-07-14 16:02:40 +00:00
Jonathan Peyton 228d149c19 Rename OMPT placeholder type names to be in the OMPT name space
r242052 changed the name of OMPT placeholder functions to move them from
the omp_ name space to the ompt_ name space. This patch moves the names of the
types of these functions into the OMPT name space as well.

Patch by John Mellor-Crummey

Differential Revision: http://reviews.llvm.org/D11171

llvm-svn: 242155
2015-07-14 15:42:03 +00:00
Benjamin Kramer 4a93caf4cf Pull trivial SanitizerSet methods into the header.
Inlining them is always preferable to a call. NFC.

llvm-svn: 242154
2015-07-14 15:34:19 +00:00
Rafael Espindola e098bd6819 Use a range loop. NFC.
llvm-svn: 242153
2015-07-14 15:22:42 +00:00
JF Bastien 2a39d3a38d Revert "Fix `llvm-config` to emit the linker flag for the combined shared object built by autoconfig/make instead of the individual components."
This reverts commit 01446706b4c0a86bb64768f307079cab5c514aa3.

Causes breakage, seems to be related to 'svn' in the file's name:

  CC=gcc CXX=g++ \
  ../llvm/configure \
    --prefix=/usr \
    --sysconfdir=/etc \
    --enable-shared \
    --enable-libffi \
    --enable-targets=all \
    --disable-assertions \
    --with-python=/usr/bin/python2 \
    --enable-optimized

  make REQUIRES_RTTI=1 ENABLE_PIC=1

results:
llvm[2]: Linking Release unit test Support (without symbols)
llvm[2]: ======= Finished Linking Release Unit test Support (without symbols)
make[3]: Entering directory '/build/llvm-svn/src/build/bindings/ocaml/llvm'
make[3]: *** No rule to make target '/build/llvm-
svn/src/build/Release/lib/ocaml/libLLVM-3.7.0svn.so', needed by 'build-
deplibs'.  Stop.
make[3]: *** Waiting for unfinished jobs....
llvm[3]: Compiling llvm_ocaml.c for Release build
make[3]: Leaving directory '/build/llvm-svn/src/build/bindings/ocaml/llvm'
/build/llvm-svn/src/llvm/Makefile.rules:880: recipe for target 'all' failed
/build/llvm-svn/src/llvm/Makefile.rules:965: recipe for target 'all' failed

Differential Revision: http://reviews.llvm.org/D10716

llvm-svn: 242152
2015-07-14 15:10:34 +00:00
Rafael Espindola bcb440fb1f Rename a test. NFC.
llvm-svn: 242151
2015-07-14 15:06:18 +00:00
Yaron Keren 88e69e4434 Support mingw-w64 toolchain on openSUSE and likely other Linuxes
Thanks to Ismail Donmez for testing and to Joerg Sonnenbergerþ for his comments.

llvm-svn: 242150
2015-07-14 15:02:09 +00:00
Marshall Clow 71ff7c3f0f Move bits from N4258. Mark vector's move-constructor unconditionally noexcept in C++1z
llvm-svn: 242148
2015-07-14 14:46:32 +00:00
Alexandros Lamprineas a04e6b1853 Caused regressions: compile Release+Asserts failed on clang-native-arm-cortex-a9
Revert "-Added API for retrieving the default FPU of a CPU from TargetParser."

This reverts commit 01199ab0c6ff2d5c4f6b2c05a95ec011e41c4669.

llvm-svn: 242147
2015-07-14 14:34:06 +00:00
Tom Stellard e48fe2a27a AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11061

llvm-svn: 242146
2015-07-14 14:15:03 +00:00
Aaron Ballman a927a86c72 Silencing two MSVC warnings; 'argument' : truncation from 'unsigned int' to 'int16_t' and truncation of constant value. NFC intended.
llvm-svn: 242145
2015-07-14 14:14:00 +00:00