2550ba2a27
Add X86-SSE4 codegen support for vector-select.
...
llvm-svn: 139285
2011-09-08 08:11:19 +00:00
cc2a801f64
lto/addAsmGlobalSymbols: fast path when no module level asm is present.
...
llvm-svn: 139284
2011-09-08 07:38:25 +00:00
8149dd6619
lto/addAsmGlobalSymbols: fail fracefully when the target does not define AsmParser.
...
llvm-svn: 139283
2011-09-08 07:36:39 +00:00
4fe44b4381
Adding myself to test my new commit powers.
...
llvm-svn: 139280
2011-09-08 05:32:49 +00:00
43674ad44d
Fix a use of freed string contents.
...
Speculatively try to fix our windows testers with a patch I found on the internet.
llvm-svn: 139279
2011-09-08 05:25:49 +00:00
61abca6daa
whitespace
...
llvm-svn: 139278
2011-09-08 05:23:14 +00:00
b78ac543c7
A couple minor corrections to r139276.
...
llvm-svn: 139277
2011-09-08 02:37:07 +00:00
3d1b307672
Fix the logic in BasicAliasAnalysis::aliasGEP for comparing GEP's with variable differences so that it actually does something sane. Fixes PR10881.
...
llvm-svn: 139276
2011-09-08 02:23:31 +00:00
3343da5424
Thumb2 assembly parsing and encoding for LDR post-indexed.
...
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
llvm-svn: 139272
2011-09-08 01:01:32 +00:00
c086f689f8
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
...
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
llvm-svn: 139270
2011-09-08 00:39:19 +00:00
f174959286
Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions.
...
llvm-svn: 139268
2011-09-08 00:11:18 +00:00
2392c53e73
Thumb2 assembly parsing and encoding for LDRBT.
...
llvm-svn: 139267
2011-09-07 23:39:14 +00:00
f40ca22cd3
Thumb2 assembly parsing and encoding for LDRB(register).
...
llvm-svn: 139266
2011-09-07 23:17:00 +00:00
e0ebc1c396
Thumb2 assembly parsing and encoding for LDR(register).
...
llvm-svn: 139264
2011-09-07 23:10:15 +00:00
2e63f6eac0
Add two notes for correlated-expression optimizations.
...
llvm-svn: 139263
2011-09-07 22:49:26 +00:00
946e0a4665
Revert r139247 "Cache intermediate results during traceSiblingValue."
...
It broke the self host and clang-x86_64-darwin10-RA.
llvm-svn: 139259
2011-09-07 21:43:52 +00:00
c8e3656b43
Thumb2 assembly parsing and encoding for LDRB(immediate).
...
llvm-svn: 139258
2011-09-07 21:41:25 +00:00
e2d68844bc
Thumb2 assembly parsing and encoding for LDR(literal).
...
Need branch relocation support to distinguish this encoding from the
16-bit Thumb1 encoding w/o the explicit .w suffix. That comes later, though.
llvm-svn: 139257
2011-09-07 21:33:16 +00:00
18d17aa6b7
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
...
llvm-svn: 139256
2011-09-07 21:10:42 +00:00
fed3ab5bc1
Add tests for Thumb2 LDR(immediate) from r139254.
...
llvm-svn: 139255
2011-09-07 21:06:46 +00:00
5bfa8bab06
Thumb2 parsing and encoding for LDR(immediate).
...
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.
llvm-svn: 139254
2011-09-07 20:58:57 +00:00
1c7406767e
Thumb2 parsing and encoding for LDMDB.
...
llvm-svn: 139251
2011-09-07 19:57:53 +00:00
8067df9503
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
...
llvm-svn: 139250
2011-09-07 19:42:28 +00:00
b77d5c1484
Cache intermediate results during traceSiblingValue.
...
In some cases such as interpreters using indirectbr, the CFG can be very
complicated, and live range splitting may be forced to insert a large
number of phi-defs. When that happens, traceSiblingValue can spend a
lot of time zipping around in the CFG looking for defs and reloads.
This patch causes more information to be cached in SibValues, and the
cached values are used to terminate searches early. This speeds up
spilling by 20x in one interpreter test case. For more typical code,
this is just a 10% speedup of spilling.
llvm-svn: 139247
2011-09-07 19:07:31 +00:00
02f2f89a98
Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).
...
This isn't exactly ideal, but it is good enough for the moment.
llvm-svn: 139245
2011-09-07 18:48:32 +00:00
5d5f4862eb
Update test for 139243
...
llvm-svn: 139244
2011-09-07 18:40:06 +00:00
42b5570850
Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix.
...
There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.
llvm-svn: 139243
2011-09-07 18:39:47 +00:00
a31f223af8
Thumb2 parsing and encoding for LDMIA.
...
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.
llvm-svn: 139242
2011-09-07 18:05:34 +00:00
cd5612d3a5
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
...
llvm-svn: 139240
2011-09-07 17:55:19 +00:00
4c493e8050
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
...
llvm-svn: 139237
2011-09-07 17:24:38 +00:00
524c33a27f
When inlining exception handling code into another function, ensure that
...
duplicate tests are eliminated (for example if the two functions both have
a catch clause catching the same type, ensure the redundant one is removed).
Note that it would probably be safe to say that eh.typeid.for is 'const',
but since two calls to it with the same argument can give different results
(but only if the calls are in different functions), it seems more correct to
mark it only 'pure'; this doesn't get in the way of the optimization.
llvm-svn: 139236
2011-09-07 16:44:14 +00:00
4ff93f3bc2
Thumb2 use 'ldm' as default mnemonic.
...
Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).
llvm-svn: 139234
2011-09-07 16:22:42 +00:00
6559656e73
Detect attempt to use segmented stacks on non ELF systems and error
...
(not assert) early.
llvm-svn: 139233
2011-09-07 16:10:57 +00:00
39c6e1d66d
Better diagnostic location information for mnemonic suffices.
...
llvm-svn: 139232
2011-09-07 16:06:04 +00:00
1257042b70
Another forgotten trampoline testcase.
...
llvm-svn: 139230
2011-09-07 10:05:14 +00:00
d7430cea10
Forgot to add this trampoline testcase.
...
llvm-svn: 139229
2011-09-07 09:21:38 +00:00
e978d2f644
Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs failures for atomic laod/store on ARM.
...
(The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.)
llvm-svn: 139221
2011-09-07 02:23:42 +00:00
3d76f312b2
Dependency should be on the output file name, not the dependency file
...
name.
llvm-svn: 139220
2011-09-07 02:12:03 +00:00
9de7a7db26
While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor.
...
llvm-svn: 139208
2011-09-07 00:07:58 +00:00
226c4ed92a
Reenable compact unwind by default. However, also emit the old version of unwind
...
information for older linkers.
llvm-svn: 139206
2011-09-06 23:47:14 +00:00
f4f09f8c26
memset_pattern16 uses a 16 BYTE pattern, not a 16 BIT pattern. Add comments to that effect.
...
llvm-svn: 139205
2011-09-06 23:43:26 +00:00
653cb03191
Teach BasicAA about the aliasing properties of memset_pattern16.
...
Fixes PR10872 and <rdar://problem/10065079>.
llvm-svn: 139204
2011-09-06 23:33:25 +00:00
5b5c953b07
ISB is HasDB, not just HasV7.
...
llvm-svn: 139202
2011-09-06 23:09:19 +00:00
83a6188f18
Thumb2 parsing and encoding for ISB.
...
llvm-svn: 139200
2011-09-06 22:53:27 +00:00
958feffa11
Thumb2 parsing and encoding for EOR.
...
llvm-svn: 139199
2011-09-06 22:44:50 +00:00
ed9399995a
Thumb2 parsing and encoding for DSB.
...
llvm-svn: 139194
2011-09-06 22:19:40 +00:00
e95f46384e
Thumb2 parsing and encoding for DMB.
...
llvm-svn: 139193
2011-09-06 22:14:58 +00:00
474c455060
Disable these tests harder. They're XFAIL'd, but that means they still run, and
...
these tests all infinitely recurse, bringing my system down into swapping hell.
llvm-svn: 139192
2011-09-06 22:08:18 +00:00
c048b905b4
Thumb2 parsing and encoding for DBG.
...
llvm-svn: 139191
2011-09-06 22:06:40 +00:00
565e2f5752
Thumb2 parsing and encoding for CMN and CMP.
...
llvm-svn: 139188
2011-09-06 21:44:58 +00:00
e0aa54bb98
This transform only handles two-operand AddRec's. Prevent it from trying to
...
handle anything more complex. Fixes PR10383 again!
llvm-svn: 139186
2011-09-06 21:42:18 +00:00
fc4b343dda
Add mayLoad/mayStore markings to ARM 64-bit atomic pseudo-instructions.
...
llvm-svn: 139179
2011-09-06 20:53:37 +00:00
70532e289f
Thumb2 parsing and encoding for CLZ.
...
llvm-svn: 139177
2011-09-06 20:44:17 +00:00
803898f119
Thumb2 parsing and encoding for CLREX.
...
llvm-svn: 139172
2011-09-06 20:27:04 +00:00
b041e866b0
Port more encoding tests over to Thumb2 decoding tests.
...
llvm-svn: 139171
2011-09-06 20:26:34 +00:00
1eee7f1242
Add -verify-indvars for imperfect SCEV trip count verification after indvars.
...
llvm-svn: 139169
2011-09-06 20:20:38 +00:00
6952281037
Thumb2 parsing and encoding for CDP/CDP2.
...
llvm-svn: 139168
2011-09-06 20:12:23 +00:00
9d96c94278
Fix comment. Noticed by Duncan.
...
llvm-svn: 139161
2011-09-06 19:29:31 +00:00
f2641e1bc1
Add codegen support for vector select (in the IR this means a select
...
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
llvm-svn: 139159
2011-09-06 19:07:46 +00:00
0b758ed6ba
Fix fall outs from my recent change on how carry bit is modeled during isel.
...
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745
llvm-svn: 139157
2011-09-06 18:52:20 +00:00
c10e52a0c4
Use IRBuilder.
...
llvm-svn: 139156
2011-09-06 18:49:53 +00:00
f471ac3c72
ARM .code directive should always go to the streamer.
...
Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).
llvm-svn: 139155
2011-09-06 18:46:23 +00:00
db5823dc77
Fix style issues and typos found by Duncan.
...
llvm-svn: 139154
2011-09-06 18:43:08 +00:00
9803abb788
As a first step, emit both the compact unwind and CIE/FDEs for a function.
...
llvm-svn: 139152
2011-09-06 18:37:11 +00:00
58704ee442
Try again at r138809 (make DSE more aggressive in removing dead stores at the end of a function), now with less deleting stores before memcpy's.
...
llvm-svn: 139150
2011-09-06 18:14:09 +00:00
50ef7611aa
Atomic pseudos don't use (as in read) CPSR. They clobber it.
...
llvm-svn: 139148
2011-09-06 17:40:35 +00:00
5ea5d7965b
Now, named mdnode llvm.dbg.cu keeps track of all compile units in a module. Update DebugInfoFinder to collect compile units from llvm.dbg.cu.
...
llvm-svn: 139147
2011-09-06 17:40:08 +00:00
a098436b32
Split the init.trampoline intrinsic, which currently combines GCC's
...
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
llvm-svn: 139140
2011-09-06 13:37:06 +00:00
78664db054
Fix typo in comment again.
...
llvm-svn: 139139
2011-09-06 07:02:40 +00:00
237878b7ac
Apparently we compile the code, not the comments. Thanks Eli!
...
llvm-svn: 139138
2011-09-06 06:56:00 +00:00
0af94cc50b
Fix typo in comment.
...
llvm-svn: 139137
2011-09-06 06:46:01 +00:00
702cf1eccc
Nope! I had it right the first time. Revert the operative part of r139135 and
...
add more showing of my work.
llvm-svn: 139136
2011-09-06 06:39:54 +00:00
6f86e001d6
Fix flipped sign. While there, show my math.
...
llvm-svn: 139135
2011-09-06 05:33:18 +00:00
db66b82dd5
No no no, fix typo properly!
...
llvm-svn: 139134
2011-09-06 05:08:09 +00:00
658bdb5133
The logic inside getMulExpr to simplify {a,+,b}*{c,+,d} was wrong, which was
...
visible given a=b=c=d=1, on iteration #1 (the second iteration). Replace it with
correct math. Fixes PR10383!
llvm-svn: 139133
2011-09-06 05:05:14 +00:00
b1438c763a
Revert r139126 due to selfhost failures reported by buildbots.
...
llvm-svn: 139130
2011-09-06 02:43:13 +00:00
c4c43fbb07
Teach SCEV to report a max backedge count in one interesting case in
...
HowFarToZero; the case for a canonical loop.
llvm-svn: 139126
2011-09-05 23:25:16 +00:00
73df7e3830
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
...
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
llvm-svn: 139125
2011-09-05 21:51:43 +00:00
df06b6e069
Update the C++ backend to use the new ArrayRef'ified APIs. Patch by arrowdodger!
...
llvm-svn: 139124
2011-09-05 18:50:59 +00:00
f1a5f57d2f
Fix typo in comment.
...
llvm-svn: 139122
2011-09-05 18:35:03 +00:00
4b79c21ef2
InstSimplify: Don't try to replace an extractvalue/insertvalue pair with the original value if types don't match.
...
Fixes clang selfhost.
llvm-svn: 139120
2011-09-05 18:16:19 +00:00
29192d042e
Delete trivial landing pads that just continue unwinding the caught
...
exception.
llvm-svn: 139117
2011-09-05 12:57:57 +00:00
fd26a954a8
Add some simple insertvalue simplifications, for the purpose of cleaning
...
up do-nothing exception handling code produced by dragonegg.
llvm-svn: 139113
2011-09-05 06:52:48 +00:00
0ca1ad0783
Use canonical forms for the branch probability zero heutistic.
...
- Drop support for X >u 0, it's equivalent to X != 0 and should be canonicalized into the latter.
- Add X < 1 -> unlikely, which is what instcombine canonicalizes X <= 0 into.
- Add X > -1 -> likely, which is what instcombine canonicalizes X >= 0 into.
llvm-svn: 139110
2011-09-04 23:53:04 +00:00
908abc3439
As a (rather delayed) followup to r136738 which stopped building the
...
edis shared library in the Makefile build, also stop building it in the
CMake build.
Patch by arrowdodger!
llvm-svn: 139108
2011-09-04 23:32:05 +00:00
ada9aa2b98
Complete the removal of FindBison from CMake. Noticed this when browsing
...
some CMake patch backlog...
llvm-svn: 139107
2011-09-04 23:29:12 +00:00
ceb4e6408a
Update the CMake documentation to the correct variables.
...
Patch by arrowdodger!
llvm-svn: 139106
2011-09-04 23:24:13 +00:00
321fb37773
Use Duncan's patch to delete the instructions in reverse order (minus the landingpad and terminator).
...
llvm-svn: 139090
2011-09-04 09:43:36 +00:00
acaad83cd0
The insertion point for the loads is right before the llvm.eh.exception
...
call. The call may be in the same BB as the landingpad instruction. If that's
the case, then inserting the loads after the landingpad inst, but before the
extractvalues, causes undefined behavior.
llvm-svn: 139088
2011-09-04 09:02:18 +00:00
09ade9bb8b
valgrind: Suppress glibc's optiized strcasecmp harder.
...
llvm-svn: 139084
2011-09-03 17:59:31 +00:00
7859d2e148
Use internal storage for command line option.
...
llvm-svn: 139079
2011-09-03 03:45:06 +00:00
7c1d6358a2
Don't reload the values that are already there. The llvm.eh.resume uses the same
...
values that the resume instruction uses.
PR10850
llvm-svn: 139076
2011-09-03 01:38:17 +00:00
2f5420b225
Exclude more arm jit failures pending PR10783.
...
llvm-svn: 139074
2011-09-03 01:08:35 +00:00
07d9914620
Add AVX versions to match AESENC/AESDEC intrinsics. This hopefully ends
...
the cycle of missing AVX counterparts of already present SSE* patterns
llvm-svn: 139073
2011-09-03 00:47:08 +00:00
1d5c2d9227
Add AVX version of a SSE4.1 VPBLENDVB pattern
...
llvm-svn: 139072
2011-09-03 00:47:05 +00:00
212a8c4357
Add AVX versions of SSE4.1 EXTRACTPS patterns
...
llvm-svn: 139071
2011-09-03 00:47:03 +00:00
3d581a36b6
Add AVX versions for SSE4.1 MOVZX* patterns
...
llvm-svn: 139070
2011-09-03 00:47:01 +00:00
6d701fcef0
Add one more AVX pattern for MOVZPQILo2PQI
...
llvm-svn: 139069
2011-09-03 00:46:58 +00:00
9923c51564
Move PUNPCKLQDQ splat pattern close to the instruction definition and
...
duplicate it for AVX mode.
llvm-svn: 139068
2011-09-03 00:46:56 +00:00
96b11f39e2
Add AVX pattern versions for PSHUFB,PSIGN{B,W,D}
...
llvm-svn: 139067
2011-09-03 00:46:54 +00:00
9a0da1e57a
Add AVX versions of MOVZDI2PDI patterns. Use SUBREG_TO_REG to indicate
...
that the AVX versions (even the 128-bit ones) all clear the upper part
of the destination register.
llvm-svn: 139066
2011-09-03 00:46:51 +00:00
903952223a
Enforce subtarget checks in a few places to be explicit when the
...
pattern should be matched
llvm-svn: 139065
2011-09-03 00:46:49 +00:00
521b0cfdc6
Tidy up code moving patterns to their appropriate place!
...
llvm-svn: 139064
2011-09-03 00:46:47 +00:00
aad5e50ded
Add AVX versions of FsMOVAPS and FsMOVAPS. Teach X86InstrInfo how to use
...
it!
llvm-svn: 139063
2011-09-03 00:46:45 +00:00
d893fc92af
Teach X86FastISel to use AVX versions of instructions when possible
...
llvm-svn: 139062
2011-09-03 00:46:42 +00:00
006c9371a1
Fix 80-column and style
...
llvm-svn: 139061
2011-09-03 00:46:40 +00:00
dbb40015ff
Tidy up some SSE/AVX convert intrinsics. Also add an AVX version of
...
OptForSize pattern
llvm-svn: 139060
2011-09-03 00:46:38 +00:00
40d756eacc
Fix a truly heinous bug in DAGCombine related to AssertZext.
...
If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert. The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users. No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem.
Fixes <rdar://problem/10063365>.
llvm-svn: 139059
2011-09-03 00:26:49 +00:00
5423017526
Revert r129875, XFAILing this test for arm, since the fix was reverted.
...
llvm-svn: 139058
2011-09-03 00:14:24 +00:00
1f72dd40c7
Pseudo CMOV instructions don't clobber EFLAGS.
...
The explanation about a 0 argument being materialized as xor is no
longer valid. Rematerialization will check if EFLAGS is live before
clobbering it.
The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.
This causes one less testb instruction to be generated in the cmov.ll
test case.
llvm-svn: 139057
2011-09-02 23:52:55 +00:00
f08354d183
Check for EFLAGS live-out before clobbering it.
...
It is only allowed to clobber EFLAGS at the end of a block if it isn't
live-in to any successor.
llvm-svn: 139056
2011-09-02 23:52:52 +00:00
d0c8a31c8b
Use existing function.
...
llvm-svn: 139055
2011-09-02 23:52:49 +00:00
f347d1d772
Thumb2 parsing and encoding for CBZ/CBNZ.
...
llvm-svn: 139054
2011-09-02 23:46:10 +00:00
34842ceb97
Thumb2 parsing and encoding for BXJ.
...
llvm-svn: 139053
2011-09-02 23:43:09 +00:00
9e55023ca7
Thumb2 parsing and encoding for BIC.
...
llvm-svn: 139052
2011-09-02 23:37:54 +00:00
93e3fd29b2
Thumb2 parsing and encoding for BFI.
...
llvm-svn: 139051
2011-09-02 23:28:46 +00:00
be31448d99
Thumb2 parsing and encoding for BFC.
...
llvm-svn: 139050
2011-09-02 23:25:46 +00:00
a0d34d3b5e
Thumb2 parsing and encoding of B instruction.
...
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
llvm-svn: 139049
2011-09-02 23:22:08 +00:00
67ba2403e8
Attempt to silence known valgrind errors.
...
llvm-svn: 139048
2011-09-02 22:59:34 +00:00
38019e3188
Remove unused variables.
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llvm-svn: 139047
2011-09-02 22:41:25 +00:00
4aa2573748
Try to eliminate the use of the 'unwind' instruction.
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llvm-svn: 139046
2011-09-02 22:41:11 +00:00
f3dd6da7a8
Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel.
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llvm-svn: 139044
2011-09-02 22:33:24 +00:00
a216debb37
Thumb2 parsing and encoding for ASR.
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For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
llvm-svn: 139040
2011-09-02 21:28:54 +00:00
912668d998
Better fix for this testcase. Update it to the new EH scheme entirely.
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llvm-svn: 139039
2011-09-02 21:27:08 +00:00
17706bcffb
Update for new EH stuff. (I'm not sure if this is 100% correct.)
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llvm-svn: 139038
2011-09-02 21:24:17 +00:00
310a448cfe
Test case update for unroll-scev.
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llvm-svn: 139037
2011-09-02 21:21:03 +00:00
bbb226a827
Comment and clarifying assert.
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llvm-svn: 139036
2011-09-02 21:20:46 +00:00
73e6333ce1
No need to get fancy inserting a PHI node when the values are stored in stack
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slots. This fixes a bug where the number of nodes coming into the PHI node may
not equal the number of predecessors. E.g., two or more landingpad instructions
may require a PHI before reaching the eh.exception and eh.selector instructions.
llvm-svn: 139035
2011-09-02 21:17:08 +00:00
09d153eb12
Make RecordVal Name an Init
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Store a RecordVal's name as an Init to allow class-qualified Record
members to reference Records that have Init names. We'll use this to
provide more programmability in how we name defs and their associated
members.
llvm-svn: 139031
2011-09-02 20:12:07 +00:00
5b03f72292
Change X86 disassembly to print immediates values as signed by default. Special
...
case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
2011-09-02 20:01:23 +00:00
05dec8b122
Tidy up. Formatting.
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llvm-svn: 139024
2011-09-02 18:46:15 +00:00
a336e70573
Update comments to reflect reality.
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llvm-svn: 139023
2011-09-02 18:43:33 +00:00
0a57375a28
Tidy up. 80 columns.
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llvm-svn: 139022
2011-09-02 18:43:25 +00:00
370e923434
Thumb2 parsing and encoding for AND (register).
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llvm-svn: 139021
2011-09-02 18:41:35 +00:00
97fe09ad2e
Simplify by using isFullCopy().
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llvm-svn: 139019
2011-09-02 18:18:29 +00:00
4e1d018935
Revert r138826 until PR10834 can be fixed.
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llvm-svn: 139018
2011-09-02 18:15:04 +00:00
2761155203
Thumb2 parsing and encoding for ADD (register).
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llvm-svn: 139017
2011-09-02 18:14:46 +00:00
5c04c62765
Darwin wants ctors/dtors to be ordered the other way round to linux.
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llvm-svn: 139015
2011-09-02 18:07:19 +00:00
54e09b4799
Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
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llvm-svn: 139014
2011-09-02 18:03:03 +00:00
b861b2b475
Tests for Thumb2 AND (immediate) instruction.
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llvm-svn: 139013
2011-09-02 17:44:27 +00:00
63a3a0e010
Extra CHECK-NOT to make sure that GVN transform works properly.
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llvm-svn: 139012
2011-09-02 17:40:39 +00:00
4a31ba3bae
-unroll-scev flag removal
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llvm-svn: 139010
2011-09-02 17:36:14 +00:00
31b941a60d
Enable SCEV-based unrolling by default.
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This changes loop unrolling to use the same mechanism for trip count
computation as indvars. This is a stronger check that tends to unroll
more loops. A very common side-effect is that many single iteration
loops will be removed sooner. The real goal was simply to remove
dependence on canonical IVs.
x86 is break even.
ARM performance changes to expect (+ is good):
External/SPEC/CFP2000/183.equake/183.equake +13%
SingleSource/Benchmarks/Dhrystone/fldry +21%
MultiSource/Applications/spiff/spiff +3%
SingleSource/Benchmarks/Stanford/Puzzle -14%
The Puzzle regression is actually an improvement in loop optimization
that defeats GVN: rdar://problem/10065079.
llvm-svn: 139009
2011-09-02 17:26:28 +00:00
c302f5cce7
Add FIXME. Thumb2 ADR encoding choice is non-trivial.
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llvm-svn: 139008
2011-09-02 17:21:59 +00:00
59a1de1c9d
Return undef value (instead of arbitrary) for wrong or undef index in
...
ConstantVector.
llvm-svn: 139007
2011-09-02 17:01:40 +00:00
057d423e4b
ConstantVector returns arbitrary value for the wrong index.
...
This fixes PR10813.
llvm-svn: 139006
2011-09-02 15:43:43 +00:00
7470fb01d0
Compare type size instead of type _store_ size to make sure that BitCastInst
...
will be valid. This fixes PR10820.
llvm-svn: 139005
2011-09-02 14:57:37 +00:00
f5769c1070
Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.
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llvm-svn: 139004
2011-09-02 10:05:01 +00:00
94ce535647
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
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llvm-svn: 138997
2011-09-02 04:17:54 +00:00
5b49bb6bf5
Perform the upgrading of the old EH to the new EH in a more sane manner.
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Perform the upgrading in steps.
* First, create a map of the invokes to the EH intrinsics.
* Next, take that mapping and determine if the invoke's unwind destination has a
single predecessor. If not, then create a new empty block to hold the new
landingpad instruction.
* Create a landingpad instruction into the uwnind destination. Fill it with the
values from the old selector. Map the old intrinsic calls to the new
landingpad values (there may be multiple landingpad instructions per instrinic
call pairs).
* Go through the old intrinsic calls, create a PHI node when necessary, and then
replace their values with the new values from the landingpad instructions.
* Delete all dead instructions.
* ???
* Profit!
llvm-svn: 138990
2011-09-02 01:30:08 +00:00
723cec7a5f
Update to new EH scheme.
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llvm-svn: 138989
2011-09-02 01:25:11 +00:00
ed96b58bd2
Merge the ARM disassembler header into the implementation file, since it is not externally exposed.
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llvm-svn: 138982
2011-09-01 23:35:51 +00:00
03aadae01f
Fix 80 columns violations.
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llvm-svn: 138980
2011-09-01 23:23:50 +00:00
3767be9aee
Revert r131152, r129796, r129761. This code is currently considered
...
to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.
llvm-svn: 138977
2011-09-01 23:07:08 +00:00
6397051ece
Don't drop alignment info on local common symbols.
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- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm
Based on a patch by NAKAMURA Takumi.
Fixes PR9337, PR9483 and PR10128.
llvm-svn: 138976
2011-09-01 23:04:27 +00:00
d7776ed030
Null-initialize to shut up -Wuninitialized warnings.
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llvm-svn: 138974
2011-09-01 22:27:41 +00:00
5ada2a7e27
Fix apparent build error caused by r138948 on certain versions of GCC with -Werror. Sorry for the inconvenience.
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llvm-svn: 138973
2011-09-01 22:01:14 +00:00
a3ba6d3b80
Reduce indentation. No functionality change.
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llvm-svn: 138968
2011-09-01 21:29:49 +00:00
bf8280ff27
Change worklist driven deletion to be an iterative process.
...
Duncan noticed this!
llvm-svn: 138967
2011-09-01 21:28:33 +00:00
4028a51c74
Fix test; sorry for any inconvenience.
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llvm-svn: 138966
2011-09-01 21:25:42 +00:00
71f5c2f158
Fix an issue with the IR sink pass found by inspection. (I'm not sure anyone is actually using this, but might as well fix it since I found the issue.)
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llvm-svn: 138965
2011-09-01 21:21:24 +00:00
cc6e92892f
Add missing newline.
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llvm-svn: 138964
2011-09-01 21:20:11 +00:00
2e2d75fb97
Fix the build for us -Werror users.
...
Remove broken emacs mode major notation marking a C++ file as C.
No functionality change.
llvm-svn: 138963
2011-09-01 21:09:04 +00:00
b053ac7e0c
Make isSafeToSpeculativelyExecute() return the right answer for some new instructions. Found by inspection; not sure what practical impact, if any, this has.
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llvm-svn: 138962
2011-09-01 21:03:03 +00:00
c032617581
XFAIL this test on arm until the backend is fixed.
...
llvm-svn: 138955
2011-09-01 18:40:03 +00:00
0f6ff8cb2b
This test depends on cmov being available.
...
llvm-svn: 138954
2011-09-01 18:40:01 +00:00
5dc87d0f4d
Permit remat of partial register defs when it is safe.
...
An instruction may define part of a register where the other bits are
undefined. In that case, it is safe to rematerialize the instruction.
For example:
%vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>
The extra <imp-def> operand indicates that the instruction does not read
the other parts of the virtual register, so a remat is safe.
This patch simply allows multiple def operands for the virtual register.
It is MI->readsVirtualRegister() that determines if we depend on a
previous value so remat is impossible.
llvm-svn: 138953
2011-09-01 18:27:51 +00:00
f6d5d60f99
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
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llvm-svn: 138952
2011-09-01 18:22:13 +00:00
f61d1c072e
Fix vbroadcast matching logic to early unmatch if the node doesn't have
...
only one use. Fix PR10825.
llvm-svn: 138951
2011-09-01 18:15:06 +00:00
db4ce60328
Fix up r137380 based on post-commit review by Jim Grosbach.
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llvm-svn: 138948
2011-09-01 18:02:14 +00:00
35d240f9e8
t2Bcc is allowed to have a predicate without a preceding IT instruction.
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llvm-svn: 138946
2011-09-01 17:47:45 +00:00
e417273fce
Revert r138794, "Do not try to rematerialize a value from a partial definition."
...
The problem is fixed for all register allocators by r138944, so this
patch is no longer necessary.
<rdar://problem/10032939>
llvm-svn: 138945
2011-09-01 17:25:18 +00:00
6357fa2f06
Prevent remat of partial register redefinitions.
...
An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.
This was fixed for the inline spiller in r138794. This patch fixes the
problem for all register allocators, and includes a small test case.
<rdar://problem/10032939>
llvm-svn: 138944
2011-09-01 17:18:50 +00:00
90da66bb69
Teach MachineLICM reg pressure tracking code to deal with MVT::untyped. Sorry, I can't come up with a small test case. rdar://10043690
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llvm-svn: 138934
2011-09-01 01:45:00 +00:00
185d377597
Update to new EH scheme.
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llvm-svn: 138933
2011-09-01 01:28:25 +00:00
a617c32745
Resubmit with fix. Properly remove the instructions except for landingpad, which should be removed only when its invokes are.
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llvm-svn: 138932
2011-09-01 01:28:11 +00:00
9f7cf20e60
Submitted this too early.
...
llvm-svn: 138931
2011-09-01 01:18:33 +00:00
2d1f11f743
Don't DCE the landingpad instruction.
...
The landingpad instruction can be removed only when its invokes are removed.
llvm-svn: 138930
2011-09-01 01:16:58 +00:00
d33e3007fa
Update to new EH scheme.
...
llvm-svn: 138928
2011-09-01 01:08:21 +00:00
3b17c1b48d
Update to new EH scheme.
...
llvm-svn: 138927
2011-09-01 01:02:41 +00:00
e88632d667
Update some tests to the new EH scheme.
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llvm-svn: 138925
2011-09-01 00:58:03 +00:00
832a6a1909
PreRA scheduler should avoid cloning compares.
...
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261
llvm-svn: 138924
2011-09-01 00:54:31 +00:00
b9a899995d
Don't forget to add the landingpad and resume instructions to the InstructionList.
...
This was found via a nightly build of 483.xalancbmk.
llvm-svn: 138923
2011-09-01 00:50:20 +00:00
1d3c137839
Thumb2 assembly parsing and encoding for ADD(immediate).
...
llvm-svn: 138922
2011-09-01 00:28:52 +00:00
17847ae757
Fixup for functions that return a bool.
...
llvm-svn: 138918
2011-08-31 23:49:05 +00:00
080f40a49d
Reenable test.
...
llvm-svn: 138916
2011-08-31 23:08:05 +00:00
54b91028f0
Revert accidental commit
...
llvm-svn: 138915
2011-08-31 23:07:46 +00:00
c472975fd9
Disable this test until Bill fixes it properly.
...
llvm-svn: 138914
2011-08-31 23:03:30 +00:00
e1995f2566
Static relocation model Thumb jump table interworking.
...
Make sure the low bit of the PC is set when loading an address directly
for jump tables in static relocation model.
llvm-svn: 138912
2011-08-31 22:23:09 +00:00
4af0aa98d5
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
...
llvm-svn: 138910
2011-08-31 22:00:41 +00:00
5624fe0cff
Update to new EH scheme.
...
llvm-svn: 138908
2011-08-31 21:50:07 +00:00
e336599f6d
Update to new EH scheme.
...
llvm-svn: 138906
2011-08-31 21:44:24 +00:00
55fb73a6e0
Remove old declare statements.
...
llvm-svn: 138905
2011-08-31 21:41:20 +00:00
22055c713f
Update more tests to the new EH scheme.
...
llvm-svn: 138904
2011-08-31 21:40:15 +00:00
d4e871404d
Update more tests to the new EH scheme.
...
llvm-svn: 138903
2011-08-31 21:39:05 +00:00
293c31b81c
Add tests for the transformations SCCP can do on atomic loads and stores (which are safe without any modifications).
...
llvm-svn: 138902
2011-08-31 21:37:06 +00:00
7df940d660
Fix Size Typing
...
Stores sizes as uint64_t to avoid possible truncation.
llvm-svn: 138901
2011-08-31 21:34:20 +00:00
c4c24f03e9
Revert r138894. This was failing on cmake-clang-i686-msvc10.
...
llvm-svn: 138900
2011-08-31 21:20:25 +00:00
99bc84662f
Thumb2 t2Bcc should encode as t2B when condition is 'always'.
...
llvm-svn: 138898
2011-08-31 21:17:31 +00:00
a0d85139e5
Move more code around and duplicate AVX patterns: MOVHPS and MOVLPS
...
llvm-svn: 138897
2011-08-31 21:15:32 +00:00
Nadav Rotem